Detailed Action
The instant application having Application No. 17453,715 has a total of 19 claims pending in the application; there are 3 independent claims and 16 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 5/22/25. Claims 1-15 and 17-20 are pending.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-13, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hyde et al. (U.S. Patent Application Publication No. 2014/0136915), herein referred to as Hyde et al., in view of Linstadt (U.S. Patent Application Publication No. 2015/0254192), herein referred to as Linstadt and in view of Luck (U.S. Patent Application Publication No. 2018/0190365), herein referred to as Luck.
Referring to claim 1, Hyde et al. disclose as claimed, an apparatus, comprising: a plurality of arrays of memory cells formed on a single memory chip (see para. 35-36, where the memory device can include two or more segments of any non-volatile memory type. Also see para. 111), each array of the plurality of arrays of memory cells configured to receive data values from a data file such that data values are redundantly stored over the plurality of arrays of memory cells (see para. 163 and 171, where data may be copied and stored redundantly); and comparator circuitry configured to: compare the data files redundantly stored over the plurality of arrays to determine whether there is a match among the deserialized data files stored by more than a half of the plurality of arrays (see para. 166 and para. 60-62, where there is comparator circuitry for comparing selected ones of a plurality of copies and determining match of more than half); and output the matched data file stored in one array of the plurality of arrays (see para. 171-172, where an error may be corrected using the matched copies, and therefore output and stored).
Hyde et al. disclose the claimed invention except for a deserializer configured to: receive a data file comprising k data values via a k-bit data bus; and the deserializer configured to deserialize the data file into n portions of k data values; each array of the plurality of arrays of memory cells configured to receive n portions of k data values that are deserialized at the deserializer via a respective bus of a plurality of kn-bit data buses in parallel such that the n portions of the deserialized data file each having k data values are redundantly stored over the plurality of arrays of memory cells; and where the data values are redundantly stored in parallel.
However, Linstadt discloses a deserializer configured to: receive a data file comprising k data values via a k-bit data bus (see para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus); and the deserializer configured to deserialize the data file into n portions of k data values (see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus); each array of the plurality of arrays of memory cells configured to receive n portions of k data values that are deserialized at the deserializer via a respective bus of a plurality of kn-bit data buses in parallel such that the n portions of the deserialized data file each having k data values are redundantly stored over the plurality of arrays of memory cells (see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 bit wide bus. See para. 23, where the data bits are transferred in parallel, and see para. 29-31, where the transfers take place via one or more data buses 212 and 214, which would be a parallel transfer. Also see fig. 2A and 2B showing that each data bit is connected to different buses going to the memory arrays, and therefore the data would be transferred in parallel).
Hyde et al. and Linstadt are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Linstadt, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise a deserializer configured to: receive a data file comprising k data values via a k-bit data bus; and the deserializer configured to deserialize the data file into n portions of k data values; each array of the plurality of arrays of memory cells configured to receive n portions of k data values that are deserialized at the deserializer via a respective bus of a plurality of kn-bit data buses in parallel such that the n portions of the deserialized data file each having k data values are redundantly stored over the plurality of arrays of memory cells, as taught by Linstadt in order to allow for smaller chunks of data that are easily transmittable and then assembling or deserializing the data for storage.
Hyde et al. and Linstadt disclose the claimed invention except for where the data values are redundantly stored in parallel.
However, Luck discloses where the data values are redundantly stored in parallel (see fig. 2c, where a memory controller may mirror writes to an original block and reserved block of memory. Also see para. 31, where data may be written to both locations in parallel).
Hyde et al. and Luck are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Luck, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise where the data values are redundantly stored in parallel, as taught by Luck in order to allow for faster storage across the arrays. It is well known in the art to redundantly store data in parallel and it would be obvious to implement this method with Hyde et al. and Linstadt.
As to claim 2, Hyde et al., Linstadt and Luck also disclose the apparatus of claim 1, wherein the comparator circuitry comprises a number of comparator components each coupled to a respective set of two arrays of the plurality and configured to determine a match between the data files redundantly stored over the two arrays of the respective set (see Hyde et al., para. 34, where the control logic may compare the plurality of copies of data. Also see para. 62).
As to claim 3, Hyde et al., Linstadt and Luck also disclose the apparatus of claim 2, wherein the comparator circuitry further comprises a validation component that is coupled to at least a portion of the number of comparator components, and wherein the comparator circuitry is configured to determine the match among the deserialized data file stored by more than a half of the plurality of arrays using the validation component (see Hyde et al., para. 62, where a majority rule may be used by the comparator to determine the correct data).
As to claim 4, Hyde et al., Linstadt and Luck also disclose the apparatus of claim 1, further comprising a serializer coupled to the comparator circuitry (see Linstadt, fig. 2b, showing a serializer coupled to the memory device and the controller and would therefore be coupled to the comparator circuitry when combined with Hyde et al.), and wherein: the comparator circuitry is configured to provide the matched data file stored in the one array to the serializer (see Hyde et al., para. 171, where data may be corrected based on the matched copies); and the serializer is configured to reconstruct the received data file having the n portions into a single sequence of k data values (see Linstadt, para. 29-31, where the serializer may deserialize and serialize data).
As to claim 5, Hyde et al., Linstadt and Luck also disclose the apparatus of claim 1, wherein one array of the plurality of arrays is configured to receive the data file corresponding to the n portions of k data values via a kn-bit data bus (see Linstadt, fig. 2b, showing an array receiving deserialized data as explained in claim 1. Hyde discloses where data may be redundantly copied to multiple arrays).
As to claim 6, Hyde et al., Linstadt and Luck also disclose the apparatus of claim 1, wherein each array of the plurality of arrays is configured to receive the data file corresponding to the n portions of k data values via a separate and respective kn-bit data bus and wherein a copy function is subsequently performed to copy the data file stored in the one array to the other arrays of the plurality of arrays (see Hyde et al., para. 163, where data can be copied for redundant storage).
Referring to claim 7, Hyde et al. disclose as claimed, a system, comprising: a plurality of arrays of memory cells formed on a single memory chip (see para. 35-36, where the memory device can include two or more segments of any non-volatile memory type. Also see para. 111), wherein a data file is redundantly stored over the plurality of arrays (see para. 163 and 171, where data may be copied and stored redundantly) comparator circuitry coupled to the plurality of arrays; wherein the comparator circuitry is configured to: compare the data files redundantly stored over the plurality of arrays; and access, in response to a determination of a match among the data files redundantly stored over at least a half of the plurality of arrays (see para. 166 and para. 60-62, where there is comparator circuitry for comparing selected ones of a plurality of copies and determining match of more than half), one array of the plurality of arrays storing the matched data file to output the matched data file (see para. 171-172, where an error may be corrected using the matched copies, and therefore output and stored).
Hyde et al. disclose the claimed invention except for a deserializer configured to: receive a data file comprising k data values via a k-bit data bus; and the deserializer configured to deserialize the data file into n portions of k data values; a data file is received to each array of the plurality of arrays of memory cells via a respective bus of a plurality of kn-bit data buses in parallel; where the data file is stored in a deserialized form and as n portions each having k data values; and a serializer is coupled to the comparator; and where the data file having n portions is sent to the serializer wherein the serializer is configured to reconstruct the data file into a single sequence of k data values; and where the data values are redundantly stored in parallel.
However, Linstadt discloses a deserializer configured to: receive a data file comprising k data values via a k-bit data bus (see para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus); and the deserializer configured to deserialize the data file into n portions of k data values (see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus); a data file is received to each array of the plurality of arrays of memory cells via a respective bus of a plurality of kn-bit data buses in parallel (See para. 23, where the data bits are transferred in parallel, and see para. 29-31, where the transfers take place via one or more data buses 212 and 214, which would be a parallel transfer. Also see fig. 2A and 2B showing that each data bit is connected to different buses going to the memory arrays, and therefore the data would be transferred in parallel); where the data file is stored in a deserialized form and as n portions each having k data values (see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 bit wide bus); and a serializer is coupled to the comparator (see fig. 2b, where the serializer is coupled to the memory device and the controller. When combined with Hyde, which has a comparator in a memory device, the serializer would be coupled to the comparator); and where the data file having n portions is sent to the serializer wherein the serializer is configured to reconstruct the data file into a single sequence of k data values (see Linstadt, para. 29-31, where the serializer may deserialize and serialize data).
Hyde et al. and Linstadt are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Linstadt, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise a deserializer configured to: receive a data file comprising k data values via a k-bit data bus; and the deserializer configured to deserialize the data file into n portions of k data values; where a data file is received to each array of the plurality of arrays of memory cells via a respective bus of a plurality of kn-bit data buses in parallel; the data file is stored in a deserialized form and as n portions each having k data values; and a serializer is coupled to the comparator; and where the data file having n portions is sent to the serializer wherein the serializer is configured to reconstruct the data file into a single sequence of k data values. , as taught by Linstadt in order to allow for smaller chunks of data that are easily transmittable and then assembling or deserializing the data for storage.
Hyde et al. and Linstadt disclose the claimed invention except for where the data values are redundantly stored in parallel.
However, Luck discloses where the data values are redundantly stored in parallel (see fig. 2c, where a memory controller may mirror writes to an original block and reserved block of memory. Also see para. 31, where data may be written to both locations in parallel).
Hyde et al. and Luck are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Luck, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise where the data values are redundantly stored in parallel, as taught by Luck in order to allow for faster storage across the arrays. It is well known in the art to redundantly store data in parallel and it would be obvious to implement this method with Hyde et al. and Linstadt.
As to claim 8, Hyde et al., Linstadt and Luck also disclose the system of claim 7, wherein the comparator circuitry is coupled directly to a functionality or indirectly to the functionality through the serializer (see Linstadt, fig. 2b, where the serializer is part of the memory device and coupled to the memory, logic and controller. See Hyde, fig. 1a, where the control logic is part of the memory device, and therefore when combined, they would be coupled together).
As to claim 10, Hyde et al., Linstadt and Luck also disclose the system of claim 9, wherein the serializer is configured to provide, in response to the determination of a match among the data files redundantly stored over at least the half of the plurality of arrays, the serialized data file having k data values to the functionality without providing the notification (see Hyde et al., para. 62, where if there is a match, an error may be corrected without providing a notification).
As to claim 11, Hyde et al., Linstadt and Luck also disclose the system of claim 8, wherein the functionality is formed on a different memory chip than the single memory chip (see Linstadt, fig. 2b, where the controller is separate from the memory chip and would therefore have a separate smaller memory as well as the logic functionality).
As to claim 12, Hyde et al., Linstadt and Luck also disclose the system of claim 7, wherein the serializer is formed on the single memory chip (see Linstadt, fig. 2b, where the serializer is on the memory chip).
Referring to claim 13, Hyde et al. disclose as claimed, a system, comprising: a plurality of arrays of memory cells (see para. 35-36, where the memory device can include two or more segments of any non-volatile memory type. Also see para. 111); and comparator circuitry coupled to the plurality of arrays of memory cells and configured to: compare the data files redundantly stored over the plurality of arrays to determine whether there is a match among the data files stored by more than a half of the plurality of arrays (see para. 166 and para. 60-62, where there is comparator circuitry for comparing selected ones of a plurality of copies and determining match of more than half); and output the matched data file stored in one array of the plurality of arrays (see para. 171-172, where an error may be corrected using the matched copies, and therefore output and stored).
Hyde et al. disclose the claimed invention except for a deserializer coupled to the plurality of arrays of memory cells and configured to: receive a data file having k data values via a k-bit data bus; deserialize the data file into a number of n portions each having k data values; and provide, via a respective bus of a plurality of kn-bit data buses, the deserialized data file to each one the plurality of array of memory cells in parallel such that the deserialized data file is redundantly stored over the plurality of arrays; and where the data values are redundantly stored in parallel.
However, Linstadt discloses a deserializer coupled to the plurality of arrays of memory cells and configured to: receive a data file having k data values via a k-bit data bus (see para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus); deserialize the data file into a number of n portions each having k data values; and provide, via a respective bus of a plurality of kn-bit data buses, the deserialized data file to each one the plurality of array of memory cells in parallel such that the deserialized data file is redundantly stored over the plurality of arrays (see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus. See para. 23, where the data bits are transferred in parallel, and see para. 29-31, where the transfers take place via one or more data buses 212 and 214, which would be a parallel transfer. Also see fig. 2A and 2B showing that each data bit is connected to different buses going to the memory arrays, and therefore the data would be transferred in parallel);
Hyde et al. and Linstadt are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Linstadt, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise a deserializer coupled to the plurality of arrays of memory cells and configured to: receive a data file having k data values via a k-bit data bus; deserialize the data file into a number of n portions each having k data values; and provide, via a respective bus of a plurality of kn-bit data buses, the deserialized data file to each one the plurality of array of memory cells in parallel such that the deserialized data file is redundantly stored over the plurality of arrays, as taught by Linstadt in order to allow for smaller chunks of data that are easily transmittable and then assembling or deserializing the data for storage.
Hyde et al. and Linstadt disclose the claimed invention except for where the data values are redundantly stored in parallel.
However, Luck discloses where the data values are redundantly stored in parallel (see fig. 2c, where a memory controller may mirror writes to an original block and reserved block of memory. Also see para. 31, where data may be written to both locations in parallel).
Hyde et al. and Luck are analogous art because they are from the same field of endeavor of memory devices (see Hyde et al., abstract and Luck, abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde to comprise where the data values are redundantly stored in parallel, as taught by Luck in order to allow for faster storage across the arrays. It is well known in the art to redundantly store data in parallel and it would be obvious to implement this method with Hyde et al. and Linstadt.
As to claim 15, Hyde et al., Linstadt and Luck also disclose the system of claim 13, wherein the deserializer is configured to receive the data file via a k-bit data bus (see Linstadt, para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus ).
As to claim 17, Hyde et al., Linstadt and Luck also disclose the system of claim 13, wherein the deserialized data file is redundantly stored over a portion of the plurality of arrays and a size of the portion of the plurality of arrays is determined based on a size of the data file (see Linstadt, para. 29, where the memory comprises an array to store data and when the memory is stored, it would be the size of the data file and take up that space in the memory array).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hyde et al. in view of Linstadt and Luck and also in view of Kentley et al. (U.S. Patent Application Publication No. 2017/0123421), herein referred to as Kentley et al.
As to claim 14, Hyde et al., Linstadt and Luck also disclose the system of claim 13, wherein the system further comprises a memory, the memory storing instructions executable for a failover functionality for execution responsive to determination of no match or a mismatch among the deserialized data file stored by more than the half of the plurality of arrays (see Hyde et al., para. 60-62, 163 and 171-17, where the redundantly stored copies may be encrypted and reconstructed/corrected depending on if there is a match and/or error in one of the copies).
Hyde et al. and Linstadt disclose the claimed invention except for the plurality of arrays of memory cells is formed on an autonomous vehicle
However, Kentley et al. disclose where redundant systems are used on autonomous vehicles (see para. 68, 78, and para. 177, where communications and sensors on autonomous vehicles incorporate redundancy)
Hyde et al. and Kentley et al. are analogous art because they are from the same field of endeavor of redundancy and verification (see Hyde et al., abstract, and Kentley et al., para. 68, 78 and 177, regarding redundancy and verification).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde et al. to comprise where redundant systems are used on autonomous vehicles, as taught by Kentley et al., in order to utilize the redundant system in a practical application. It is well known in the art that autonomous vehicles use redundant systems, and it would be obvious to combine Hyde et al.’s technology in an autonomous vehicle.
Claims 9 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hyde et al. in view of Linstadt and Luck and also in view of Kim (U.S. Patent Application Publication No. 2016/0300625), herein referred to as Kim.
As to claim 9, Hyde et al., Linstadt and Luck disclose the claimed invention except for the system of claim 8, wherein the comparator circuitry is configured to provide, in response to a determination of no match among the data files redundantly stored over the plurality of arrays, a notification directly to the functionality.
However, Kim discloses wherein the comparator circuitry is configured to provide, in response to a determination of no match among the data files redundantly stored over the plurality of arrays, a notification directly to the functionality (see para. 51, where a comparison result may be outputted).
Hyde et al. and Kim are analogous art because they are from the same field of endeavor of redundancy and verification (see Hyde et al., abstract, and Kim, abstract, regarding redundancy and verification).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde et al. to comprise wherein the comparator circuitry is configured to provide, in response to a determination of no match among the data files redundantly stored over the plurality of arrays, a notification directly to the functionality, as taught by Kim., in order to notify of a failure. In addition, a failure notification on a failed read/write/command is common and would be obvious to implement with Hyde et al. and Linstadt.
As to claim 18, Hyde et al., Linstadt and Luck disclose the claimed invention except for the system of claim 13, wherein each array of the plurality of arrays corresponds to a different bank group, each different bank group having a plurality of memory banks formed on a single memory chip.
However, Kim discloses wherein each array of the plurality of arrays corresponds to a different bank group, each different bank group having a plurality of memory banks formed on a single memory chip (see fig. 2, where the first and second memory array are half banks on the same memory chip, and would each constitute a different bank group. See para. 122, where the memory device may be any standard memory type and memory module).
Hyde et al. and Kim are analogous art because they are from the same field of endeavor of redundancy and verification (see Hyde et al., abstract, and Kim, abstract, regarding redundancy and verification).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde et al. to comprise wherein each array of the plurality of arrays corresponds to a different bank group, each different bank group having a plurality of memory banks formed on a single memory chip, as taught by Kim., in order to organize the arrays and allow for faster parallel access.
As to claim 19, Hyde et al., Linstadt and Luck disclose the claimed invention except for the system of claim 13, wherein each array of the plurality of arrays corresponds to a different memory bank formed on a single memory chip.
However, Kim discloses wherein each array of the plurality of arrays corresponds to a different memory bank formed on a single memory chip (see fig. 2, where the first and second memory array are half banks on the same memory chip. See para. 122, where the memory device may be any standard memory type and memory module, and could therefore use full banks instead of half banks).
Hyde et al. and Kim are analogous art because they are from the same field of endeavor of redundancy and verification (see Hyde et al., abstract, and Kim, abstract, regarding redundancy and verification).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde et al. to comprise wherein each array of the plurality of arrays corresponds to a different memory bank formed on a single memory chip, as taught by Kim., in order to organize the arrays and allow for faster parallel access.
As to claim 20, Hyde et al., Linstadt and Luck disclose the claimed invention except for the system of claim 13, wherein each array of the plurality of arrays corresponds to a different section of a single memory bank formed on a single memory chip.
However, Kim discloses wherein each array of the plurality of arrays corresponds to a different section of a single memory bank formed on a single memory chip (see fig. 2, where the first and second memory array are half banks on the same memory chip).
Hyde et al. and Kim are analogous art because they are from the same field of endeavor of redundancy and verification (see Hyde et al., abstract, and Kim, abstract, regarding redundancy and verification).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyde et al. to comprise wherein each array of the plurality of arrays corresponds to a different section of a single memory bank formed on a single memory chip, as taught by Kim., in order to organize the arrays and a more compact form with a smaller footprint.
Response to Arguments
Applicant's arguments filed 5/22/25 have been fully considered but they are not persuasive.
Applicant argues with regards to Linstadt that operating the 4-bit data link DQ[3:0] in parallel does not necessarily indicate storing deserialized data in parallel to different memory devices. Applicant argues that the buses 214 used in Linstadt are not used for transferring the deserialized data to different places redundantly. However, Linstadt was not cited for a redundant parallel transfer. Linstadt does teach deserializing the data (see Linstadt, para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus. Also see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus). Linstadt is being combined with Hyde and Luck, which both teach redundant storage of data. Hyde, para. 35-36 teaches storing redundant portions of memory and where the two redundant portions may be on two or more different memory segments or devices. Luck teaches where the data values are redundantly stored in parallel (see Luck, fig. 2c, where a memory controller may mirror writes to an original block and reserved block of memory. Also see para. 31, where data may be written to both locations in parallel).
Applicant further argues that Luck does not disclose and is not relevant to serializing or deserializing data and does not disclose or imply a deserializer configured to receive a data file comprising k data values via a k-bit data bus. Luck is not being cited for deserializing data. It is being combined with Linstadt, which does teach a deserializer configured to receive a data file comprising k data values via a k-bit data bus (see Linstadt, para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus. Also see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus).
Applicant further argues that Hyde, Linstadt and Luck do not teach or suggest a structural characteristic (bus width) of buses coupled to both ends of the deserializer which enables parallel writing of redundant data to the multiple memory arrays. Linstadt teaches a deserializer with bus width of buses coupled to both ends of the deserializer (see Linstadt, para. Para. 28-31 and fig. 2B, where the deserializer receives a data file comprising 4 data values via a 4-bit data bus. Also see para. 30-31 and fig. 2B, showing several arrays of memory, receiving data from a 4 bit data link DQ and the serializer deserializes the data to multiplexer 204 in a 256 bit wide data bus. Therefore, the file or piece of data would be broken up into 64 or n portions and then sent over the 256 wide bus), and it is being combined with Luck which does teach parallel writing of redundant data (see Luck, fig. 2c, where a memory controller may mirror writes to an original block and reserved block of memory. Also see para. 31, where data may be written to both locations in parallel).
CLOSING COMMENTS
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chu et al. (U.S. Patent Application Publication No. 2019/0132555) disclose a deserializer storing redundant data in parallel to two different embedded control units.
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-15 and 17-20 stand rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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