Remarks
Claims 1-20 are pending.
Claims 11-19 are withdrawn from consideration, as noted below.
Claims 1-10 and 20 are rejected below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, claims 1-10 and 20, in the reply filed on 5/9/2024 is acknowledged. The traversal is on the ground(s) that invention II has been amended to be dependent from invention I. This is not found persuasive because they are still distinct inventions, as specified in the restriction requirement dated 4/12/2024 and not argued.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/9/2024.
MPEP 821.04 discusses rejoinder, which may apply when a non-elected invention depends from an elected invention and the elected invention is determined to be allowable.
Claim Objections
Claim 6 is objected to because of the following informalities: Claim 6 states “RISC-V”, which includes an acronym which is not defined in the claim. However, the first time an acronym is set forth in the claims, it must be fully defined. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claims do not include any physical components. However, in order to be statutory as a machine, the claim must distinguish itself by physical components. Claim 1 only has domains and control channels, and all of these could simply be virtual entities (e.g., software or other virtual entities). None of claims 2-10 fix this issue and they are rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-7, 9, and 20 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Wachendorf (U.S. Patent 9,892,284).
Regarding Claim 1,
Wachendorf discloses a processor configured to provide isolation of software executing in one or more execution domains, the processor comprising:
An isolation domain comprising a highest priority hardware thread executed by the processor and configured to access an entire physical address space of the processor, all control/status registers, all hardware configuration registers, and secure system resources (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, line 65 to Column 5, line 38; and associated figures; this domain may be the entire system or any subset thereof (perhaps the combination of all trusted threads, all trusted and untrusted threads, etc.) that includes a trusted thread and can access all memory, registers, peripherals, secure resources, such as crypto resources, etc., for example);
One or more execution domains, wherein (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; other threads that do not have access to everything, for example);
Each execution domain comprises a thread executed by the processor with a lower priority than the highest priority hardware thread of the isolation domain (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; untrusted threads, for example);
Each execution domain is configured to access an assigned subset of the physical address space and access an assigned subset of the control/status registers, but is unable to access any of the secure system resources (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; memory/registers split between the untrusted threads and no access to secure resources, certain peripherals, etc., for example);
Each assigned subset of the physical address space comprises less than the entire physical address space (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; portion of memory, for example); and
Each assigned subset of the control/status registers comprises less than the entire control/status registers (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; portion of registers, for example); and
A corresponding control channel coupling each execution domain with the isolation domain, each corresponding control channel configured to provide one or more of interrupt routing, reset control, and address space control, wherein each corresponding control channel is configured exclusively by the isolation domain (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; any channel between them, such as in controlling of the untrusted threads, triggering trusted code from untrusted code (which allows access to trusted code by trusted thread at the request of the untrusted thread, thus controlling the address space), ensuring access only to appropriate portions of memory, etc., for example).
Regarding Claim 20,
Claim 20 is a system claim that corresponds to method claim 1 and is rejected for the same reasons. Claim 20 also includes a memory coupled to the processor and a peripheral coupled to the processor, wherein the peripheral is accessible only to the isolation domain, met by Wachendorf’s memory and peripherals as shown, for example, in Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 5, lines 15-38; and associated figures.
Regarding Claim 2,
Wachendorf discloses that the address space control of the corresponding control channel is configured to provide access to a region of memory in the physical address space to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures).
Regarding Claim 5,
Wachendorf discloses that the one or more execution domains are configured to communicate a service request to the isolation domain by generating an event to activate the highest priority hardware thread (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; ITC communications to run trusted thread on behalf of untrusted application, for example); and
The highest priority hardware thread is configured to respond to the service request (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; performing of such, returning control, etc., for example).
Regarding Claim 6,
Wachendorf discloses that the service request comprises one of an environment call instruction when the processor comprises a RISC-V processor or a system call instruction equivalent to the environment call instruction when the processor comprises a type of processor other than a RISC-V processor (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; request from untrusted code to execute trusted code, for example).
Regarding Claim 7,
Wachendorf discloses that the service request comprises a custom service request instruction (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; the above is customized to what is being requested, for example).
Regarding Claim 9,
Wachendorf discloses that the isolation domain is configured to control which of the one or more execution domain threads executes by the processor (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, line 65 to Column 5, line 38; and associated figures; the system including the trusted thread(s) controls execution, for example).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Hokenek (U.S. Patent Application Publication 2004/0073910).
Regarding Claim 3,
Wachendorf does not explicitly disclose that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains.
Hokenek, however, discloses that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Paragraphs 11, 12, 15, 49, 58, 59, 62-70, and associated figures; interrupts are routed based on thread identifiers associated therewith, so only those interrupts directed to a particular thread go to that particular thread, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt techniques of Hokenek into the multithreaded system of Wachendorf in order to allow the system to set and determine which interrupts are directed to which threads, to properly route interrupts between threads, and/or to provide a low latency, low overhead mechanism for delivering and servicing cross thread interrupts in a multithreaded processor.
Regarding Claim 8,
Wachendorf does not appear to explicitly disclose that the service request comprises one or more inter-context communication flag bits.
Hokenek, however, discloses that the service request comprises one or more inter-context communication flag bits (Exemplary Citations: for example, Abstract, Paragraphs 11, 12, 15, 49, 58, 59, 62-70, and associated figures; flag bits used for inter-thread communications, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt techniques of Hokenek into the multithreaded system of Wachendorf in order to allow the system to set and determine which interrupts are directed to which threads, to properly route interrupts between threads, and/or to provide a low latency, low overhead mechanism for delivering and servicing cross thread interrupts in a multithreaded processor.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Codrescu (U.S. Patent Application Publication 2007/0088938).
Regarding Claim 3,
Wachendorf does not explicitly disclose that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains.
Codrescu, however, discloses that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Paragraphs 28-31, 39, 40, and associated figures; only sending certain interrupts or types of interrupts to each thread, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt control techniques of Codrescu into the multithreaded system of Wachendorf in order to allow the system to efficiently manage interrupts, to provide for different types of interrupts to be handled in different ways, to allow for resetting of threads, and/or to increase security in the system.
Regarding Claim 4,
Wachendorf does not explicitly disclose that the corresponding control channel is configured to reset an execution domain of the one or more execution domains, without requiring reset of any other execution domains of the one or more execution domains, by applying a reset vector to the execution domain using the reset control of the corresponding control channel.
Codrescu, however, discloses that the corresponding control channel is configured to reset an execution domain of the one or more execution domains, without requiring reset of any other execution domains of the one or more execution domains, by applying a reset vector to the execution domain using the reset control of the corresponding control channel (Exemplary Citations: for example, Abstract, Paragraphs 28-31, 39, 40, and associated figures; resetting one thread using reset vector, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt control techniques of Codrescu into the multithreaded system of Wachendorf in order to allow the system to efficiently manage interrupts, to provide for different types of interrupts to be handled in different ways, to allow for resetting of threads, and/or to increase security in the system.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Kang (U.S. Patent Application Publication 2008/0040579).
Regarding Claim 10,
Wachendorf does not explicitly disclose that the isolation domain is configured to select which of the one or more execution domain threads is executed by the processor using a round robin context switching determined by one of a time period or a set number of instructions.
Kang, however, discloses that the isolation domain is configured to select which of the one or more execution domain threads is executed by the processor using a round robin context switching determined by one of a time period or a set number of instructions (Exemplary Citations: for example, Paragraphs 39, 57, 65, 66, 68, 70, and associated figures; round robin switching, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the thread switching techniques of Kang into the multithreaded system of Wachendorf in order to allow the system to set how many clock cycles each thread can run for, to allow for interrupts and exceptions to be taken into account for thread switching, to ensure that a single thread can’t take all processing resources, and/or to ensure fairness in processor usage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey D Popham whose telephone number is (571)272-7215. The examiner can normally be reached Monday through Friday 9:00-5:30.
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/Jeffrey D. Popham/Primary Examiner, Art Unit 2432
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