Remarks
Claims 1-20 are pending.
Claims 11-19 remain withdrawn from consideration.
Claims 1-10 and 20 are rejected below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Applicant notes (e.g., page 10 of the response dated 1/10/2025) that “claim 1 recites ‘a processor’, which is a physical component” and also notes that “all of” “an entire physical address space of the processor, all control/status registers, all hardware configuration registers, and secure system resources” “are physical components”.
Response to Arguments
Applicant's arguments filed 1/10/2025 have been fully considered but they are not persuasive.
Applicant continues to argue the restriction, despite the restriction being made final already. Here is a copy of the restriction:
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-10 and 20, drawn to virtual machine isolation, classified in G06F2009/45587.
II. Claims 11-19, drawn to handling requests in a SOEMT processor, classified in G06F9/3009.
The inventions are independent or distinct, each from the other because:
Inventions I and II are related as combination and subcombination. Inventions in this relationship are distinct if it can be shown that (1) the combination as claimed does not require the particulars of the subcombination as claimed for patentability, and (2) that the subcombination has utility by itself or in other combinations (MPEP § 806.05(c)). In the instant case, the combination as claimed does not require the particulars of the subcombination as claimed because invention I does not require the specific processing steps of the SOEMT processor as in invention II. The subcombination has separate utility such as an application waking up a kernel thread when necessary.
The examiner has required restriction between combination and subcombination inventions. Where applicant elects a subcombination, and claims thereto are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable subcombination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
--the inventions have acquired a separate status in the art in view of their different classification;
--the inventions have acquired a separate status in the art due to their recognized divergent subject matter; and/or
--the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Applicant now, newly provides various allegations, such as that “the Office asserts that claims 1-10 are directed to a ‘virtual machine implementation’” and erroneous allegations based thereon in the same section. The Examiner cannot find such a quotation from any office action sent by the Examiner in the instant application. Thus, no response can be provided. Moreover, this argument is not timely, and should have been provided in response to the restriction requirement (not after final). Furthermore, with respect to what was actually stated in the restriction and not argued by Applicant at any point, the application as originally filed discusses virtual machine isolation, for example, the application as originally filed is directed to “process threads executing application programs (e.g., in execution domains)”. Thus, the execution domains that are being isolated within claim 1 are virtual machines, since they comprise these application programs/process threads. These are virtual elements.
Applicant miss-quotes the MPEP at the top of page 9 of the response, alleging that MPEP 808.2 states that “a restriction is never proper where ‘as disclosed in the application, the several inventions claimed are related.” In fact, this sentence goes on to list additional requirements, and reads, in its entirety, as follows: “Where, as disclosed in the application, the several inventions claimed are related, and such related inventions are not patentably distinct as claimed, restriction under 35 U.S.C. 121 is never proper (MPEP § 806.05).” As the restriction requirement details, the inventions are patentable distinct.
With respect to Applicant’s allegations spanning pages 9-10, as noted in the restriction, there is serious burden. For example, despite Applicant alleging “no appropriate explanation was given in the Office Action with respect to any of the above-mentioned sections with respect to the claims”, the restriction explicitly noted that invention I is classified in G06F2009/45587 and invention II is classified in G06F9/3009, showing separate classification at least. This is exemplary. Thus, Applicant is simply incorrect.
Moreover, it is noted that, if any claims depend from allowable claims at the end of the day, these claims may be subject to rejoinder. Thus, arguing back and forth about the restriction requirement appears to be pointless and serves only to add additional time to each response on both sides.
Applicant’s arguments with respect to the prior art have been considered but are moot in view of the new ground(s) of rejection provided below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the control-control/status registers” in the final limitation. There is insufficient antecedent basis for this limitation in the claim. Claim 20 has the same issue and is rejected for the same reasons. Claims 2-10 are rejected at least based on their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-7, 9, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf (U.S. Patent 9,892,284) in view of Natarajan (U.S. Patent Application Publication 2023/0062917).
Regarding Claim 1,
Wachendorf discloses a processor configured to provide isolation of software executing in one or more execution domains, the processor comprising:
One or more processor cores (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; processor core(s), for example);
A physical address space (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; all memory, for example);
Control/status registers (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; registers, for example);
Hardware configuration registers (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; registers, for example);
Secure system resources (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; secure resources, for example);
An isolation domain comprising a highest priority hardware thread executed by at least one of the one or more processor cores and configured to access the entire physical address space of the processor, the control/status registers, the hardware configuration registers, and the secure system resources (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, line 65 to Column 5, line 38; and associated figures; this domain may be the entire system or any subset thereof (perhaps the combination of all trusted threads, all trusted and untrusted threads, etc.) that includes a trusted thread and can access all memory, registers, peripherals, secure resources, such as crypto resources, etc., for example);
One or more execution domains, wherein (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; other threads that do not have access to everything, for example);
Each execution domain comprises a thread executed by one of the one or more processor cores with a lower priority than the highest priority hardware thread of the isolation domain (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; untrusted threads, for example);
Each execution domain is configured to access an assigned subset of the physical address space and access an assigned subset of the control/status registers, but is unable to access any of the secure system resources (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; memory/registers split between the untrusted threads and no access to secure resources, certain peripherals, etc., for example);
Each assigned subset of the physical address space comprises less than the entire physical address space (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; portion of memory, for example); and
Each assigned subset of the control/status registers comprises less than the entire control/status registers (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; portion of registers, for example); and
A corresponding control channel coupling each execution domain with the isolation domain, each corresponding control channel configured to provide one or more of interrupt routing, reset control, and address space control, wherein each corresponding control channel is configured exclusively by the isolation domain (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; any channel between them, such as in controlling of the untrusted threads, triggering trusted code from untrusted code (which allows access to trusted code by trusted thread at the request of the untrusted thread, thus controlling the address space), ensuring access only to appropriate portions of memory, etc., for example); and
Wherein, when the thread of one of the one or more execution domains attempts to access an address in a private memory space of the physical address space, the control/status registers, the hardware configuration registers, or the secure system resources, the corresponding control channel or thread aware logic within address generation hardware of the processor limits/restricts access (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-11; Column 4, line 65 to Column 5, line 38; and associated figures; specific memory regions are inaccessible to untrusted entities, for example);
But does not appear to explicitly disclose that limiting/restricting access comprises generating an illegal address exception.
Natarajan, however, discloses that limiting/restricting access comprises generating an illegal address exception (Exemplary Citations: for example, Paragraphs 35, 45, 53, 68-72, 84, and associated figures; limiting access to memory includes illegal address exceptions, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the address authorization techniques of Natarajan into the multithreaded system of Wachendorf in order to inform the OS when an unauthorized entity attempts memory access, to allow for memory protections for caches, and/or to increase security in the system.
Regarding Claim 20,
Claim 20 is a system claim that corresponds to method claim 1 and is rejected for the same reasons. Claim 20 also includes a memory coupled to the processor and a peripheral coupled to the processor, wherein the peripheral is accessible only to the isolation domain, met by Wachendorf’s memory and peripherals as shown, for example, in Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 5, lines 15-38; and associated figures.
Regarding Claim 2,
Wachendorf discloses that the address space control of the corresponding control channel is configured to provide access to a region of memory in the physical address space to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures).
Regarding Claim 5,
Wachendorf discloses that the one or more execution domains are configured to communicate a service request to the isolation domain by generating an event to activate the highest priority hardware thread (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; ITC communications to run trusted thread on behalf of untrusted application, for example); and
The highest priority hardware thread is configured to respond to the service request (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; performing of such, returning control, etc., for example).
Regarding Claim 6,
Wachendorf discloses that the service request comprises one of an environment call instruction when the processor comprises a RISC-V processor or a system call instruction equivalent to the environment call instruction when the processor comprises a type of processor other than a RISC-V processor (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; request from untrusted code to execute trusted code, for example).
Regarding Claim 7,
Wachendorf discloses that the service request comprises a custom service request instruction (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, lines 5-39; Column 4, line 65 to Column 5, line 38; and associated figures; the above is customized to what is being requested, for example).
Regarding Claim 9,
Wachendorf discloses that the isolation domain is configured to control which of the one or more execution domain threads executes by the processor (Exemplary Citations: for example, Abstract, Column 2, line 54 to Column 3, line 50; Column 4, line 65 to Column 5, line 38; and associated figures; the system including the trusted thread(s) controls execution, for example).
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Natarajan and Hokenek (U.S. Patent Application Publication 2004/0073910).
Regarding Claim 3,
Wachendorf does not explicitly disclose that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains.
Hokenek, however, discloses that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Paragraphs 11, 12, 15, 49, 58, 59, 62-70, and associated figures; interrupts are routed based on thread identifiers associated therewith, so only those interrupts directed to a particular thread go to that particular thread, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt techniques of Hokenek into the multithreaded system of Wachendorf as modified by Natarajan in order to allow the system to set and determine which interrupts are directed to which threads, to properly route interrupts between threads, and/or to provide a low latency, low overhead mechanism for delivering and servicing cross thread interrupts in a multithreaded processor.
Regarding Claim 8,
Wachendorf does not appear to explicitly disclose that the service request comprises one or more inter-context communication flag bits.
Hokenek, however, discloses that the service request comprises one or more inter-context communication flag bits (Exemplary Citations: for example, Abstract, Paragraphs 11, 12, 15, 49, 58, 59, 62-70, and associated figures; flag bits used for inter-thread communications, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt techniques of Hokenek into the multithreaded system of Wachendorf as modified by Natarajan in order to allow the system to set and determine which interrupts are directed to which threads, to properly route interrupts between threads, and/or to provide a low latency, low overhead mechanism for delivering and servicing cross thread interrupts in a multithreaded processor.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Natarajan and Codrescu (U.S. Patent Application Publication 2007/0088938).
Regarding Claim 3,
Wachendorf does not explicitly disclose that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains.
Codrescu, however, discloses that the interrupt routing of the corresponding control channel is configured to provide a subset of external interrupts to an execution domain of the one or more execution domains (Exemplary Citations: for example, Abstract, Paragraphs 28-31, 39, 40, and associated figures; only sending certain interrupts or types of interrupts to each thread, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt control techniques of Codrescu into the multithreaded system of Wachendorf as modified by Natarajan in order to allow the system to efficiently manage interrupts, to provide for different types of interrupts to be handled in different ways, to allow for resetting of threads, and/or to increase security in the system.
Regarding Claim 4,
Wachendorf does not explicitly disclose that the corresponding control channel is configured to reset an execution domain of the one or more execution domains, without requiring reset of any other execution domains of the one or more execution domains, by applying a reset vector to the execution domain using the reset control of the corresponding control channel.
Codrescu, however, discloses that the corresponding control channel is configured to reset an execution domain of the one or more execution domains, without requiring reset of any other execution domains of the one or more execution domains, by applying a reset vector to the execution domain using the reset control of the corresponding control channel (Exemplary Citations: for example, Abstract, Paragraphs 28-31, 39, 40, and associated figures; resetting one thread using reset vector, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the interrupt control techniques of Codrescu into the multithreaded system of Wachendorf as modified by Natarajan in order to allow the system to efficiently manage interrupts, to provide for different types of interrupts to be handled in different ways, to allow for resetting of threads, and/or to increase security in the system.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wachendorf in view of Natarajan and Kang (U.S. Patent Application Publication 2008/0040579).
Regarding Claim 10,
Wachendorf does not explicitly disclose that the isolation domain is configured to select which of the one or more execution domain threads is executed by the processor using a round robin context switching determined by one of a time period or a set number of instructions.
Kang, however, discloses that the isolation domain is configured to select which of the one or more execution domain threads is executed by the processor using a round robin context switching determined by one of a time period or a set number of instructions (Exemplary Citations: for example, Paragraphs 39, 57, 65, 66, 68, 70, and associated figures; round robin switching, for example). It would have been obvious to one of ordinary skill in the art at the time of applicant’s invention, which is before any effective filing date of the claimed invention, to incorporate the thread switching techniques of Kang into the multithreaded system of Wachendorf as modified by Natarajan in order to allow the system to set how many clock cycles each thread can run for, to allow for interrupts and exceptions to be taken into account for thread switching, to ensure that a single thread can’t take all processing resources, and/or to ensure fairness in processor usage.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey D Popham whose telephone number is (571)272-7215. The examiner can normally be reached Monday through Friday 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Nickerson can be reached at (469) 295-9235. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeffrey D. Popham/Primary Examiner, Art Unit 2432
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