DETAILED ACTION
This action is responsive to the communication filed on 12/19/2025. Claims 1, 8-11, 13-14, 16-17, 19, 21, and 23-24 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-11, 13-14, 16, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20180293181 A1) in view of Richter et al. (US 20200201418 A1) in view of Kim (US 20130169353 A1) in view of Hoerner (US 20070030149 A1) in view of Lee (KR 100502101 B1) in view of Merry et al. (US 8108692 B1).
As per claim 1,
A method, comprising: detecting an occurrence of a power-up event associated with the memory sub-system at a beginning of a usage of the memory sub-system, wherein the memory sub-system comprises a plurality of blocks of non-volatile memory cells; responsive to the detected change in the system condition of the memory sub-system and detecting the occurrence of the power-up event at the beginning of the usage of the memory sub-system, providing signaling to temporarily disable a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system prior to completion of the power-up event and prior to a host using the memory sub-system, [Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data along with various circuits such as command control circuit, and read and write circuits), wherein subsequently receiving an access code may enable the device (completion of power-up event) and normal memory operations will then be possible (host use) (para. 34, line 11 – para. 37, line 6; para. 26 showing the device operating in response to input signals including commands), wherein the source of the commands may correspond to the host, and wherein the device being powered on may correspond to a beginning of a usage of the device] wherein the signaling is configured to prevent access to confidential and manufacturer specific data stored in at least a portion of the plurality of blocks of non-volatile memory cells in the absence of signaling indicative of an erase operation associated with the plurality of blocks of non-volatile memory cells; [Jang teaches normal memory operations being performed if the memory device is enabled (para. 37, lines 1-6; see para. 21, 26 providing read data being provided in memory device operations and the device operating in response to commands; also see para. 25 contrasting the present disclosures with a prior art providing for normal memory operations happening subsequent to power-on without a disabling step), wherein Jang’s disclosure is not contingent on an erase operation] responsive to receipt of signaling indicative of a vendor specific access code, providing signaling to reenable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system; and performing a memory operation to access the confidential and manufacturer specific data. [Jang teaches an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (para. 34, line 1 – para. 35, line 9), wherein a pass code to match with the access code may be set by the manufacturer (para. 28, lines 10-12, para. 18); wherein the memory device may then perform normal memory operations (para. 37, lines 1-6; para. 26 showing the device operating in response to input signals including commands)]
Jang does not explicitly disclose, but Richter discloses:
a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system [Richter discloses a memory system (fig. 1 and associated paragraphs) comprising a memory device with components including voltage generating components (para. 86-89; see fig. 3 and associated paragraphs); Richter teaches disabling components of an unused memory module set to low power mode based on a register bit (para. 17-19, 57-58; see para. 21-22, 126-129, fig. 11 and associated paragraphs providing for bit indicating entering low power mode); where Richter discloses that external interface circuits and voltage producing components of the memory device may be disabled (para. 19, 57-58), and discloses charge pumps (voltage pump) as voltage producing components that may be disabled (para. 78, 84; see para. 89 providing for the voltage-producing components, including charge pump, subject to being deactivated or activated according to low power mode; see fig. 3 and para. 86-89 providing for charge pump and voltage generating components forming part of the memory device and coupled to the memory array)]
Jang and Richter are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang and Richter, to modify the disclosures by Jang to include disclosures by Richter since they both teach data storage, wherein Richter is directed towards improved power resource management (para. 2-5, 14). Therefore, it would be applying a known technique (disabling components of an unused memory device including voltage generating components and interface) to a known device (memory system disabling memory device comprising memory circuit, wherein the memory circuit comprises memory cells and various circuits associated with the operation of the memory circuit) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter does not explicitly disclose, but Kim discloses:
a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system [Where Richter discloses disabling voltage producing components as shown above, Kim discloses that an oscillator and voltage pump may conventionally comprise a voltage generation circuit (para. 5)]
Jang, Richter, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter and Kim, to modify the disclosures by Jang in view of Richter to include disclosures by Kim since they both teach data storage, wherein Kim is directed towards improvements in operation of a semiconductor memory device (para. 34). Therefore, it would be applying a known technique (semiconductor memory device configured to include voltage generating components including voltage pump and oscillator) to a known device (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump and oscillator, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter in view of Kim does not explicitly disclose, but Hoerner discloses:
detecting a change in a system condition of a memory sub-system, wherein the detected change is a change in a value of a configuration bit of the memory sub-system to a first value; detected change in the system condition of the memory sub-system [Hoerner teaches disabling of a hard disk drive in association with detecting theft and booting of a device (para. 30, 32, 35, 61, 64; fig. 3 and associated paragraphs); Hoerner teaches a ‘theft detected’ bit on a BIOS EPROM that may default to 0 but may be set to 1 to signify theft of the device, where the hard disk drive may be disabled based on the bit value after startup (para. 49-63; figs. 8-9 and associated paragraphs; see para. 9 providing for checking the theft detected bit on each start up (para. 53, 55; steps SS1, SS3) and also teaching setting the theft detected bit to 1 responsive to a condition such as a theft sticker being removed (para. 59-60; steps SS7, SS8))]
Jang, Richter, Kim, and Hoerner are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim and Hoerner, to modify the disclosures by Jang in view of Richter in view of Kim to include disclosures by Hoerner since they both teach data storage, wherein Hoerner is directed towards restricting access to a hard disk drive in association with theft deterrence (para. 1, 35). Therefore, it would be applying a known technique (a change in a bit value on a BIOS EPROM determined on startup to determine whether a hard disk drive should be disabled) to a known device (memory system disabling a memory device on power-on and requiring an access code for reenabling the device) ready for improvement to yield predictable results (memory system that may disable a memory device on power-on and require an access code for reenabling the device, where the memory system may further comprise a BIOS EPROM comprising a bit, indicating theft of the a device, that may be checked on power-on to determine whether the memory device should be disabled in order to provide for determination of appropriate scenarios for enabling certain features such as those preventing access to a memory device). MPEP 2143
Jang in view of Richter in view of Kim in view of Hoerner does not explicitly disclose, but Lee discloses:
providing signaling to change the value of the configuration bit of the memory sub- system from the first value to a second value responsive to providing the signaling to reenable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system; [Jang in view of Richter in view of Kim in view of Hoerner as shown above teaches disabling of a device in association with a configuration bit having been changed to a first value indicating theft of the device, and an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (see the rejection above: Jang: para. 34, line 1 – para. 35, line 9; para. 21; Hoerner: para. 30, 32, 35, 49-64); Jang in view of Richter in view of Kim in view of Hoerner does not explicitly disclose changing the value of the configuration bit from the first value to a second value, but Lee discloses an anti-theft flag set to indicate enabling of anti-theft function, wherein, responsive to a password being input, the anti-theft flag is reset (please see the attached translated document: page 1, abstract; page 2, paragraphs 13-14, 18; page 7, last paragraph; page 9, last paragraph – page 10, paragraph 1)]
Jang, Richter, Kim, Hoerner, and Lee are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim in view of Hoerner and Lee, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hoerner to include disclosures by Lee since they both teach data storage, wherein Lee is directed towards improved data security through preventing stored information of a computer from leaking outside through theft (page 1, abstract). Therefore, it would be applying a known technique (responsive to submission of a password, resetting a flag indicating enablement of anti-theft features) to a known device (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value) ready for improvement to yield predictable results (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value and the configuration value in order to provide for an improved user experience where a successful user authentication of a recovered device may provide for normal subsequent uses of the device without requiring repeated authentication). MPEP 2143
Jang in view of Richter in view of Kim in view of Hoerner in view of Lee does not explicitly disclose, but Merry discloses:
confidential and manufacturer specific; confidential and manufacturer specific [Jang in view of Richter in view of Kim in view of Hoerner in view of Lee teaches protection of sensitive data stored in memory (Jang: para. 1, 18-19); while it does not specifically describe the sensitive data as confidential and manufacturer specific, Merry discloses memory device which stores data string(s), which identifies the manufacturer of the memory array, into a restricted/protected area of the memory (claim 5; col. 2, line 56 – col. 3, line 4; col. 3, lines 42-51; col. 9, lines 9-16; figs. 1, 4 and associated paragraphs), where the string(s) may be read by a host command and used by the host for decrypting and executing a file in the memory system (col. 5, line 57-col. 6, line 36; fig. 3 and associated paragraphs);Additionally, specifying the data in the claim as confidential and manufacture specific does not create a functional relationship between the data and the product with which it is associated and is therefore directed to non-functional descriptive material not accorded patentable weight (please see MPEP 2111.05). That is, there is no indication of realization of a functional relationship served by the confidential and manufacture specific being so stored and protected in the system, and the functionality of the relevant limitations in the claim would not otherwise be different if a different data was stored.
“However, where the claim as a whole is directed to conveying a message or meaning to a human reader independent of the intended computer system, and/or the computer-readable medium merely serves as a support for information or data, no functional relationship exists.” (MPEP section 2111.05.III.) "Nonfunctional descriptive material cannot render nonobvious an invention that would have otherwise been obvious." Ex parte Curry, 84 USPQ2d 1272, 1274 (BPAI 2005) (citing In re Ngai, 367 F.3d 1336, 1339 (Fed. Cir. 2004)), aft'd, Appeal No. 2006-1003 (Fed. Cir. 2006). "[W]hen descriptive material is not functionally related to the substrate, the descriptive material will not distinguish the invention from the prior art in terms of patentability[.]" Curry, 84 USPQ2d at 1274 (citing In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983)).]
Jang, Richter, Kim, Hoerner, Lee, and Merry are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jang in view of Richter in view of Kim in view of Hoerner in view of Lee with Merry’s disclosures directed towards memory device storing protected string(s) indicative of manufacturer that are used for decrypting and executing an encrypted file. Doing so would provide for an additional level of protection for contents of a memory subsystem (Merry: col. 7, lines 45-53)]
As per claim 8, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 1 as shown above and further teaches:
wherein providing the signaling to disable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system further comprises providing the signaling to disable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system to prevent read access, write access, or both, to at least the portion the plurality of blocks of non-volatile memory cells. [Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry discloses disabling memory device comprising memory cells and voltage generating components (voltage generation pump and oscillator) as well as interface as shown above (see claim 1); Jang teaches a system that disables a memory device by setting an enable signal to a deasserted state (Jang: para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data); Jang teaches normal memory operations being performed if the memory device is later enabled (para. 37, lines 1-6; see para. 21, 26 providing read and write operations performed with the device)]
As per claim 9, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 1 as shown above and further teaches:
wherein providing the signaling to disable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system further comprises providing the signaling to disable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system responsive to detecting the occurrence of the power-up event. [Jang in view of Richter in view of Kim in view of Hoerner discloses disabling memory device comprising memory cells and voltage generating components (voltage generation pump and oscillator) as well as interface as shown above (see claim 1); Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data; also see Hoerner above indicating checking a value of the theft detected bit on boot in association with disabling a memory device (Hoerner: para. 49-63)) wherein the device being powered on may correspond to the occurrence of the power-up event, and the device receiving an access code and enabled may correspond to the completion of the power-up event.]
As per claim 10, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 1 as shown above and further teaches:
further comprising providing the signaling to disable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system [Jang in view of Richter in view of Kim in view of Hoerner discloses disabling memory device comprising memory cells and voltage generating components (voltage generation pump and oscillator) as well as interface as shown above (see claim 1); Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data); where Jang’s disclosure configured to disable the memory device by default may correspond to initial configuration, and it would have been obvious for one of ordinary skill in the arts to also implement the disclosures of Jang in view of Richter in view of Kim in view of Hoerner in view of Lee so that the device is configured to be disabled by default on power-on and reenabled using an access code as taught by Jang in order to provide for improved security]
As per claim 11,
An apparatus, comprising: a memory sub-system that further comprises a memory access management component configured to: detect an occurrence of a power-up event associated with a plurality of blocks of non-volatile memory cells of the memory sub-system at a beginning of a usage of the memory sub-system; responsive to the detected change in the system condition of the memory sub-system and detection of the occurrence of the power-up event at the beginning of the usage of the memory sub-system, provide signaling to temporarily disable a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system prior to a host using the memory sub-system, to prevent access to confidential and manufacturer specific data stored in the plurality of blocks of the non-volatile memory cells in the absence of signaling indicative of an erase operation associated with the confidential and manufacturer specific data stored in the plurality of blocks of non- volatile memory cells; [Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data along with various circuits such as command control circuit, and read and write circuits; wherein the processor of the memory device and the chip enable protection circuit (para. 27) may correspond to memory access management component), wherein subsequently receiving an access code may enable the device (completion of power-up event) and normal memory operations will then be possible (host use) (para. 34, line 11 – para. 37, line 6; para. 26 showing the device operating in response to input signals including commands, wherein the source of the commands may correspond to the host, also see para. 25 contrasting present disclosures with a prior art providing for normal memory operations happening subsequent to power-on without a disabling step; see para. 18-19 on the method being used to protect data stored on the memory device including sensitive data), where Jang’s disclosure is not contingent on an erase operation, and wherein the device being powered on may correspond to a beginning of a usage of the device] responsive to receipt of signaling indicative of a vendor specific access code, provide signaling to reenable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system; and perform a memory operation to access the confidential and manufacturer specific data stored in the plurality of blocks of non- volatile memory cells. [Jang teaches an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (para. 34, line 1 – para. 35, line 9), wherein a pass code to match with the access code may be set by the manufacturer (para. 28, lines 10-12, para. 18); wherein the memory device may then perform normal memory operations (para. 37, lines 1-6; para. 26 showing the device operating in response to input signals including commands)]
Jang does not explicitly disclose, but Richter discloses:
a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system [Richter discloses a memory system (fig. 1 and associated paragraphs) comprising a memory device with components including voltage generating components (para. 86-89; see fig. 3 and associated paragraphs); Richter teaches disabling components of an unused memory module set to low power mode based on a register bit (para. 17-19, 57-58; see para. 21-22, 126-129, fig. 11 and associated paragraphs providing for bit indicating entering low power mode); where Richter discloses that external interface circuits and voltage producing components of the memory device may be disabled (para. 19, 57-58), and discloses charge pumps (voltage pump) as voltage producing components that may be disabled (para. 78, 84; see para. 89 providing for the voltage-producing components, including charge pump, subject to being deactivated or activated according to low power mode; see fig. 3 and para. 86-89 providing for charge pump and voltage generating components forming part of the memory device and coupled to the memory array)]
Jang and Richter are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang and Richter, to modify the disclosures by Jang to include disclosures by Richter since they both teach data storage, wherein Richter is directed towards improved power resource management (para. 2-5, 14). Therefore, it would be applying a known technique (disabling components of an unused memory device including voltage generating components and interface) to a known device (memory system disabling memory device comprising memory circuit, wherein the memory circuit comprises memory cells and various circuits associated with the operation of the memory circuit) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter does not explicitly disclose, but Kim discloses:
a voltage generation pump and an oscillator of the memory sub-system, and an interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system [Where Richter discloses disabling voltage producing components as shown above, Kim discloses that an oscillator and voltage pump may conventionally comprise a voltage generation circuit (para. 5)]
Jang, Richter, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter and Kim, to modify the disclosures by Jang in view of Richter to include disclosures by Kim since they both teach data storage, wherein Kim is directed towards improvements in operation of a semiconductor memory device (para. 34). Therefore, it would be applying a known technique (semiconductor memory device configured to include voltage generating components including voltage pump and oscillator) to a known device (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump and oscillator, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter in view of Kim does not explicitly disclose, but Hoerner discloses:
detect a change in a system condition of the memory sub-system, wherein the detected change is a change in a value of a configuration bit of the memory sub-system to a first value; the detected change in the system condition of the memory sub-system [Hoerner teaches disabling of a hard disk drive in association with detecting theft and booting of a device (para. 30, 32, 35, 61, 64; fig. 3 and associated paragraphs); Hoerner teaches a ‘theft detected’ bit on a BIOS EPROM that may default to 0 but may be set to 1 to signify theft of the device, where the hard disk drive may be disabled based on the bit value after startup (para. 49-63; figs. 8-9 and associated paragraphs; see para. 9 providing for checking the theft detected bit on each start up (para. 53, 55; steps SS1, SS3) and also teaching setting the theft detected bit to 1 responsive to a condition such as a theft sticker being removed (para. 59-60; steps SS7, SS8))]
Jang, Richter, Kim, and Hoerner are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim and Hoerner, to modify the disclosures by Jang in view of Richter in view of Kim to include disclosures by Hoerner since they both teach data storage, wherein Hoerner is directed towards restricting access to a hard disk drive in association with theft deterrence (para. 1, 35). Therefore, it would be applying a known technique (a change in a bit value on a BIOS EPROM determined on startup to determine whether a hard disk drive should be disabled) to a known device (memory system disabling a memory device on power-on and requiring an access code for reenabling the device) ready for improvement to yield predictable results (memory system that may disable a memory device on power-on and require an access code for reenabling the device, where the memory system may further comprise a BIOS EPROM comprising a bit, indicating theft of the a device, that may be checked on power-on to determine whether the memory device should be disabled in order to provide for determination of appropriate scenarios for enabling certain features such as those preventing access to a memory device). MPEP 2143
Jang in view of Richter in view of Kim in view of Hoerner does not explicitly disclose, but Lee discloses:
providing signaling to change the value of the configuration bit of the memory sub-system from the first value to a second value responsive to providing the signaling to reenable the voltage generating pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system; [Jang in view of Richter in view of Kim in view of Hoerner as shown above teaches disabling of a device in association with a configuration bit having been changed to a first value indicating theft of the device, and an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (see the rejection above: Jang: para. 34, line 1 – para. 35, line 9; para. 21; Hoerner: para. 30, 32, 35, 49-64); Jang in view of Richter in view of Kim in view of Hoerner does not explicitly disclose changing the value of the configuration bit from the first value to a second value, but Lee discloses an anti-theft flag set to indicate enabling of anti-theft function, wherein, responsive to a password being input, the anti-theft flag is reset (please see the attached translated document: page 1, abstract; page 2, paragraphs 13-14, 18; page 7, last paragraph; page 9, last paragraph – page 10, paragraph 1)]
Jang, Richter, Kim, Hoerner, and Lee are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim in view of Hoerner and Lee, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hoerner to include disclosures by Lee since they both teach data storage, wherein Lee is directed towards improved data security through preventing stored information of a computer from leaking outside through theft (page 1, abstract). Therefore, it would be applying a known technique (responsive to submission of a password, resetting a flag indicating enablement of anti-theft features) to a known device (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value) ready for improvement to yield predictable results (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value and the configuration value in order to provide for an improved user experience where a successful user authentication of a recovered device may provide for normal subsequent uses of the device without requiring repeated authentication). MPEP 2143
Jang in view of Richter in view of Kim in view of Hoerner in view of Lee does not explicitly disclose, but Merry discloses:
confidential and manufacturer specific; confidential and manufacturer specific; confidential and manufacturer specific [Jang in view of Richter in view of Kim in view of Hoerner in view of Lee teaches protection of sensitive data stored in memory (Jang: para. 1, 18-19); while it does not specifically describe the sensitive data as confidential and manufacturer specific, Merry discloses memory device which stores data string(s), which identifies the manufacturer of the memory array, into a restricted/protected area of the memory (claim 5; col. 2, line 56 – col. 3, line 4; col. 3, lines 42-51; col. 9, lines 9-16; figs. 1, 4 and associated paragraphs), where the string(s) may be read by a host command and used by the host for decrypting and executing a file in the memory system (col. 5, line 57-col. 6, line 36; fig. 3 and associated paragraphs);Additionally, specifying the data in the claim as confidential and manufacture specific does not create a functional relationship between the data and the product with which it is associated and is therefore directed to non-functional descriptive material not accorded patentable weight (please see MPEP 2111.05). That is, there is no indication of realization of a functional relationship served by the confidential and manufacture specific being so stored and protected in the system, and the functionality of the relevant limitations in the claim would not otherwise be different if a different data was stored.
“However, where the claim as a whole is directed to conveying a message or meaning to a human reader independent of the intended computer system, and/or the computer-readable medium merely serves as a support for information or data, no functional relationship exists.” (MPEP section 2111.05.III.) "Nonfunctional descriptive material cannot render nonobvious an invention that would have otherwise been obvious." Ex parte Curry, 84 USPQ2d 1272, 1274 (BPAI 2005) (citing In re Ngai, 367 F.3d 1336, 1339 (Fed. Cir. 2004)), aft'd, Appeal No. 2006-1003 (Fed. Cir. 2006). "[W]hen descriptive material is not functionally related to the substrate, the descriptive material will not distinguish the invention from the prior art in terms of patentability[.]" Curry, 84 USPQ2d at 1274 (citing In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983)).]
Jang, Richter, Kim, Hoerner, Lee, and Merry are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jang in view of Richter in view of Kim in view of Hoerner in view of Lee with Merry’s disclosures directed towards memory device storing protected string(s) indicative of manufacturer that are used for decrypting and executing an encrypted file. Doing so would provide for an additional level of protection for contents of a memory subsystem (Merry: col. 7, lines 45-53)]
As per claim 13, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 11 as shown above and further teaches:
wherein the memory access management component is further configured to provide signaling to disable a memory array in the apparatus. [Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data along with various circuits such as command control circuit, and read and write circuits); wherein the memory cells comprising the memory device in the memory circuit may correspond to the memory array]
As per claim 14, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 11 as shown above and further teaches:
wherein the prior to the host using the memory sub-system includes prior to asserting commands on the memory sub-system. [Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry discloses disabling memory device comprising memory cells and voltage generating components (voltage generation pump and oscillator) as well as interface upon initiation of power-up as shown above (see claim 11) and Jang provides that normal memory operations being possible after a subsequent reenabling of the device (see claim 11 above; Jang: para. 34, line 11 – para. 37, line 6; para. 21, 26 showing the device operating in response to input signals including commands when enabled, where commands would necessarily not be asserted in the device if it is disabled upon start-up); Richter further discloses that external interface disabled may comprise command bus used to communicate with a host device (para 17), where the command bus as being disabled upon power-up would necessarily not enable commands to be asserted prior to the device’s the components, including the bus, being disabled]
Jang and Richter are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang and Richter, to modify the disclosures by Jang to include disclosures by Richter since they both teach data storage, wherein Richter is directed towards improved power resource management (para. 2-5, 14). Therefore, it would be applying a known technique (disabling components of an unused memory device including voltage generating components and interface) to a known device (memory system disabling memory device comprising memory circuit, wherein the memory circuit comprises memory cells and various circuits associated with the operation of the memory circuit) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
As per claim 16, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 11 as shown above and further teaches:
wherein the memory access management component is further configured to provide signaling to disable a controller coupled to the memory sub-system. [Where Jang discloses disabling the memory device’s memory circuit (para. 27; also see the rejection in claim 11 above), Jang teaches that the memory circuit may include components including command control circuit, which may correspond to a controller (para. 26, lines 19-22)]
As per claim 23, Jang in view of Richter in view of Kim in view of Hoerner in view of Lee in view of Merry teaches claim 1 as shown above and further teaches:
wherein the change in the value of the configuration bit corresponds to a lost or stolen memory device event. [Hoerner teaches disabling of a hard disk drive in association with detecting theft and booting of a device (para. 30, 32, 35, 61, 64; fig. 3 and associated paragraphs); Hoerner teaches a ‘theft detected’ bit on a BIOS EPROM that may default to 0 but may be set to 1 to signify theft of the device, where the hard disk drive may be disabled based on the bit value after startup (para. 49-63; figs. 8-9 and associated paragraphs; see para. 9 providing for checking the theft detected bit on each start up (para. 53, 55; steps SS1, SS3) and also teaching setting the theft detected bit to 1 responsive to a condition such as a theft sticker being removed (para. 59-60; steps SS7, SS8))]
Jang, Richter, Kim, and Hoerner are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim and Hoerner, to modify the disclosures by Jang in view of Richter in view of Kim to include disclosures by Hoerner since they both teach data storage, wherein Hoerner is directed towards restricting access to a hard disk drive in association with theft deterrence (para. 1, 35). Therefore, it would be applying a known technique (a change in a bit value on a BIOS EPROM determined on startup to determine whether a hard disk drive should be disabled) to a known device (memory system disabling a memory device on power-on and requiring an access code for reenabling the device) ready for improvement to yield predictable results (memory system that may disable a memory device on power-on and require an access code for reenabling the device, where the memory system may further comprise a BIOS EPROM comprising a bit, indicating theft of the a device, that may be checked on power-on to determine whether the memory device should be disabled in order to provide for determination of appropriate scenarios for enabling certain features such as those preventing access to a memory device). MPEP 2143
Claims 17, 19, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20180293181 A1) in view of Richter et al. (US 20200201418 A1) in view of Kim (US 20130169353 A1) in view of Hughes et al. (US 20200133833A1) in view of Hoerner (US 20070030149 A1) in view of Lee (KR 100502101 B1) in view of Merry et al. (US 8108692 B1).
As per claim 17,
A system, comprising: a memory sub-system comprising a plurality of memory components arranged to form a stackable cross-gridded array of a plurality of blocks of interleaved non-volatile memory cells; and a processing device coupled to the plurality of memory components, the processing device to perform operations comprising: detecting an occurrence of a power-up event associated with the memory sub-system at a beginning of usage of the memory sub-system; responsive to the detected change in the system condition of the memory sub-system and detecting the occurrence of the power-up event at the beginning of the usage of the memory sub-system, providing signaling to temporarily disable a voltage generation pump and an oscillator of the memory sub-system, and a physical interface coupled to the memory sub-system prior to a host using the interleaved non-volatile memory cells to prevent the host from accessing confidential and manufacturer specific data in at least a portion of the blocks of interleaved non-volatile memory cells; [Jang teaches a system which, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data; wherein the processor in communication with the memory device and the chip enable protection circuit (para. 26-27, 34) may collectively correspond to the claim’s processing device), wherein subsequently receiving an access code may enable the device (completion of power-up event) and normal memory operations will then be possible (host use) (para. 34, line 11 – para. 37, line 6; para. 26 showing the device operating in response to input signals including commands and providing read data; also see para. 25 contrasting present disclosures with a prior art providing for normal memory operations happening subsequent to power-on without a disabling step), wherein the source of the commands may correspond to the host, and wherein the device being powered on may correspond to a beginning of a usage of the device] responsive to receipt of signaling indicative of a vendor specific access code, providing signaling to reenable the voltage generation pump and the oscillator of the memory sub-system, and the physical interface coupled to the memory sub-system to permit access to the confidential and manufacturer specific data in at least the portion of the blocks of interleaved non-volatile memory cells; and performing a memory operation on the interleaved non-volatile memory cells to access the confidential and manufacturer specific data. [Jang teaches an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (para. 34, line 1 – para. 35, line 9), wherein a pass code to match with the access code may be set by the manufacturer (para. 28, lines 10-12, para. 18); wherein the memory device may then perform normal memory operations (para. 37, lines 1-6; para. 21, 26 showing the device operating in response to input signals including commands)]
Jang does not explicitly disclose, but Richter discloses:
a voltage generation pump and an oscillator of the memory sub-system, and a physical interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the physical interface coupled to the memory sub-system [Richter discloses a memory system (fig. 1 and associated paragraphs) comprising a memory device with components including voltage generating components (para. 86-89; see fig. 3 and associated paragraphs); Richter teaches disabling components of an unused memory module set to low power mode based on a register bit (para. 17-19, 57-58; see para. 21-22, 126-129, fig. 11 and associated paragraphs providing for bit indicating entering low power mode); where Richter discloses that external interface circuits and voltage producing components of the memory device may be disabled (para. 19, 57-58), and discloses charge pumps (voltage pump) as voltage producing components that may be disabled (para. 78, 84; see para. 89 providing for the voltage-producing components, including charge pump, subject to being deactivated or activated according to low power mode; see fig. 3 and para. 86-89 providing for charge pump and voltage generating components forming part of the memory device and coupled to the memory array)]
Jang and Richter are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang and Richter, to modify the disclosures by Jang to include disclosures by Richter since they both teach data storage, wherein Richter is directed towards improved power resource management (para. 2-5, 14). Therefore, it would be applying a known technique (disabling components of an unused memory device including voltage generating components and interface) to a known device (memory system disabling memory device comprising memory circuit, wherein the memory circuit comprises memory cells and various circuits associated with the operation of the memory circuit) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter does not explicitly disclose, but Kim discloses:
a voltage generation pump and an oscillator of the memory sub-system, and a physical interface coupled to the memory sub-system; the voltage generation pump and the oscillator of the memory sub-system, and the physical interface coupled to the memory sub-system [Where Richter discloses disabling voltage producing components as shown above, Kim discloses that an oscillator and voltage pump may conventionally comprise a voltage generation circuit (para. 5)]
Jang, Richter, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter and Kim, to modify the disclosures by Jang in view of Richter to include disclosures by Kim since they both teach data storage, wherein Kim is directed towards improvements in operation of a semiconductor memory device (para. 34). Therefore, it would be applying a known technique (semiconductor memory device configured to include voltage generating components including voltage pump and oscillator) to a known device (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump and oscillator, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
Jang in view of Richter in view of Kim does not explicitly disclose, but Hughes discloses:
comprising a plurality of memory components arranged to form a stackable cross-gridded array of a plurality of blocks of interleaved non-volatile memory cells; the interleaved non-volatile memory cells; interleaved non-volatile memory cells; interleaved non-volatile memory cells; the interleaved non-volatile memory cells [Hughes teaches memory components comprising stackable cross-gridded access array of memory cells (para. 13, lines 1-36) and interleaved writing of data on the memory components (para. 26, lines 1-23)]
The disclosures by Jang, Richter, Kim, and Hughes are analogous to the claimed invention because they are in the same field of endeavor of data storage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jang in view of Richter in view of Kim and Hughes, to modify the teachings of Jang in view of Richter in view of Kim with Hughes’s disclosures since they both teach data storage, wherein Hughes is directed towards providing more persistent performance of memory components (Hughes: para. 9). Therefore, it would have been a simple substitution of one type of non-volatile memory (stackable cross-gridded memory array supporting interleaved writing) for another non-volatile memory (flash memory comprising memory blocks not specified to comprise stacking or interleaving) ready for improvement to provide predictable results (superior bandwidth associated with stackable memory array)
Jang in view of Richter in view of Kim in view of Hughes does not explicitly disclose, but Hoerner discloses:
detecting a change in a system condition of a memory sub-system, wherein the detected change is a change in a value of a configuration bit of the memory sub-system to a first value; detected change in the system condition of the memory sub-system [Hoerner teaches disabling of a hard disk drive in association with detecting theft and booting of a device (para. 30, 32, 35, 61, 64; fig. 3 and associated paragraphs); Hoerner teaches a ‘theft detected’ bit on a BIOS EPROM that may default to 0 but may be set to 1 to signify theft of the device, where the hard disk drive may be disabled based on the bit value after startup (para. 49-63; figs. 8-9 and associated paragraphs; see para. 9 providing for checking the theft detected bit on each start up (para. 53, 55; steps SS1, SS3) and also teaching setting the theft detected bit to 1 responsive to a condition such as a theft sticker being removed (para. 59-60; steps SS7, SS8))]
Jang, Richter, Kim, Hughes, and Hoerner are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim in view of Hughes and Hoerner, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hughes to include disclosures by Hoerner since they both teach data storage, wherein Hoerner is directed towards restricting access to a hard disk drive in association with theft deterrence (para. 1, 35). Therefore, it would be applying a known technique (a change in a bit value on a BIOS EPROM determined on startup to determine whether a hard disk drive should be disabled) to a known device (memory system disabling a memory device on power-on and requiring an access code for reenabling the device) ready for improvement to yield predictable results (memory system that may disable a memory device on power-on and require an access code for reenabling the device, where the memory system may further comprise a BIOS EPROM comprising a bit, indicating theft of the a device, that may be checked on power-on to determine whether the memory device should be disabled in order to provide for determination of appropriate scenarios for enabling certain features such as those preventing access to a memory device). MPEP 2143
Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner does not explicitly disclose, but Lee discloses:
providing signaling to change the value of the configuration bit of the memory sub- system from the first value to a second value responsive to providing the signaling to reenable the voltage generation pump and the oscillator of the memory sub-system, and the interface coupled to the memory sub-system; [Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner as shown above teaches disabling of a device in association with a configuration bit having been changed to a first value indicating theft of the device, and an access code that may be entered to reenable the memory device followed by resetting an access code attempt count to 0 (see the rejection above: Jang: para. 34, line 1 – para. 35, line 9; para. 21; Hoerner: para. 30, 32, 35, 49-64); Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner does not explicitly disclose changing the value of the configuration bit from the first value to a second value, but Lee discloses an anti-theft flag set to indicate enabling of anti-theft function, wherein, responsive to a password being input, the anti-theft flag is reset (please see the attached translated document: page 1, abstract; page 2, paragraphs 13-14, 18; page 7, last paragraph; page 9, last paragraph – page 10, paragraph 1)]
Jang, Richter, Kim, Hughes, Hoerner, and Lee are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner and Lee, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner to include disclosures by Lee since they both teach data storage, wherein Lee is directed towards improved data security through preventing stored information of a computer from leaking outside through theft (page 1, abstract). Therefore, it would be applying a known technique (responsive to submission of a password, resetting a flag indicating enablement of anti-theft features) to a known device (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value) ready for improvement to yield predictable results (memory system disabling a memory device on power-on responsive to detection of a changed configuration value indicating theft, and, responsive to an access code being entered, reenabling the device and resetting access attempt count value and the configuration value in order to provide for an improved user experience where a successful user authentication of a recovered device may provide for normal subsequent uses of the device without requiring repeated authentication). MPEP 2143
Jang in view of Richter in view of Kim in view of Hoerner in view of Lee does not explicitly disclose, but Merry discloses:
confidential and manufacturer specific; confidential and manufacturer specific; confidential and manufacturer specific [Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee teaches protection of sensitive data stored in memory (Jang: para. 1, 18-19); while it does not specifically describe the sensitive data as confidential and manufacturer specific, Merry discloses memory device which stores data string(s), which identifies the manufacturer of the memory array, into a restricted/protected area of the memory (claim 5; col. 2, line 56 – col. 3, line 4; col. 3, lines 42-51; col. 9, lines 9-16; figs. 1, 4 and associated paragraphs), where the string(s) may be read by a host command and used by the host for decrypting and executing a file in the memory system (col. 5, line 57-col. 6, line 36; fig. 3 and associated paragraphs);
Additionally, specifying the data in the claim as confidential and manufacture specific does not create a functional relationship between the data and the product with which it is associated and is therefore directed to non-functional descriptive material not accorded patentable weight (please see MPEP 2111.05). That is, there is no indication of realization of a functional relationship served by the confidential and manufacture specific being so stored and protected in the system, and the functionality of the relevant limitations in the claim would not otherwise be different if a different data was stored.
“However, where the claim as a whole is directed to conveying a message or meaning to a human reader independent of the intended computer system, and/or the computer-readable medium merely serves as a support for information or data, no functional relationship exists.” (MPEP section 2111.05.III.) "Nonfunctional descriptive material cannot render nonobvious an invention that would have otherwise been obvious." Ex parte Curry, 84 USPQ2d 1272, 1274 (BPAI 2005) (citing In re Ngai, 367 F.3d 1336, 1339 (Fed. Cir. 2004)), aft'd, Appeal No. 2006-1003 (Fed. Cir. 2006). "[W]hen descriptive material is not functionally related to the substrate, the descriptive material will not distinguish the invention from the prior art in terms of patentability[.]" Curry, 84 USPQ2d at 1274 (citing In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983)).]
Jang, Richter, Kim, Hughes, Hoerner, Lee, and Merry are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee with Merry’s disclosures directed towards memory device storing protected string(s) indicative of manufacturer that are used for decrypting and executing an encrypted file. Doing so would provide for an additional level of protection for contents of a memory subsystem (Merry: col. 7, lines 45-53)]
As per claim 19, Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee in view of Merry teaches claim 17 as shown above and further teaches:
wherein the plurality of blocks of interleaved non- volatile memory cells are NAND memory cells in a NAND memory array resident on a mobile computing device. [Hughes teaches that its memory components may comprise NAND flash memory (para. 13, lines 1-9); Hughes further teaches that a host system may be a mobile device (para. 12, lines 1-4; para. 31, lines 1-6) and may include a memory subsystem (para. 30, lines 1-11) comprising the memory components (para. 11, lines 1-8); Jang also teaches that its disclosure may comprise a smart phone (para. 19)]
Jang, Richter, Kim, Hughes, Hoerner, Lee, and Merry are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim and Hughes in view of Hoerner in view of Lee, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee in view of Merry to include additional disclosures by Hughes since they both teach data storage in non-volatile memory, wherein Hughes is directed towards providing more persistent performance of memory components (Hughes: para. 9). Therefore, it would be applying a known technique (use of non-volatile memory array comprising NAND cells resident on a mobile device) to a known device (memory system disabling components of a memory device upon power up) ready for improvement to yield predictable results (memory system disabling components of a memory device comprising NAND cells on a mobile device to prevent tempering of the boot code on a mobile device that may be subject to a greater risk of loss of custody). MPEP 2143
As per claim 21, Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee in view of Merry teaches claim 17 as shown above and further teaches:
wherein the processing device is to perform operations comprising providing the signaling to temporarily disable the entire memory sub-system, and the physical interface coupled to the memory sub-system prior to the host using the interface. [Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee in view of Merry discloses disabling memory device comprising memory cells and voltage generating components (voltage generation pump and oscillator) as well as interface as shown above (see claim 17 above); Jang teaches a system that, upon power-on, disables a memory device by setting an enable signal to a deasserted state (para. 34, lines 1-10; figs. 3-4 and associated paragraphs; see para. 20 providing for memory device comprising flash; see para. 21 and 26-27 providing chip enabling signal enabling/disabling memory device’s memory circuit containing memory cells with data, components for receiving read/write commands, and the memory device not functioning when the chip enable signal is deasserted, wherein the source of the commands may correspond to the host); Richter also teaches disabling components of a memory module during low power mode based on a register bit (para. 17-19, 58; see para. 21-22, 126-129, fig. 11 and associated paragraphs providing for bit indicating entering low power mode); where Richter discloses that external interface circuits and voltage producing components of the memory device may be disabled (para. 19, 58)]
Jang and Richter are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang and Richter, to modify the disclosures by Jang to include disclosures by Richter since they both teach data storage, wherein Richter is directed towards improved power resource management (para. 2-5, 14). Therefore, it would be applying a known technique (disabling components of an unused memory device including voltage generating components and interface) to a known device (memory system disabling memory device comprising memory circuit, wherein the memory circuit comprises memory cells and various circuits associated with the operation of the memory circuit) ready for improvement to yield predictable results (memory system disabling a memory circuit and interface associated with the memory circuit, wherein the memory circuit comprises memory cells, various circuits associated with the operation of the memory circuit, and includes voltage generating components such as voltage pump, in order to ensure reduction in power usage when the memory circuit is not being utilized). MPEP 2143
As per claim 24, Jang in view of Richter in view of Kim in view of Hughes in view of Hoerner in view of Lee in view of Merry teaches claim 17 as shown above and further teaches:
wherein the change in the value of the configuration bit corresponds to the detected power-up event. [Hoerner teaches disabling of a hard disk drive in association with detecting theft and booting of a device (para. 30, 32, 35, 61, 64; fig. 3 and associated paragraphs); Hoerner teaches a ‘theft detected’ bit on a BIOS EPROM that may default to 0 but may be set to 1 to signify theft of the device, where the hard disk drive may be disabled based on the bit value after startup (para. 49-63; figs. 8-9 and associated paragraphs; see para. 9 providing for checking the theft detected bit on each start up (para. 53, 55; steps SS1, SS3) and also teaching setting the theft detected bit to 1 responsive to a condition such as a theft sticker being removed (para. 59-60; steps SS7, SS8)), where the changed in the bit being determined on startup may correspond to the change in the value corresponding to the power up.]
Jang, Richter, Kim, Hughes, and Hoerner are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jang in view of Richter in view of Kim in view of Hughes and Hoerner, to modify the disclosures by Jang in view of Richter in view of Kim in view of Hughes to include disclosures by Hoerner since they both teach data storage, wherein Hoerner is directed towards restricting access to a hard disk drive in association with theft deterrence (para. 1, 35). Therefore, it would be applying a known technique (a change in a bit value on a BIOS EPROM determined on startup to determine whether a hard disk drive should be disabled) to a known device (memory system disabling a memory device on power-on and requiring an access code for reenabling the device) ready for improvement to yield predictable results (memory system that may disable a memory device on power-on and require an access code for reenabling the device, where the memory system may further comprise a BIOS EPROM comprising a bit, indicating theft of the a device, that may be checked on power-on to determine whether the memory device should be disabled in order to provide for determination of appropriate scenarios for enabling certain features such as those preventing access to a memory device). MPEP 2143
Response to Arguments
Applicant’s arguments with respect to the rejection of independent claims and claims depending therefrom under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of amendments to the claims and newly found prior art(s).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Noble (US 20070226394 A1) teaches a reserved area in a recording media for storing manufacturer specific data.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135