Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device formed by a wafer process, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/27/2023.
Examiner’s note
Regarding the limitation of claim 11, A method of processing a wafer having at first side including an optical waveguide and an opposing bottom side, the examiner interprets this to mean that the following steps of claim 11 simply cut a wafer and that the disclosure of there being an optical waveguide on a wafer is combinable with art for cutting a wafer for microcrack reduction because they solve the same problem.
Response to Arguments
Applicant's arguments filed 3/8/2026 have been fully considered but they are not persuasive.
Regarding applicant’s arguments towards 35 USC 112(a) rejection of claim 11, the orientation of the wafer’s top and bottom, or alternatively first and second sides, are considered arbitrary designations and the applicant has support for cutting into a bottom surface of a wafer first per par. 27 but does not provide support in the disclosure for that cutting of a bottom surface being cut or being required to be cut from below the wafer because there is no orientation provided in fig. 5 of the instant application. The present disclosure is limited only to the surface nomenclature being cut and not the act of cutting from below a wafer onto a bottom surface of a wafer. Therefore, the rejection stands.
Regarding the applicant’s arguments towards 35 USC 112(b) for the method of reducing micro cracks. The specification is light on a description of how the applicant is reducing microcracks. From this stand point, the examiner concludes that where any art of record teaches cutting a wafer from below that it anticipates the limitations of reducing microcracks. The applicant is respectfully reminded that the mere observation of still another beneficial result of an old process cannot form the basis of patentability. Allen et al. v. Cae, 57 USPQ 136; In re Maeder et al. 143 USPQ 249. Therefore, the rejection stands.
Retarding applicant’s arguments towards 35 USC 102 and 35 USC 103 towards the use of Kawashima where the applicant argues Kawashima does not cut through a bottom side of the wafer from below, the examiner interprets top and bottom to be arbitrary designations of a spatial orientation of a wafer and as such believes the disclosed orientation to be a rearrangement of parts as shifting the location of an element would not have modified the operation of device and the particular placement of an element was held to be obvious. Further, regarding the recitations of “cutting the wafer by cutting into the second side of the wafer from below the wafer a second distance to reduce creating micro-cracks and defects proximate the waveguide”, the applicant has support for cutting into a bottom surface of a wafer first per par. 27 but does not provide support in the disclosure for that cutting of a bottom surface being cut or being required to be cut from below the wafer. The present disclosure is limited only to the surface nomenclature being cut and not the act of cutting from below a wafer onto a bottom surface of a wafer. The examiner also respectfully points out that the applicant acknowledges that per par. 27 “the order of cutting can be reversed” meaning it is obvious to also cut from a top side of a wafer, flip said wafer, then subsequently cut through a bottom side meaning that the nomenclature of which side of a wafer is top or bottom is immaterial. Due to the way the specification is written and the lack of support for cutting below the wafer, the inventive concept is interpreted by the examiner to be related to the distance the wafer is cut through on the first and second cuts. Further, the examiner concludes that where any art of record teaches cutting a wafer from below that it anticipates the limitations of reducing microcracks. The applicant is respectfully reminded that the mere observation of still another beneficial result of an old process cannot form the basis of patentability. Allen et al. v. Cae, 57 USPQ 136; In re Maeder et al. 143 USPQ 249.
Further, in relation to the top, bottom, first, and second sides being considered arbitrary nomenclature, the applicant further admits this in par. 15 of the instant application which discloses “Also, to the extent used herein, any directional term, such as front, rear, inwards, outwards, towards, left, right, lateral, longitudinal, up, down, upper, lower, top, bottom and side, are used by way of example only, and are not limiting as to direction or orientation of any optic or component of an optic constructed as otherwise described herein”.
Regarding applicant’s arguments towards the prior art of Alexander, the examiner reposefully points out that the art of Alexander is used to provide evidence that it is obvious to irradiate a workpiece from underneath, aka a bottom side. From this standpoint, it is therefore obvious to modify the art of Kawashima such that Kawashima is rearranged to irradiate a laser from the underside of the workpiece of Kawashima. The rejection respectfully stands.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-13, 19, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 11, and the recitation of “cutting the wafer by cutting into the second side of the wafer from below the wafer a second distance to reduce creating micro-cracks and defects proximate the waveguide”, the applicant has support for cutting into a bottom surface of a wafer first per par. 27 but does not provide support in the disclosure for that cutting of a bottom surface being cut or being required to be cut from below the wafer because there is no orientation provided in fig. 5 of the instant application. The present disclosure is limited only to the surface nomenclature being cut and not the act of cutting from below a wafer onto a bottom surface of a wafer.
Claims 12, 13, 19, and 20 are also rejected due to their dependence to one or more of the above rejected independent claims.
Claims 19 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 of which claims 19 and 20 depend limits the method of the invention to cutting into, but not through, the bottom side of the wafer a first distance, flipping the wafer, and cutting the wafer into a top side a second distance. Claims 19 and 20 as amended introduce steps which are additional to those steps recited in claim 11 and are therefore considered new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 12, 13, 19, and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: the method for reducing micro cracks. The specification is light on the method of reducing microcracks. It is interpreted by the examiner that the applicant intends to mean that the act of cutting the wafer of the instant application reduces microcracks. The examiner is unclear if laser power, the act of flipping the wafer, or some other method is causing the reduction of micro cracks.
Claims 12, 13, 19, and 20 are also rejected due to their dependence to one or more of the above rejected independent claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 12, 13, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US20090294913A1 Kawashima.
Regarding claim 11, Kawashima teaches, except where struck through, A method of processing a wafer having a first side (surface 18) including an optical waveguide (CP or chip 30 is taught in par. 52 to be an optical waveguide) and an opposing second side (other surface 19), comprising the sequential steps of:
cutting the wafer by cutting into, but not through, the second side of the wafer from below the wafer a first distance (par. 118 teaches cutting to a depth Dg per figs. 4a and 4b which is not through) to reduce creating micro-cracks and defects proximate the waveguide (Kawashima teaches the method and device disclosed in the instant application, therefore, it is anticipated that the method of Kawashima has the inherent advantage to reduce microcracks and defects);
flipping the wafer (par. 118 teaches cutting to a depth Dg per figs. 4a and 4b then flipping the wafer to cut from the other side);
and cutting the wafer by cutting into the top side of the wafer from below the wafer a second distance (par. 121 teaches the focal length per fig. 4b as a second distance) to reduce creating micro-cracks and defects proximate the waveguide (Kawashima teaches the method and device disclosed in the instant application, therefore, it is anticipated that the method of Kawashima has the inherent advantage to reduce microcracks and defects), wherein the optical waveguide is separated into a die (chip 30), wherein the cutting into the first side from below the wafer the first distance and then into the second side of the wafer from below the wafer the second distance reduces micro-cracks. The applicant is respectfully reminded that the mere observation of still another beneficial result of an old process cannot form the basis of patentability. Allen et al. v. Cae, 57 USPQ 136; In re Maeder et al. 143 USPQ 249.
Regarding claim 12, Kawashima teaches, wherein the wafer is cut using at least one laser (par. 118 teaches laser light L).
Regarding claim 13, Kawashima teaches, wherein the wafer is comprised of glass (par. 47 teaches “The substrate is, for example, a silicon substrate or a glass substrate”).
Regarding claim 20, Kawashima teaches, further comprising cutting into the first side such that the first distance is unequal to the second distance the wafer is cut into the second side (figs. 1c teaches Dg vs Dc vs Tr vs Tw, 2b teaches Dg vs Bv, and 4b teaches DG vs TW vs BW all of which are unequal depths).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090294913A1 Kawashima in view of US20080296263A1 Alexander in view of US10384306B1 Beresford.
Regarding claim 19, Kawashima does not teach further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side.
Beresford teaches, further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side (column 9 lines 59 to 67 and column 10 lines 1 to 10 teach the combinations of choosing to cut with each laser beam at equal distances and non-equal distances. Following the replacement discussed in claim 1 where laser array 420a and b of the embodiment of fig. 4 is replaced with the laser beams 524a to c of the embodiment of fig. 5, it is obvious to one of ordinary skill in the art to modify the laser beams in the top and bottom laser array 420a and b to cut at the same or different depths into the substrate 412 or 512 of Beresford).
Therefore, it would have been obvious before the effective date of the claimed invention to one of ordinary skill in the art to modify the device in the Kawashima reference, such that f further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side, as suggested and taught by Beresford, for the purpose of providing a partial cut through the substrate (summation of column 9 lines 64 to 67 and column 10 lines 1 to 11). It would have been obvious to one having ordinary skill in the art to have determined the optimum values of the relevant process parameters through routine experimentation in the absence of a showing of criticality. In re Aller, USPQ 233 (CCPA 1955).
In the alternative Claim(s) 11, 12, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090294913A1 Kawashima in view of US20080296263A1 Alexander.
Regarding claim 11, Kawashima teaches, except where struck through, A method of processing a wafer having a first side (surface 18) including an optical waveguide (CP or chip 30 is taught in par. 52 to be an optical waveguide) and an opposing second side (other surface 19), consisting of the sequential steps:
cutting the wafer by cutting into, but not through, the first side of the wafer(par. 118 teaches cutting to a depth Dg per figs. 4a and 4b which is not through, regarding the laser of Kawashima being below a wafer, Shifting the location of an element would not have modified the operation of device. In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975) The particular placement of an element was held to be obvious) to reduce creating micro-cracks and defects proximate the waveguide (Kawashima teaches the method and device disclosed in the instant application, therefore, it is anticipated that the method of Kawashima has the inherent advantage to reduce microcracks and defects);
flipping the wafer (par. 118 teaches cutting to a depth Dg per figs. 4a and 4b then flipping the wafer to cut from the other side);
and cutting the wafer by cutting into the second side of the wafer from below the wafer a second distance (par. 121 teaches the focal length per fig. 4b as a second distance) to reduce creating micro-cracks and defects proximate the waveguide (Kawashima teaches the method and device disclosed in the instant application, therefore, it is anticipated that the method of Kawashima has the inherent advantage to reduce microcracks and defects), wherein the optical waveguide is separated into a die (chip 30) wherein the cutting into the first side from below the wafer the first distance and then into the second side of the wafer from below the wafer the second distance reduces micro-cracks.
The difference between the prior art and the claimed invention is that Kawashima does not teach: cutting the wafer by cutting into…the bottom side of the wafer from below the wafer.
Alexander teaches, teaches a method of removing material from an object from below (claim 1 and par. 101 and 194) which a known technique that is applicable to the base device of Kawashima.
One of ordinary skill in the art would have been capable of applying this known technique of invert the invention of Kawashima to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filing date of the claimed invention to rearrange the invention of Kawashima to be inverted.
The results would have been predictable, because Alexander teaches irradiating a workpiece from below to aid in particle removal benefits (par. 101 and 194).
Regarding claim 12, Kawashima teaches, wherein the wafer is cut using at least one laser (par. 118 teaches laser light L).
Regarding claim 13, Kawashima teaches, wherein the wafer is comprised of glass (par. 47 teaches “The substrate is, for example, a silicon substrate or a glass substrate”).
Regarding claim 20, Kawashima teaches, further comprising cutting into the first side such that the first distance is unequal to the second distance the wafer is cut into the second side (figs. 1c teaches Dg vs Dc vs Tr vs Tw, 2b teaches Dg vs Bv, and 4b teaches DG vs TW vs BW all of which are unequal depths).
In the alternative Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090294913A1 Kawashima in view of US20080296263A1 Alexander in view of US10384306B1 Beresford.
Regarding claim 19, Kawashima does not teach further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side.
Beresford teaches, further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side (column 9 lines 59 to 67 and column 10 lines 1 to 10 teach the combinations of choosing to cut with each laser beam at equal distances and non-equal distances. Following the replacement discussed in claim 1 where laser array 420a and b of the embodiment of fig. 4 is replaced with the laser beams 524a to c of the embodiment of fig. 5, it is obvious to one of ordinary skill in the art to modify the laser beams in the top and bottom laser array 420a and b to cut at the same or different depths into the substrate 412 or 512 of Beresford).
Therefore, it would have been obvious before the effective date of the claimed invention to one of ordinary skill in the art to modify the device in the Kawashima reference, such that further comprising cutting into the first side such that the first distance is equal to the second distance the wafer is cut into the second side, as suggested and taught by Beresford, for the purpose of providing a partial cut through the substrate (summation of column 9 lines 64 to 67 and column 10 lines 1 to 11). It would have been obvious to one having ordinary skill in the art to have determined the optimum values of the relevant process parameters through routine experimentation in the absence of a showing of criticality. In re Aller, USPQ 233 (CCPA 1955).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM M ECKARDT whose telephone number is (313)446-6609. The examiner can normally be reached 6 a.m to 2:00 p.m EST Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Edward Landrum can be reached at (571) 272-5567. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ADAM MICHAEL. ECKARDT
Assistant Examiner
Art Unit 3761
/ADAM M ECKARDT/Examiner, Art Unit 3761
/WOODY A LEE JR/Primary Examiner, Art Unit 3761
Prosecution Insights