Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gupta et al. (hereinafter “Gupta”, 2017/0228345).
Re Claim 1, Gupta discloses in Figs. 1 and 5 and (para. [0001]-[0026] & [0041]-[0042]), a meta crossbar array (150), comprising:
a plurality of unit crossbars (140), wherein each unit crossbar among the plurality of unit crossbars comprises: row and column decoders (110, 112) acting as analog multiplexers that couple an input and an output to a selected memristor (144) located between a selected column and a selected row;
a binary enable control (read/write control circuit [0003]) that enables or disables the row and column decoders; and
a multi-bit selection control (memristor control circuit [0003]) which sets the selected row and the selected column of the each unit crossbar, wherein each unit crossbar is configured such that only one or no memristor is coupled to a common input source at a time.
Re Claim 2. Gupta discloses in para. [0002]-[0003], wherein the binary enable control of the each unit crossbar is controlled by a unique memory element associated with a specific unit crossbar among the plurality of unit crossbars and wherein the unique memory element is operable to be individually set or individually reset.
Re Claim 3. Gupta discloses, the meta crossbar array is configured as a non-topological array, wherein all inputs of the each unit crossbar are connected to a common input and all outputs of the each unit crossbar are connected to a common output.
Re Claim 4, Gupta discloses, further comprising a pair of meta crossbar arrays acting as a differential pair wherein each meta array among the pair of meta crossbar arrays receives the same enable and the same selection control bits.
Re Claim 5. Gupta discloses [0061]-[0071] wherein:
the non-topological array comprises a pair of non-topological meta crossbar arrays acting as a differential pair; and each non-topological meta crossbar array among the pair of non-topological meta crossbar arrays receives the same enable and the same selection control bits.
Re Claim 6. Gupta discloses, wherein the selection control lines of all unit crossbars among the plurality of unit crossbars are connected such that each unit crossbar among the plurality of unit crossbars receives the same selection signals.
Re Claim 7. Gupta discloses, wherein each unique address of the selection control bits is associated with a unique layer of a neural network.
Re Claim 15. Gupta discloses in [0061]-[0071], wherein the selection control lines of all unit crossbars among the plurality of unit crossbars are connected wherein each unit crossbar among the plurality of unit crossbars receives the same selection signals.
Re Claim 16. Gupta discloses in [0061]-[0071], wherein each unique address of the selection control bits is associated with a unique layer of a neural network.
Re Claim 17. Gupta discloses in [0061]-[0071], wherein each unique address of the selection control bits is associated with a unique neuron of a neural network.
Re Claim 18. Gupta discloses in Figs. 1 and 5 and (para. [0001]-[0026] & [0041]-[0042]), a meta crossbar array (150), comprising:
a plurality of unit crossbars (140), wherein each unit crossbar among the plurality of unit crossbars comprises: row and column decoders (110, 112)) acting as analog multiplexers that couple an input and an output to a selected memristor (144) located between a selected column and a selected row;
a binary enable control (read/write control circuit [0003]) that enables or disables the row and column decoders;
a multi-bit selection (memristor control circuit [0003]) that which sets the selected row and the selected column of the each unit crossbar; and
a memory element (306, 312), wherein the binary enable control of the each unit crossbar is controlled by the memory element associated with a specific unit crossbar among the plurality of unit crossbars and wherein the memory element is operable to be individually set or individually reset, and wherein each unit crossbar is configured such that only one or no memristor is coupled to a common input source at a time.
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/MARVIN PAYEN/Primary Examiner, Art Unit 2899
