Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action is sent in response to Applicant’s Communication received on 02/06/2026 for application number 17/461,808.
Response to Amendments
3. The Amendment filed 02/06/2026 has been entered. Claims 13, 16, 17, 19, and 20 have been amended. Claims 13-20 remain pending in the application.
Response to Arguments
Applicant argues that Friedman describes only a probability associated with a single switching event. Friedman is silent as to any repeated control operations applied to a holding circuit, and further silent as to any cumulative switching probability that evolves as a function of the number of such operations. Liyanagedera does not teach or suggest applying a control signal repeatedly and observing a "cumulative switching probability over multiple operations," as recited in amended independent claim 13. Applicant has also considered Nishi, and respectfully submits that this reference does not overcome the above-noted deficiencies of Friedman alone or Friedman in view of Liyanagedera with regard to the subject matter of amended claim 13.
The Examiner respectfully disagrees, Friedman does not disclose only a single isolated switching event; rather, Friedman teaches repeated programming activity in recurring S1/S2 phases and repeating cycles, with stochastic signals whose probability depends on prior spike history and counter values, thus reasonable teaching repeated control operations applied to the synaptic device. Liyanagedera further teaches that the switching probability of the stochastic switching element follows a sigmoidal relationship to the write current. Nishi supplies the cumulative aspect by expressly teaching a relationship between switching period and cumulative probability, and by teaching repeated stochastic switching operations whose outcomes are accumulated statistically. Thus, the combination of Friedman, Liyanagedera, and Nishi teach the above argued features.
Claim Rejections – 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 13, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Friedman et al. (U.S. Patent Application Pub. No. US 20120084241 A1) in view of Liyanagedera et al. (Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes, arXiv, published 2018, pages 1-5) and further in view of Nishi et al. (U.S. Patent Application Pub. No. US 20160085626 A1).
Claim 13: Friedman teaches a neural network device comprising:
a first neuron circuit (i.e. FIG. 2 shows a diagram of an example neuromorphic network 100, according to an embodiment of the invention, comprising electronic neurons 101, 102, 103, 104, 105, 106 and 107 interconnected via synapses 22. Each of the synapses 22 includes a variable state resistor 23 and a FET 25, as described above. In each synapse 22, the resistor 23 comprises a PCM device connected in series with the drain terminal D of a FET 25, wherein the source terminal S of the FET 25 functions as an axon a, the gate terminal G of the FET 25 functions as a gating membrane m, and the top electrode of the resistor 23 functions as a dendrite d. The interconnections between the neurons and synapses in FIG. 2 is based on a cross-bar array, such as shown in FIG. 1. The neurons comprise CMOS circuits for integrate-and-fire functions to implement binary probabilistic STDP in synapses 22; para. [0052]);
a conversion circuit that converts a spike signal from the first neuron circuit to a synapse current according to a weight signal (i.e. As shown by example in FIG. 10B, in one embodiment, an axon driver X3 comprises a timing circuit 453 and a level generator circuit 454. When the driver X3 receives a spike signal from a neuron, the level generator circuit 454 of the driver X3 generates axonal signals. In one example, such an axonal signal comprises an axonal spike signal about 0.1 ms long used for forward communication of the neuron spike signal. The spike signal creates a voltage bias across a corresponding synaptic device 22 (FIG. 10A), resulting in a current flow into down-stream neurons, such that the magnitude of the current is weighted by the conductance of the corresponding synaptic device 22; para. [0086]);
a transmission circuit that transmits the converted synapse current to a second neuron circuit (i.e. As shown by example in FIG. 10B, in one embodiment, an axon driver X3 comprises a timing circuit 453 and a level generator circuit 454. When the driver X3 receives a spike signal from a neuron, the level generator circuit 454 of the driver X3 generates axonal signals. In one example, such an axonal signal comprises an axonal spike signal about 0.1 ms long used for forward communication of the neuron spike signal. The spike signal creates a voltage bias across a corresponding synaptic device 22 (FIG. 10A), resulting in a current flow into down-stream neurons, such that the magnitude of the current is weighted by the conductance of the corresponding synaptic device 22; para. [0086]);
a holding circuit that holds and supplies the weight signal a state of which is discretely changeable (i.e. the invention provides a probabilistic asynchronous neuromorphic network for producing spike-timing dependent plasticity. The network comprises a plurality of electronic neurons and an interconnect circuit coupled to the plurality of electronic neurons to interconnect the plurality of electronic neurons. The interconnect circuit comprises a plurality of axons and a plurality of dendrites such that the axons and dendrites are orthogonal to one another. The interconnect circuit further comprises plural synaptic devices for interconnecting the electronic neurons via axons and dendrites, such that each synaptic device comprises a binary state memory device at a cross-point junction of the interconnect circuit coupled between a dendrite and an axon; para. [0008, 0095); and
a control circuit that provides a control signal repeatedly to the holding circuit (i.e. A timing controller generates a timing signal for controlling phased operation of the electronic neurons. The timing signal provides a sequence of phases, wherein activity of each electronic neuron is confined to said phases such that the synaptic devices provide spike-timing dependent plasticity based on the activity of the electronic neurons in a time phased fashion; para. [0007, 0093]),
wherein the holding circuit includes a memory cell connected between the control circuit and the conversion circuit (i.e. Embodiments of the invention provide a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path; para. [0006, 0034, 0052]),
a first switch circuit connected between the control circuit and the memory cell (i.e. The cross-bar array 12 comprises a nanoscale cross-bar array comprising said resistors 23 at the cross-point junctions, employed to implement arbitrary and plastic connectivity between said electronic neurons. Each synapse device 22 further comprises an access or control device 25 comprising a FET which is not wired as a diode, at every cross-bar junction to prevent cross-talk during signal communication (neuronal firing events) and to minimize leakage and power consumption; para. [0039]), the first switch circuit being configured to switch the level of the weight signal responding on the control signal (i.e. The combined action of the signals from drivers X2 and X3 in response to spiking signals from the firing neurons in the cross-bar array 12, causes the corresponding resistors 23 in synapses 22 at the cross-bar array junctions thereof, to change value based on the spiking timing action of the firing neurons. This provides programming of the resistors 23. The magnitude of the voltage pulses generated by interface drivers X2 and X3 are selected such that the current flow through the synaptic element due to the activity of only one among them is not sufficient to program the synaptic element; para. [0101]), a switching probability over multiple operations of the first switch circuit showing a variation along a shape with respect to the number of input times of the control signals (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13; para. [0095, 0126]),
a second switch circuit connected between the control circuit and the memory cell in parallel with the first switch circuit (i.e. The cross-bar array 12 comprises a nanoscale cross-bar array comprising said resistors 23 at the cross-point junctions, employed to implement arbitrary and plastic connectivity between said electronic neurons. Each synapse device 22 further comprises an access or control device 25 comprising a FET which is not wired as a diode, at every cross-bar junction to prevent cross-talk during signal communication (neuronal firing events) and to minimize leakage and power consumption; para. [0039]), the second switch circuit being configured to switch the level of the weight signal responding on the control signal (i.e. The combined action of the signals from drivers X2 and X3 in response to spiking signals from the firing neurons in the cross-bar array 12, causes the corresponding resistors 23 in synapses 22 at the cross-bar array junctions thereof, to change value based on the spiking timing action of the firing neurons. This provides programming of the resistors 23. The magnitude of the voltage pulses generated by interface drivers X2 and X3 are selected such that the current flow through the synaptic element due to the activity of only one among them is not sufficient to program the synaptic element; para. [0101]), a probability of the switch operation of the level of the weight signal showing a variation along a shape with respect to the number of input times of the control signals (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13; para. [0095, 0126]).
Friedman does not explicitly teach a cumulative probability and a sigmoidal shape.
However, Liyanagedera teaches a switching probability over multiple operations of the first switch circuit showing a variation along a sigmoidal shape (i.e. Figure 4(b) depicts the variation of the switching probability of the MTJ with I Ibias, normalized by a factor Io. Io can be found by fitting the switching probability characteristics [Psw(:::)] to the sigmoid function; page 4) with respect to the number of input times of the control signals (i.e. Given a particular duration of write current
owing through the device, a magnet exhibits a particular probability of switching during that corresponding write cycle. Consecutive write and read cycles can be used to generate an output pulse stream whose average value depends on the magnitude of the input stimulus; page 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Friedman to include the feature of Liyanagedera. One would have been motivated to make this modification in order to accurately model and control the cumulative probability of weight updates over multiple control pulses.
However, Nishi teaches a cumulative switching probability (i.e. FIG. 18 is illustrated an exemplary relationship between the switching period and the cumulative probability of the resistance switch element 300 in which TaO.sub.x is used. That is, in FIG. 18 is illustrated a cumulative probability distribution of the period of time (the switching period) taken in the resistance switch element 300, in which TaO.sub.x is used, since the application of a fixed voltage in the high-resistance state up to transition to the low-resistance state. As can be understood from FIG. 18, the switching period is distributed across about triple digits, and it is indicated that the transition itself is stochastic. If the state of the resistance switch element 300 is to be switched at the rate of 20%, it can be understood from FIG. 18 that the voltage can be applied for 400 nanoseconds. That is, in FIG. 18, it takes 400 nanoseconds for the cumulative probability to reach 0.2; para. [0126, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman and Liyanagedera to include the feature of Nishi. One would have been motivated to make this modification in order to achieve predictable and controllable cumulative switching behavior over multiple control pulses in a neuromorphic circuit.
Claim 14: Friedman, Liyanagedera, and Nishi teach the neural network device according to claim 13. Friedman further teaches wherein the first switch circuit includes multiple switches and selectors connected in series between the control circuit and the memory cell, the second switch circuit includes multiple switches and selectors connected in series between the control circuit and the memory cell in parallel with the first multiple switches (i.e. figs. 1, 10, the synapse devices 22 are at the cross-point junctions of the cross-bar array 12, wherein the synapse devices 22 are connected between axons 24 and dendrites 26 such that the axons 24 and dendrites 26 are orthogonal to one another. Embodiments of synaptic devices 22 include binary variable state resistors which implement probability modulated STDP versions. Disclosed embodiments include systems with access devices and systems without access devices; para. [0081, 0082, 0101]).
Claim 18: Friedman, Liyanagedera, and Nishi teach the neural network device according to claim 14. Friedman further teaches wherein the memory cell includes a SRAM (Static Random Access Memory) cell (i.e. Referring to the diagram in FIG. 16, in another embodiment, the invention provides a probabilistic asynchronous synaptic network 400 implementing binary stochastic spike-timing-dependent plasticity using a cross-bar array 412 of including static random access memory (SRAM) devices 22 at cross-point junctions of the cross-bar array 412. In one embodiment, each synapse device 22 comprises a binary state SRAM device including transistor devices; para. [0130]), each switch in the first switch circuit includes a resistance change element whose resistance state is changeable depending on a voltage applied both ends, each switch in the second switch circuit includes a resistance change element whose resistance state is changeable depending on a voltage applied both ends (i.e. The term variable state resistor refers to a class of devices in which the application of an electrical pulse (either a voltage or a current) will change the electrical conductance characteristics of the device; para. [0035, 0052]).
6. Claims 15, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Friedman, Liyanagedera, Nishi, and further in view of Ali et al. (Accurate bearing remaining useful life prediction based on Weibull distribution and artificial neural network, Mechanical Systems and Signal Processing Volumes 56–57, published 2015, pages 150-172).
Claim 15: Friedman, Liyanagedera, and Nishi teach the neural network device according to claim 13. Friedman further teaches wherein the first switch circuit includes one switch following a distribution connected between the control circuit and the memory cell, the second switch circuit includes one switch following a distribution connected between the control circuit and the memory cell in parallel with the first switch circuit (i.e. Each driver circuit X2 and X3 includes a stochastic signal generator 250A shown in FIG. 11 that generates a signal with a probability of occurrence that decays as a function of the time elapsed since the last spiking of a corresponding electronic neuron. The stochastic signal generator 250A comprises a cyclic counter 251 that is constantly updating its value (i.e., always-on counter), a spike dependent counter 252 that is initiated when an external alter signal (such as neuron spiking signal) is received, and a comparator 253 that compares the value of the spike dependent counter to the value of the cyclic counter upon receiving a request signal. If the value of the spike dependent counter is greater than the value of the cyclic counter, the comparator 253 causes a pulse module 254 to generate a stochastic binary enable pulse. The term “binary” means that each pulse is being used to represent one of two possible data values; para. [0081, 0082, 0093-0095]).
Friedman does not explicitly teach Weibull distribution.
However, Ali teaches Weibull distribution (i.e. Weibull distribution; pages 150-157).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman, Liyanagedera, and Nishi to include the feature of Ali. One would have been motivated to make this modification because it can model different types of failure rates or event timings.
Claim 17: Friedman, Liyanagedera, Nishi, and Ali teach the neural network device according to claim 15. Friedman further teaches wherein the switching probability over multiple operations of each of the first switch circuit and the second switch circuit shows a variation according to a distribution with respect to the number of input times of the control signals (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13; para. [0095, 0126]).
Friedman does not explicitly teach wherein the cumulative switching probability according to a Weibull distribution.
However, Nishi further teaches a switching cumulative probability (i.e. FIG. 18 is illustrated an exemplary relationship between the switching period and the cumulative probability of the resistance switch element 300 in which TaO.sub.x is used. That is, in FIG. 18 is illustrated a cumulative probability distribution of the period of time (the switching period) taken in the resistance switch element 300, in which TaO.sub.x is used, since the application of a fixed voltage in the high-resistance state up to transition to the low-resistance state. As can be understood from FIG. 18, the switching period is distributed across about triple digits, and it is indicated that the transition itself is stochastic. If the state of the resistance switch element 300 is to be switched at the rate of 20%, it can be understood from FIG. 18 that the voltage can be applied for 400 nanoseconds. That is, in FIG. 18, it takes 400 nanoseconds for the cumulative probability to reach 0.2; para. [0126, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman and Liyanagedera to include the feature of Nishi. One would have been motivated to make this modification in order to achieve predictable and controllable cumulative switching behavior over multiple control pulses in a neuromorphic circuit.
Friedman does not explicitly teach Weibull distribution.
However, Ali further teaches Weibull distribution (i.e. Weibull distribution; pages 150-157).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman, Liyanagedera, and Nishi to include the feature of Ali. One would have been motivated to make this modification because it can model different types of failure rates or event timings.
Claim 19: Friedman, Liyanagedera, Nishi, and Ali teach the neural network device according to claim 15. Friedman further teaches wherein the memory cell includes a SRAM (Static Random Access Memory) cell (i.e. Referring to the diagram in FIG. 16, in another embodiment, the invention provides a probabilistic asynchronous synaptic network 400 implementing binary stochastic spike-timing-dependent plasticity using a cross-bar array 412 of including static random access memory (SRAM) devices 22 at cross-point junctions of the cross-bar array 412. In one embodiment, each synapse device 22 comprises a binary state SRAM device including transistor devices; para. [0130]), the one switch in the first switch circuit includes a resistance change element whose resistance state is changeable depending on a voltage applied both ends so that the switching probability over multiple operations of each of the first switch circuit and the second switch circuit shows a variation according to a distribution with respect to the number of input times of the control signals (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13; para. [0095, 0126]), the one switch in the second switch circuit includes a resistance change element whose resistance state is changeable depending on a voltage applied both ends so that the switching probability over multiple operations of each of the first switch circuit and the second switch circuit shows a variation according to a distribution with respect to the number of input times of the control signals (i.e. The term variable state resistor refers to a class of devices in which the application of an electrical pulse (either a voltage or a current) will change the electrical conductance characteristics of the device; para. [0035, 0052]).
Friedman does not explicitly teach wherein the cumulative probability and a Weibull distribution.
However, Nishi further teaches a cumulative switching probability (i.e. FIG. 18 is illustrated an exemplary relationship between the switching period and the cumulative probability of the resistance switch element 300 in which TaO.sub.x is used. That is, in FIG. 18 is illustrated a cumulative probability distribution of the period of time (the switching period) taken in the resistance switch element 300, in which TaO.sub.x is used, since the application of a fixed voltage in the high-resistance state up to transition to the low-resistance state. As can be understood from FIG. 18, the switching period is distributed across about triple digits, and it is indicated that the transition itself is stochastic. If the state of the resistance switch element 300 is to be switched at the rate of 20%, it can be understood from FIG. 18 that the voltage can be applied for 400 nanoseconds. That is, in FIG. 18, it takes 400 nanoseconds for the cumulative probability to reach 0.2; para. [0126, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman and Liyanagedera to include the feature of Nishi. One would have been motivated to make this modification in order to achieve predictable and controllable cumulative switching behavior over multiple control pulses in a neuromorphic circuit.
Friedman does not explicitly teach Weibull distribution.
However, Ali further teaches Weibull distribution (i.e. Weibull distribution; pages 150-157).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman, Liyanagedera, and Nishi to include the feature of Ali. One would have been motivated to make this modification because it can model different types of failure rates or event timings.
7. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Friedman, Liyanagedera, Nishi, and further in view of Kim (Convolutional Neural Network Quantization using Generalized Gamma Distribution, arXiv:1810.13329, published 2018, pages 1-10).
Claim 16: Friedman, Liyanagedera, and Nishi teach the neural network device according to claim 14. Friedman further teaches wherein the switching probability over multiple operations of each of the first switch circuit and the second switch circuit shows a variation according to a distribution with respect to the number of input times of the control signals (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13. The synapse device 22 includes a memory device with two states, wherein the state of the memory device is changed probabilistically based on the pulse from the stochastic signal generator 250A. FIG. 13 shows the probability of changing state of the memory device in the synapse device 22 (vertical axis), normalized by the minimum between before and after state of synapse device 22, as a function of the timing between neuronal firing (horizontal axis); para. [0093-0095]).
Friedman does not explicitly teach wherein the cumulative probability according to a gamma distribution.
However, Nishi teaches a cumulative switching probability (i.e. FIG. 18 is illustrated an exemplary relationship between the switching period and the cumulative probability of the resistance switch element 300 in which TaO.sub.x is used. That is, in FIG. 18 is illustrated a cumulative probability distribution of the period of time (the switching period) taken in the resistance switch element 300, in which TaO.sub.x is used, since the application of a fixed voltage in the high-resistance state up to transition to the low-resistance state. As can be understood from FIG. 18, the switching period is distributed across about triple digits, and it is indicated that the transition itself is stochastic. If the state of the resistance switch element 300 is to be switched at the rate of 20%, it can be understood from FIG. 18 that the voltage can be applied for 400 nanoseconds. That is, in FIG. 18, it takes 400 nanoseconds for the cumulative probability to reach 0.2; para. [0126, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman and Liyanagedera to include the feature of Nishi. One would have been motivated to make this modification in order to achieve predictable and controllable cumulative switching behavior over multiple control pulses in a neuromorphic circuit.
However, Kim teaches wherein the cumulative switching probability over multiple operations of each of the first switch circuit and the second switch circuit shows a variation according to a gamma distribution with respect to the number of input times of the control signals (i.e. gamma distribution; pages 1-9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman, Liyanagedera, and Nishi to include the feature of Kim. One would have been motivated to make this modification because it allows for flexible modeling of processes where the timing between event is critical.
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Friedman in view of Yang et al. (U.S. Patent Application Pub. No. US 20190303104 A1), Liyanagedera, and further in view of Nishi.
Claim 20: Friedman teaches a neural network device comprising:
a first neuron circuit (i.e. FIG. 2 shows a diagram of an example neuromorphic network 100, according to an embodiment of the invention, comprising electronic neurons 101, 102, 103, 104, 105, 106 and 107 interconnected via synapses 22. Each of the synapses 22 includes a variable state resistor 23 and a FET 25, as described above. In each synapse 22, the resistor 23 comprises a PCM device connected in series with the drain terminal D of a FET 25, wherein the source terminal S of the FET 25 functions as an axon a, the gate terminal G of the FET 25 functions as a gating membrane m, and the top electrode of the resistor 23 functions as a dendrite d. The interconnections between the neurons and synapses in FIG. 2 is based on a cross-bar array, such as shown in FIG. 1. The neurons comprise CMOS circuits for integrate-and-fire functions to implement binary probabilistic STDP in synapses 22; para. [0052]);
a conversion circuit that converts a spike signal from the first neuron circuit to a synapse current according to a weight signal (i.e. As shown by example in FIG. 10B, in one embodiment, an axon driver X3 comprises a timing circuit 453 and a level generator circuit 454. When the driver X3 receives a spike signal from a neuron, the level generator circuit 454 of the driver X3 generates axonal signals. In one example, such an axonal signal comprises an axonal spike signal about 0.1 ms long used for forward communication of the neuron spike signal. The spike signal creates a voltage bias across a corresponding synaptic device 22 (FIG. 10A), resulting in a current flow into down-stream neurons, such that the magnitude of the current is weighted by the conductance of the corresponding synaptic device 22; para. [0086]);
a transmission circuit that transmits the converted synapse current to a second neuron circuit (i.e. As shown by example in FIG. 10B, in one embodiment, an axon driver X3 comprises a timing circuit 453 and a level generator circuit 454. When the driver X3 receives a spike signal from a neuron, the level generator circuit 454 of the driver X3 generates axonal signals. In one example, such an axonal signal comprises an axonal spike signal about 0.1 ms long used for forward communication of the neuron spike signal. The spike signal creates a voltage bias across a corresponding synaptic device 22 (FIG. 10A), resulting in a current flow into down-stream neurons, such that the magnitude of the current is weighted by the conductance of the corresponding synaptic device 22; para. [0086]);
a holding circuit that holds and supplies the weight signal a state of which is discretely changeable (i.e. the invention provides a probabilistic asynchronous neuromorphic network for producing spike-timing dependent plasticity. The network comprises a plurality of electronic neurons and an interconnect circuit coupled to the plurality of electronic neurons to interconnect the plurality of electronic neurons. The interconnect circuit comprises a plurality of axons and a plurality of dendrites such that the axons and dendrites are orthogonal to one another. The interconnect circuit further comprises plural synaptic devices for interconnecting the electronic neurons via axons and dendrites, such that each synaptic device comprises a binary state memory device at a cross-point junction of the interconnect circuit coupled between a dendrite and an axon; para. [0008, 0095); and
a control circuit that provides a control signal repeatedly to the holding circuit (i.e. A timing controller generates a timing signal for controlling phased operation of the electronic neurons. The timing signal provides a sequence of phases, wherein activity of each electronic neuron is confined to said phases such that the synaptic devices provide spike-timing dependent plasticity based on the activity of the electronic neurons in a time phased fashion; para. [0007, 0093]),
wherein the holding circuit includes a memory cell connected between the control circuit and the conversion circuit (i.e. Embodiments of the invention provide a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path; para. [0006, 0034, 0052]),
a first AND circuit having a first input node connected to a first number generator and a second input node connected to the control circuit (i.e. Each driver circuit X2 and X3 includes a stochastic signal generator 250A shown in FIG. 11 that generates a signal with a probability of occurrence that decays as a function of the time elapsed since the last spiking of a corresponding electronic neuron. The stochastic signal generator 250A comprises a cyclic counter 251 that is constantly updating its value (i.e., always-on counter), a spike dependent counter 252 that is initiated when an external alter signal (such as neuron spiking signal) is received, and a comparator 253 that compares the value of the spike dependent counter to the value of the cyclic counter upon receiving a request signal. If the value of the spike dependent counter is greater than the value of the cyclic counter, the comparator 253 causes a pulse module 254 to generate a stochastic binary enable pulse. The term “binary” means that each pulse is being used to represent one of two possible data values; para. [0093-0095, 0101]),
a second AND circuit having a first input node connected to a second number generator and a second input node connected to the control circuit (i.e. Each driver circuit X2 and X3 includes a stochastic signal generator 250A shown in FIG. 11 that generates a signal with a probability of occurrence that decays as a function of the time elapsed since the last spiking of a corresponding electronic neuron. The stochastic signal generator 250A comprises a cyclic counter 251 that is constantly updating its value (i.e., always-on counter), a spike dependent counter 252 that is initiated when an external alter signal (such as neuron spiking signal) is received, and a comparator 253 that compares the value of the spike dependent counter to the value of the cyclic counter upon receiving a request signal. If the value of the spike dependent counter is greater than the value of the cyclic counter, the comparator 253 causes a pulse module 254 to generate a stochastic binary enable pulse. The term “binary” means that each pulse is being used to represent one of two possible data values; para. [0093-0095, 0101]),
a first counter connected between the first circuit and the memory cell (i.e. The sense amplifier devices X4 feed into excitatory spiking electronic neurons (Ne) 14, 16 and 18, which in turn connect into the axon driver devices X3 and dendrite driver devices X2. The neuron 20 is an inhibitory spiking electronic neuron (Ni). Generally, an excitatory spiking electronic neuron makes its target neurons more likely to fire, while an inhibitory spiking electronic neuron makes its target neurons less likely to fire. A variety of implementations of spiking electronic neurons can be utilized. Generally, such neurons comprise a counter that increases when inputs from source excitatory neurons are received and decreases when inputs from source inhibitory neurons are received. The amount of the increase or decrease is dependent on the strength of the connection from a source neuron to a target neuron. If the counter reaches a certain threshold, the neuron then generates its own spike (i.e., fires) and the counter undergoes a reset to a baseline value. The term spiking electronic neuron is referred to as “electronic neuron” herein; para. [0042, 0055]), and
a second counter connected between the second circuit and the memory cell in parallel with the first counter (i.e. The sense amplifier devices X4 feed into excitatory spiking electronic neurons (Ne) 14, 16 and 18, which in turn connect into the axon driver devices X3 and dendrite driver devices X2. The neuron 20 is an inhibitory spiking electronic neuron (Ni). Generally, an excitatory spiking electronic neuron makes its target neurons more likely to fire, while an inhibitory spiking electronic neuron makes its target neurons less likely to fire. A variety of implementations of spiking electronic neurons can be utilized. Generally, such neurons comprise a counter that increases when inputs from source excitatory neurons are received and decreases when inputs from source inhibitory neurons are received. The amount of the increase or decrease is dependent on the strength of the connection from a source neuron to a target neuron. If the counter reaches a certain threshold, the neuron then generates its own spike (i.e., fires) and the counter undergoes a reset to a baseline value. The term spiking electronic neuron is referred to as “electronic neuron” herein; para. [0042, 0055]),
wherein a counting probability over multiple operations of each of the first counter and the second counter (i.e. The sense amplifier devices X4 feed into excitatory spiking electronic neurons (Ne) 14, 16 and 18, which in turn connect into the axon driver devices X3 and dendrite driver devices X2. The neuron 20 is an inhibitory spiking electronic neuron (Ni). Generally, an excitatory spiking electronic neuron makes its target neurons more likely to fire, while an inhibitory spiking electronic neuron makes its target neurons less likely to fire. A variety of implementations of spiking electronic neurons can be utilized. Generally, such neurons comprise a counter that increases when inputs from source excitatory neurons are received and decreases when inputs from source inhibitory neurons are received. The amount of the increase or decrease is dependent on the strength of the connection from a source neuron to a target neuron. If the counter reaches a certain threshold, the neuron then generates its own spike (i.e., fires) and the counter undergoes a reset to a baseline value. The term spiking electronic neuron is referred to as “electronic neuron” herein; para. [0042, 0055]) shows a variation along a shape (i.e. The binary pulse from the stochastic signal generator 250A programs a corresponding synapse device 22 including a binary state device (fully ON, fully OFF) at a cross-point junction of the array 12, to implement probabilistic binary STDP. The synapse device 22 is turned ON/OFF based on a probability represented by an example STDP graph 270 illustrated in FIG. 13. The synapse device 22 includes a memory device with two states, wherein the state of the memory device is changed probabilistically based on the pulse from the stochastic signal generator 250A. FIG. 13 shows the probability of changing state of the memory device in the synapse device 22 (vertical axis), normalized by the minimum between before and after state of synapse device 22, as a function of the timing between neuronal firing (horizontal axis); para. [0095]) with respect to the number of input times of the control signals (i.e. For the next 100 ms, the S1 and S2 phase signals are sent with same amplitude, but with decreasing probability. The amplitude of the signal generated by N1 at S1 and S2 is the same during successive S1 and S2 periods, only the probability of the signal being generated is decreasing; para. [0126]).
Friedman does not explicitly teach random number generator and AND circuit, a cumulative probability and a sigmoidal shape.
However, Yang teaches random number generator and AND circuit (i.e. Since the delay time characteristic of the diffusive memristor 260 is random, the output voltage pulse V.sub.3 (212) from the comparator 210 has a random width. Voltage V.sub.3 (FIG. 2b, Panel 3) and a high frequency clock signal 232 (V.sub.4) from the clock circuit 230 (FIG. 2b, Panel 4) are sent to inputs of the AND gate 220, whose output voltage pulses (V.sub.5 in FIG. 2b, Panel 5) are sent to the counter 240. The graph in FIG. 2b, Panel 6 shows the binary bit (counter 240 output at node 5, in red (250) in FIG. 2b, Panel 6) stays at its pre-status (“0”) before the diffusive memristor 260 is turned ON, flips rapidly (triggered by clock signals 232) until the single input pulse (V.sub.1) from the voltage source 202 ends and then stays at its post-status (“1”). The bit flipping in the counter 240 is triggered by the rising edge of the clock signal 232, and hence has a frequency half of the clock frequency (232). The bit on which the counter 240 stops is random, because the stochastic delay time of the diffusive memristor 260 leads to a random pulse width from the comparator 210 (V.sub.3) and thus a random number of clock pulses from the clock circuit 230 that are sent to the counter 240. In some implementations, the random bit generation rate of the diffusive memristor based TRNG circuit 200 is increased using a multi-bit counter, with which one stochastic volatile switching event can produce more than one binary bit; para. [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Friedman to include the feature of Yang. One would have been motivated to make this modification because it improves design clarity and reproducibility by using standard RNG and logic gate components.
However, Liyanagedera teaches a sigmoidal shape (i.e. Figure 4(b) depicts the variation of the switching probability of the MTJ with I Ibias, normalized by a factor Io. Io can be found by fitting the switching probability characteristics [Psw(:::)] to the sigmoid function; page 4) with respect to the number of input times of the control signals (i.e. Given a particular duration of write current owing through the device, a magnet exhibits a particular probability of switching during that corresponding write cycle. Consecutive write and read cycles can be used to generate an output pulse stream whose average value depends on the magnitude of the input stimulus; page 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman and Yang to include the feature of Liyanagedera. One would have been motivated to make this modification in order to accurately model and control the cumulative probability of weight updates over multiple control pulses.
However, Nishi teaches a cumulative switching probability (i.e. FIG. 18 is illustrated an exemplary relationship between the switching period and the cumulative probability of the resistance switch element 300 in which TaO.sub.x is used. That is, in FIG. 18 is illustrated a cumulative probability distribution of the period of time (the switching period) taken in the resistance switch element 300, in which TaO.sub.x is used, since the application of a fixed voltage in the high-resistance state up to transition to the low-resistance state. As can be understood from FIG. 18, the switching period is distributed across about triple digits, and it is indicated that the transition itself is stochastic. If the state of the resistance switch element 300 is to be switched at the rate of 20%, it can be understood from FIG. 18 that the voltage can be applied for 400 nanoseconds. That is, in FIG. 18, it takes 400 nanoseconds for the cumulative probability to reach 0.2; para. [0126, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Friedman, Yang, and Liyanagedera to include the feature of Nishi. One would have been motivated to make this modification in order to achieve predictable and controllable cumulative switching behavior over multiple control pulses in a neuromorphic circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Gupta et al. (Pub. No. US 20150170028 A1), when used in conjunction with spike timing-dependent plasticity (STDP), the bi-modality in distribution of weights may be reduced thereby making the learning more robust to stochasticity in synaptic firing or loss of synapses. In addition, performing parameter sweeps across different sets of neuronal parameters may also be improved.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
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/TAN H TRAN/Primary Examiner, Art Unit 2141
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