DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 19th, 2026 has been entered.
Claim Status
Claims 1, 7 and 16 have been amended. Claims 3, 6, 9, 13 and 15 have been cancelled. Claims 1-2, 4-5, 7-8, 10-12, 14 and 16-20 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 10, 14 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (US Publication No. 2020/0233606 -- "Duan") in view of Eno et al. (US Publication No. 2020/0097394 – “Eno”) in further view of Palmer (US Publication No. 2020/0210108 – “Palmer”) in further view of Canepa et al. (US Patent No. 10,140,027 – “Canepa”).
Regarding claim 7, Duan teaches A system, comprising: a memory component; and a processing device, operatively coupled with the memory component, to cause the memory component to: (Duan Figure 2; Duan paragraph [0016], FIG. 1 illustrates an example system 100 including a host 105 and a memory device 110. The host 105 can include a host processor, a central processing unit, or one or more other device, processor, or controller. The memory device 110 can include a universal flash storage (UFS) device, an embedded MMC (eMMC™) device, or one or more other memory devices. The host 105 and the memory device 110 can communicate using a communication interface (I/F) 115 (e.g., a bidirectional parallel or serial communication interface)) perform a first memory operation having a first type on a location of the memory component; (Duan paragraph [0015], Memory devices, particularly NVM devices, such as NAND flash devices, etc., can include arrays of multi-level memory cells. To program multi-level memory cells, a memory page buffer is stored with the value to be written to the memory cells. A first programming pulse is applied to the control gate of the memory cell at a voltage level that should not cause the threshold voltage of the memory cell to exceed the lowest threshold voltage of a target programmed data state of a multi-level memory cell. A read operation can then be performed to verify the threshold level to which the cell is programmed. A first memory operation to a location may be a read operation. Also see Duan paragraph [0041]) and in response to receipt of an access request to perform a second memory operation having a second type: (Duan paragraph [0041], The memory device 300 may perform a series of steps to handle a host read command. First, in step A, the firmware of the processor 330 receives and parses the read command, and then sends a read request to the memory array 301. In step B, the read request is executed, and data is transferred to the memory cache 442. In step C, the data is then transferred from the memory cache 442 to the read buffer 438 with ECC checking. Finally, in step D, the data is transferred from the read buffer 438 to the host 305. Multiple memory operations of varying types can be received to later be executed/performed).
Duan does not teach perform a second memory operation on the location of the memory component and prior to allowing the second memory operation to be performed, determine one of a plurality of time intervals based on a type of the second memory operation to be performed on the location of the memory component, wherein each one of the plurality of time intervals corresponds to a respective combination of types of memory operations performed on the memory component and to be performed on the memory component; and prevent, subsequent to completion of the first memory operation, the second memory operation from being performed for a period of time corresponding to the determined one of the plurality of time intervals; allow the second memory operation to be performed independently of the plurality of time intervals in response to the second memory operation having the first type, perform the second memory operation independently of the plurality of time intervals in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals.
However, Eno teaches perform a second memory operation on the location of the memory component and prior to allowing the second memory operation to be performed (Eno paragraph [0031], In addition, the controller 115 can define delays for operations on different partitions, same partitions, and same addresses. The controller 115 can provide improved throughput by processing operations with access patterns that move across partitions enabling command and data pipelining on the bus of the memory components 112A to 112N. Accesses to data in partitions that do not have a pattern that conforms to the defined delays can result in partition collision that introduces delay in command execution and data movement. In particular, a controller 115 may be forced to introduce time delays on the bus between two sequential write operations targeting the same partition. A delay can be calculated for operations targeting the same memory addresses/partitions) determine one of a plurality of time intervals based on a type of the second memory operation to be performed on the location of the memory component, wherein each one of the plurality of time intervals corresponds to a respective combination of types of memory operations performed on the memory component and to be performed on the memory component; (Eno paragraph [0031], In media types such as PCM, partitions are independent address bands on a die. Operations performed on an address band to move data to or from a partition conform to inter-command spacing rules. These spacing rules govern spacing between commands and data being presented on a bus of the memory components 112A to 112N, such as a set of dice. The media type of the memory components 112A to 112N and the controller 115 also define additional limitations on operations including rules related to write-to-write, write-to-read, and read-to-write spacing and delay. In addition, the controller 115 can define delays for operations on different partitions, same partitions, and same addresses. The controller 115 can provide improved throughput by processing operations with access patterns that move across partitions enabling command and data pipelining on the bus of the memory components 112A to 112N. Accesses to data in partitions that do not have a pattern that conforms to the defined delays can result in partition collision that introduces delay in command execution and data movement. In particular, a controller 115 may be forced to introduce time delays on the bus between two sequential write operations targeting the same partition. A delay can be determined between two memory operations performed on the same memory addresses, which can include memory operations of different types, as seen in Eno describing a read-to-write delay operation timer) and prevent, subsequent to completion of the first memory operation, the second memory operation from being performed for a period of time corresponding to the determined one of the plurality of time intervals (Eno paragraph [0031], Operations performed on an address band to move data to or from a partition conform to inter-command spacing rules. These spacing rules govern spacing between commands and data being presented on a bus of the memory components 112A to 112N, such as a set of dice. The media type of the memory components 112A to 112N and the controller 115 also define additional limitations on operations including rules related to write-to-write, write-to-read, and read-to-write spacing and delay. In addition, the controller 115 can define delays for operations on different partitions, same partitions, and same addresses. The delay results in postponing the second operation from being performed until the delay time interval has passed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan with those of Eno. Eno teaches introducing time intervals between memory operations targeted towards the same memory addressed/partitions, and can be based on operation type (including different operation types). This can be introduced to the memory system to minimize data collisions and delays (see Eno paragraph [0031], The controller 115 can provide improved throughput by processing operations with access patterns that move across partitions enabling command and data pipelining on the bus of the memory components 112A to 112N. Accesses to data in partitions that do not have a pattern that conforms to the defined delays can result in partition collision that introduces delay in command execution and data movement. In particular, a controller 115 may be forced to introduce time delays on the bus between two sequential write operations targeting the same partition. These time delays are an order of magnitude larger than sequential write operations that target different partitions. The wear-leveling manager 113 and/or the cartridge manager 121 organize a free pool of chunks for serving write requests to avoid this partition collision and thereby avoid these time delays on the bus of the memory components 112A to 112N).
Duan in view of Eno does not teach allow the second memory operation to be performed independently of the plurality of time intervals in response to the second memory operation having the first type, perform the second memory operation independently of the plurality of time intervals in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals.
However, Palmer teaches allow the second memory operation to be performed independently of the plurality of time intervals in response to the second memory operation having the first type (Palmer paragraph [0068], In certain examples, an array of NAND devices within a die or stack of die, and associated channels, can be limited to executing only read commands for a certain interval of time, and then switched to be limited to executing only write commands for a second interval of time. In certain examples, the memory controller can alternate the read only mode and write only mode of active channels to alleviate any particular buffered read command or write command from pending for an extended time. It is understood that the power consumption profile of a write command and a read command for each channel of the memory device can be benchmarked and well understood. Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget. When commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno with those of Palmer. Palmer teaches a modal operation processing, wherein commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately, which can improve the performance of memory system by optimizing performance when delay intervals are not required (i.e., see Palmer paragraph [0068], Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget).
Duan in view of Eno in further view of Palmer does not teach perform the second memory operation independently of the plurality of time intervals in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals.
However, Canepa teaches perform the second memory operation independently of the plurality of time intervals in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals (Canepa column 6; lines 30-42, The controller 112 is configured to adaptively adjust the various delay times that are encountered for various types of commands to better manage the issuance of status commands and match the actual performance of the MME 130. FIG. 6 shows the controller 112 in conjunction with various operational circuits that are incorporated into or otherwise utilized by the controller. As with the controller, the various circuits can be realized in hardware and/or firmware (programming) as desired. Various delays/time intervals can be utilized for different commands types; however, as shown in Canepa Fig. 6, certain commands not classified with delays can bypass the determined time intervals to be executed (i.e., read/write/erase commands), such as being executed immediately or utilizing a baseline delay, independent of the previously established time intervals (i.e., see Canepa column 9; lines 40-50, A data transfer command is initially issued by the controller 112 to the MME 130 at step 202. This may take any number of suitable forms, including a read command, a write command or an erase command. At step 204, the baseline value for the delay time associated with an address of the command (e.g., an address portion of the command as in FIG. 4) is recalled from memory (such as delay table 168, FIG. 6). The baseline value is used to initiate a timer (such as timer circuit 160, FIG. 6) to denote an elapsed time interval corresponding to the baseline value, step 206).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan, Eno and Palmer with those of Canepa. Canepa teaches the concept of utilizing time intervals/delays for given command types, including executing commands without delays when not classified with a determined delay time, which allows for certain commands to be executed with priority (Canepa column 9; lines 40-50, A data transfer command is initially issued by the controller 112 to the MME 130 at step 202. This may take any number of suitable forms, including a read command, a write command or an erase command. At step 204, the baseline value for the delay time associated with an address of the command (e.g., an address portion of the command as in FIG. 4) is recalled from memory (such as delay table 168, FIG. 6). The baseline value is used to initiate a timer (such as timer circuit 160, FIG. 6) to denote an elapsed time interval corresponding to the baseline value, step 206)).
Claim 1 is the corresponding method claim to system claim 7. It is rejected with the same references and rationale.
Regarding claim 8, Duan in view of Eno in further view of Palmer in further view of Canepa teaches The system of claim 7, wherein the processing device is further to cause the memory component to allow the second memory operation to be performed in response to the particular period of time having expired (Duan paragraph [0045], Active power consumption can be improved if certain steps of the read command can be slowed down without affecting read performance. In other words, the memory device can take advantage of a read command bottle neck process by slowing the other processes of the read command as long as the slowing doesn't increase the bottle neck or otherwise reduce the overall read performance. If one of steps A, B, C, or D is a bottleneck for the read command, the other steps may offer an opportunity for slowing down to reduce active power. In general, once the memory (e.g., type of flash) and the communication interface 315 (e.g., type of protocol) are decided for a storage device, the time for the memory read access (tB) and the time for a transfer via the communication interface (tD) are set and the processor or the firmware can't dynamically Change (tB) or (tD). However, time tA can be adjusted by changing the speed of the processor, and time tC can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus. Once the time interval for the initial memory operation has passed, the second memory operation may be performed).
Claim 2 is the corresponding method claim to system claim 8. It is rejected with the same references and rationale.
Regarding claim 10, Duan in view of Eno in further view of Palmer in further view of Canepa teaches The system of claim 7, wherein the processing device is further to cause the memory component to allow the second memory operation to be performed independently of the plurality of time intervals in response to the second memory operation having the first type instead of the second type (Duan paragraphs [0043-0044], This means the read performance is limited by the slowest step of the four read steps. The time needed to execute step A (tA) mostly depends on the speed of the processor 330. The faster the processor, the faster the processor firmware will handle the read command. The time to execute step B (tB) depends on the memory read performance (e.g., a flash read time). The time to execute step C (tC) depends on the transfer rate of the bus 336 and the decoding speed of the ECC engine 440. The time to execute step D (tD) depends on the speed of the communication interface 315 between the host 305 and the memory control unit 318. The time interval is only necessary in response to a particular command type being executed. For other command types, the latency can merely be the normal processing latency associated with all operations (i.e., no delay)).
Regarding claim 14, Duan in view of Eno in further view of Palmer in further view of Canepa teaches The system of claim 7, wherein the memory component comprises an array of NAND memory cells and the location corresponds to a block of the array (Duan paragraphs [0001-0002], Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), and magnetoresistive random access memory (MRAM), 3D XPoint™ memory, among others. Memory cells are typically arranged in a matrix or an array. Multiple matrices or arrays can be combined into a memory device, and multiple devices can be combined to form a storage volume of a memory system, such as a solid-state drive (SSD), a Universal Flash Storage (UFS™) device, a MultiMediaCard (MMC) solid-state storage device, an embedded MMC device (eMMC™), etc. The NAND memory may consist of an array comprised of cells, subdivided into blocks and then further into pages, also see Duan paragraph [0003], A memory system can include one or more processors or other memory controllers performing logic functions to operate the memory devices or interface with external systems. The memory matrices or arrays can include a number of blocks of memory cells organized into a number of physical pages. The memory system can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, erase operations to erase data from the memory devices, or perform one or more other memory operations).
Regarding claim 16, Duan teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: (Duan Figure 2; Duan paragraph [0016], FIG. 1 illustrates an example system 100 including a host 105 and a memory device 110. The host 105 can include a host processor, a central processing unit, or one or more other device, processor, or controller. The memory device 110 can include a universal flash storage (UFS) device, an embedded MMC (eMMC™) device, or one or more other memory devices. The host 105 and the memory device 110 can communicate using a communication interface (I/F) 115 (e.g., a bidirectional parallel or serial communication interface)) perform a first memory operation having a first type on a location of a memory component; (Duan paragraph [0015], Memory devices, particularly NVM devices, such as NAND flash devices, etc., can include arrays of multi-level memory cells. To program multi-level memory cells, a memory page buffer is stored with the value to be written to the memory cells. A first programming pulse is applied to the control gate of the memory cell at a voltage level that should not cause the threshold voltage of the memory cell to exceed the lowest threshold voltage of a target programmed data state of a multi-level memory cell. A read operation can then be performed to verify the threshold level to which the cell is programmed. A first memory operation to a location may be a read operation. Also see Duan paragraph [0041]) receive an access request to perform a second memory operation having a second type on the location of the memory component; in response to a second memory operation having a second type: (Duan paragraph [0039], A sequential memory access request (write or read) references multiple blocks of data. The blocks of data may be in contiguous logical address space. The sequential access request may include one logical address (e.g., a base address) or a range of logical addresses for the access request. For sequential write and read, the command chunk size is larger (e.g., 128 kilobytes (128 KB) to 512 KB) and sequential write and read can require a high throughput for the device interface and memory bus. For random write and random read, the demand on the device interface and memory bus is less because the command chunk size is smaller. Several memory commands/access requests may be issued for identical memory locations. Duan paragraph [0041], The memory device 300 may perform a series of steps to handle a host read command. First, in step A, the firmware of the processor 330 receives and parses the read command, and then sends a read request to the memory array 301. In step B, the read request is executed, and data is transferred to the memory cache 442. In step C, the data is then transferred from the memory cache 442 to the read buffer 438 with ECC checking. Finally, in step D, the data is transferred from the read buffer 438 to the host 305. Multiple memory operations of varying types can be received to later be executed/performed).
Duan does not teach determine, prior to allowing the second memory operation to be performed, one of a plurality of time intervals based on the second type, wherein each one of the plurality of time intervals corresponds to a respective combination of types of memory operations performed on the memory component and to be performed on the memory component; and allow the second memory operation to be performed on the location in response to a period of time corresponding to the determined one of the plurality of time intervals having expired subsequent to completion of the first memory operation; in response to the second memory operation having the first type, allow the second memory operation to be performed independently of respective periods of time corresponding to the plurality of time intervals; and in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals, allow the second memory operation to be performed independently of the respective periods of time corresponding to the plurality of time intervals.
However, Eno teaches determine, prior to allowing the second memory operation to be performed, one of a plurality of time intervals based on the second type, wherein each one of the plurality of time intervals corresponds to a respective combination of types of memory operations performed on the memory component and to be performed on the memory component; (Eno paragraph [0031], In media types such as PCM, partitions are independent address bands on a die. Operations performed on an address band to move data to or from a partition conform to inter-command spacing rules. These spacing rules govern spacing between commands and data being presented on a bus of the memory components 112A to 112N, such as a set of dice. The media type of the memory components 112A to 112N and the controller 115 also define additional limitations on operations including rules related to write-to-write, write-to-read, and read-to-write spacing and delay. In addition, the controller 115 can define delays for operations on different partitions, same partitions, and same addresses. The controller 115 can provide improved throughput by processing operations with access patterns that move across partitions enabling command and data pipelining on the bus of the memory components 112A to 112N. Accesses to data in partitions that do not have a pattern that conforms to the defined delays can result in partition collision that introduces delay in command execution and data movement. In particular, a controller 115 may be forced to introduce time delays on the bus between two sequential write operations targeting the same partition.A delay can be determined between two memory operations performed on the same memory addresses, which can include memory operations of different types, as seen in Eno describing a read-to-write delay operation timer) and allow the second memory operation to be performed on the location in response to a period of time corresponding to the determined one of the plurality of time intervals having expired subsequent to completion of the first memory operation; (Eno paragraph [0031], Operations performed on an address band to move data to or from a partition conform to inter-command spacing rules. These spacing rules govern spacing between commands and data being presented on a bus of the memory components 112A to 112N, such as a set of dice. The media type of the memory components 112A to 112N and the controller 115 also define additional limitations on operations including rules related to write-to-write, write-to-read, and read-to-write spacing and delay. In addition, the controller 115 can define delays for operations on different partitions, same partitions, and same addresses. The delay results in postponing the second operation from being performed until the delay time interval has passed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan with those of Eno. Eno teaches introducing time intervals between memory operations targeted towards the same memory addressed/partitions, and can be based on operation type (including different operation types). This can be introduced to the memory system to minimize data collisions and delays (see Eno paragraph [0031], The controller 115 can provide improved throughput by processing operations with access patterns that move across partitions enabling command and data pipelining on the bus of the memory components 112A to 112N. Accesses to data in partitions that do not have a pattern that conforms to the defined delays can result in partition collision that introduces delay in command execution and data movement. In particular, a controller 115 may be forced to introduce time delays on the bus between two sequential write operations targeting the same partition. These time delays are an order of magnitude larger than sequential write operations that target different partitions. The wear-leveling manager 113 and/or the cartridge manager 121 organize a free pool of chunks for serving write requests to avoid this partition collision and thereby avoid these time delays on the bus of the memory components 112A to 112N).
Duan in view of Eno does not teach in response to the second memory operation having the first type, allow the second memory operation to be performed independently of respective periods of time corresponding to the plurality of time intervals; and in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals, allow the second memory operation to be performed independently of the respective periods of time corresponding to the plurality of time intervals.
However, Palmer teaches in response to the second memory operation having the first type, allow the second memory operation to be performed independently of respective periods of time corresponding to the plurality of time intervals (Palmer paragraph [0068], In certain examples, an array of NAND devices within a die or stack of die, and associated channels, can be limited to executing only read commands for a certain interval of time, and then switched to be limited to executing only write commands for a second interval of time. In certain examples, the memory controller can alternate the read only mode and write only mode of active channels to alleviate any particular buffered read command or write command from pending for an extended time. It is understood that the power consumption profile of a write command and a read command for each channel of the memory device can be benchmarked and well understood. Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget. When commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno with those of Palmer. Palmer teaches a modal operation processing, wherein commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately, which can improve the performance of memory system by optimizing performance when delay intervals are not required (i.e., see Palmer paragraph [0068], Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget).
Duan in view of Eno in further view of Palmer does not teach in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals, allow the second memory operation to be performed independently of the respective periods of time corresponding to the plurality of time intervals.
However, Canepa teaches in response to the one of the plurality of time intervals not being determined due to the respective types of the first and the second memory operations not corresponding to a respective set of types defined in association with the plurality of time intervals, allow the second memory operation to be performed independently of the respective periods of time corresponding to the plurality of time intervals (Canepa column 6; lines 30-42, The controller 112 is configured to adaptively adjust the various delay times that are encountered for various types of commands to better manage the issuance of status commands and match the actual performance of the MME 130. FIG. 6 shows the controller 112 in conjunction with various operational circuits that are incorporated into or otherwise utilized by the controller. As with the controller, the various circuits can be realized in hardware and/or firmware (programming) as desired. Various delays/time intervals can be utilized for different commands types; however, as shown in Canepa Fig. 6, certain commands not classified with delays can bypass the determined time intervals to be executed (i.e., read/write/erase commands), such as being executed immediately or utilizing a baseline delay, independent of the previously established time intervals (i.e., see Canepa column 9; lines 40-50, A data transfer command is initially issued by the controller 112 to the MME 130 at step 202. This may take any number of suitable forms, including a read command, a write command or an erase command. At step 204, the baseline value for the delay time associated with an address of the command (e.g., an address portion of the command as in FIG. 4) is recalled from memory (such as delay table 168, FIG. 6). The baseline value is used to initiate a timer (such as timer circuit 160, FIG. 6) to denote an elapsed time interval corresponding to the baseline value, step 206)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan, Eno and Palmer with those of Canepa. Canepa teaches the concept of utilizing time intervals/delays for given command types, including executing commands without delays when not classified with a determined delay time, which allows for certain commands to be executed with priority (Canepa column 9; lines 40-50, A data transfer command is initially issued by the controller 112 to the MME 130 at step 202. This may take any number of suitable forms, including a read command, a write command or an erase command. At step 204, the baseline value for the delay time associated with an address of the command (e.g., an address portion of the command as in FIG. 4) is recalled from memory (such as delay table 168, FIG. 6). The baseline value is used to initiate a timer (such as timer circuit 160, FIG. 6) to denote an elapsed time interval corresponding to the baseline value, step 206)).
Regarding claim 17, Duan in view of Eno and further in view of Palmer in further view of Canepa teaches The non-transitory computer-readable storage medium of claim 16, wherein the processing device is further to prevent, subsequent to completion of the first memory operation, the second memory operation from being performed on the location for the period of time in response to the second memory operation having the second type (Duan paragraphs [0024-0025], Memory device 200 can perform a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells 210, or a write (e.g., program) operation to store (e.g., program) information in memory cells 210. Memory device 200 can use data lines 270 associated with signals BL0 through BLn to provide information to be stored in memory cells 210 or obtain information read (e.g., sensed) from memory cells 210. Memory device 200 can also perform an erase operation to erase information from some or all of memory cells 210 of blocks 290 and 291. Memory device 200 can include a memory control unit 218 (which can include components such as a state machine (e.g., finite state machine), register circuits, and other components) configured to control memory operations (e.g., read, write, and erase operations) of memory device 200 based on control signals on lines 204. Examples of the control signals on lines 204 include one or more clock signals and other signals (e.g., a chip enable signal CE#, a write enable signal WE#) to indicate which operation (e.g., read, write, or erase operation) memory device 200 can perform. Subsequent memory operations, such as the second memory operation, may be delayed or halted for a given time interval corresponding to the execution of the first memory operation).
Regarding claim 18, Duan in view of Eno and further in view of Palmer in further view of Canepa teaches The non-transitory computer-readable storage medium of claim 16, wherein a memory operation having the first type corresponds to a program operation or an erase operation (Duan paragraphs [0024-0025], Memory device 200 can also perform an erase operation to erase information from some or all of memory cells 210 of blocks 290 and 291. Memory device 200 can include a memory control unit 218 (which can include components such as a state machine (e.g., finite state machine), register circuits, and other components) configured to control memory operations (e.g., read, write, and erase operations) of memory device 200 based on control signals on lines 204. Examples of the control signals on lines 204 include one or more clock signals and other signals (e.g., a chip enable signal CE#, a write enable signal WE#) to indicate which operation (e.g., read, write, or erase operation) memory device 200 can perform. The initial memory operation command type can be erase operations designed to clear the memory).
Regarding claim 19, Duan in view of Eno and further in view of Palmer in further view of Canepa teaches The non-transitory computer-readable storage medium of claim 16, wherein a memory operation having the second type corresponds to a program operation, an erase operation, or a read operation (Duan paragraph [0061], At 715, the operating rates of one or more first components of the memory device are reduced when the queued access requests are to sequential addresses of the memory array. At 720, the operating rates of one or more second components of the memory device are reduced when the queued access requests are to random addresses of the memory array. The memory control unit may include a processor as one of the first components. The memory control unit may reduce the operating rate of the processor when the queued access requests are to sequential addresses of the memory array. The access requests may be either sequential read requests or sequential write requests. The memory control unit may include logic circuitry to reduce the operating rate by reducing the frequency of the clock signal provided to operate the processor. The frequency can be reduced as long as the slower operation of the processor does not impact the overall performance. The lower limit of the frequency would be the point where slowing the parsing of the read/write commands and sending the access requests to the memory array begins to create a new bottle neck of performance of sequential address requests. The secondary memory operations (memory operations of the second type), can be comprised of various command types, such as a read/write or erase operation).
Regarding claim 20, Duan in view of Eno and further in view of Palmer in further view of Canepa teaches The non-transitory computer-readable storage medium of claim 16, wherein the processing device is further to allow the second memory operation to be performed within the period of time subsequent to completion of the first memory operation in response to the second memory operation having the first type (Palmer paragraph [0068], In certain examples, an array of NAND devices within a die or stack of die, and associated channels, can be limited to executing only read commands for a certain interval of time, and then switched to be limited to executing only write commands for a second interval of time. In certain examples, the memory controller can alternate the read only mode and write only mode of active channels to alleviate any particular buffered read command or write command from pending for an extended time. It is understood that the power consumption profile of a write command and a read command for each channel of the memory device can be benchmarked and well understood. Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget. When commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno with those of Palmer. Palmer teaches a modal operation processing, wherein commands of the same type are performed, the interval can be ignored and sequential commands can be performed immediately, which can improve the performance of memory system by optimizing performance when delay intervals are not required (i.e., see Palmer paragraph [0068], Consequently, the example modal operation of the memory device, where during a determined interval, all operations for a channel are of the same type, highly optimized individual active die count and command sequencing schemes can be determined by the controller for the read mode and write mode such that each mode provides high performance while conforming to the power budget).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan in view of Eno in further view of Palmer in further view of Canepa as applied to claims 1 and 7 above, and further in view of Chang et al. (US Publication No. 2008/0239861 -- "Chang2008").
Regarding claim 4, Duan in view of Eno in further view Palmer and further in view Canepa and further in view of Chang2008 teaches The method of claim 3, wherein allowing the second memory operation to be performed independently of whether the period of time has expired or not further comprises allowing the second memory operation to be performed within the period of time subsequent to completion of the first memory operation (Chang2008 paragraph [0031], In another embodiment of the present invention, the present invention can divide the memory banks of the memory into a plurality of memory groups as shown in FIG. 4. FIG. 4 is a schematic diagram illustrating the memory structure according to another embodiment of the present invention. A memory 400 includes memory groups 410˜440 and driving powers 415, 425, 435, and 445. Herein, the memory group 410 includes memory banks A401˜A404, the memory group 420 includes memory banks B401˜B404, the memory group 430 includes memory banks C401˜C404, and the memory group 440 includes memory banks D401˜D404. The minimum time interval for the memory 400 to select a row from one of the memory groups 410˜440 to selecting a row in another group is known as tRRD-inter. On the other hand, the minimum time interval for the memory 400 to select a row from any of the memory groups 410˜440 to another row in the same memory group is known as tRRD-intra. Please refer to FIG. 5. When the memory 400 selects the memory banks A401˜A404 of the memory group 410 according to the active signal ACT1, the memory 400 can select any of the memory groups 420, 430 and 440 according to the next active signal. Next, the memory 400 can return to the memory group 410 to select another row. In other words, the memory 400 can switch among the memory groups 410˜440 to increase the speed for reading out data and selecting operation of the memory banks to prevent the generation of bubbles. Please refer to the description of FIG. 3 for the remaining operation procedure of the embodiment of FIG. 4. Hence, a detailed description thereof is omitted. The time interval delay between the memory operations can be modified or removed for certain operations not previously mentioned, where the time interval delay is either unnecessary or far too large).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno and Palmer and Canepa with those of Chang2008. Chang2008 teaches performing a second memory operation independent of a time interval delay previously established based on command type combinations. In this case, the memory can operate at a faster speed by either shortening or removing the time interval delay when the command combination does not necessitate a time interval of the established duration (Chang2008 paragraph [0037], The present invention divides memory banks of the memory into different memory groups adapted for different tRRD times in order to increase the speed of the memory in selecting rows among different memory groups and reading data, reducing the generation of bubbles. Also see Chang2008 paragraph [0034], After the memory 310 has received a read command that corresponds to a memory bank such as A301 and the time interval CL has passed (i.e. seven clock cycles in the present embodiment), the read data is outputted to the bus. As shown by the data row in FIG. 5, data DATA1˜DATA3 are outputted sequentially. As a result, no bubble is generated. Comparing FIG. 5 to the conventional art shown in FIG. 2, it is obvious that the present invention has higher data output efficiency).
Claim(s) 5 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan in view of Eno in further view of Palmer in further view of Canepa, as applied to claims 1 and 7 above, and further in view of King (US Publication No. 2015/0356048 -- "King").
Regarding claim 5, Duan in view of Eno in further view of Palmer in further view of Canepa and further in view of King teaches The method of claim 1, wherein the particular time interval is one of a plurality of time intervals, and wherein the method further comprises: receiving access requests to perform a plurality of memory operations on the location of the memory component; (Duan paragraph [0039], A sequential memory access request (write or read) references multiple blocks of data. The blocks of data may be in contiguous logical address space. The sequential access request may include one logical address (e.g., a base address) or a range of logical addresses for the access request. For sequential write and read, the command chunk size is larger (e.g., 128 kilobytes (128 KB) to 512 KB) and sequential write and read can require a high throughput for the device interface and memory bus. For random write and random read, the demand on the device interface and memory bus is less because the command chunk size is smaller. Several memory commands/access requests may be issued for identical memory locations) determining a respective one of the plurality of time intervals associated with each set of consecutive memory operations of the plurality of memory operations; and performing the plurality of memory operations with the determined respective one of the plurality of time intervals to prevent a subsequent one of each set of consecutive memory operations from being performed within a respective period of time corresponding to the determined respective one of the plurality of time intervals subsequent to completion of a respective memory operation of the set (King paragraphs [0012-0013], This control, at least partially, may require the control logic to analyze a received command to determine for which memory die it is intended, and then to control the intended memory die to access the common bus so that the data and/or command is captured by the intended memory die at the appropriate time. To activate the intended memory die, the control logic may provide an active strobe signal to the memory die at a time when the data/command is on the bus or when the data should be put on the bus (this directional aspect may be command dependent, e.g., reads, writes, refreshes, and etc.). The active strobe signal may cause the intended memory die to capture information on the common bus or drive information onto the common bus. For example, the active strobe signal may cause an output or input pad of the intended memory die that is connected to the common bus to activate. Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines. As stated in King, the strobe signals may be used to indicate a command type for a first and second memory device, which may be selected between erase, read, and program operations. The choices made will result in different latency periods, given the different processing times associated with each. This inherently means that each of the above claimed combinations will comprise a unique corresponding latency, as well as other potential combinations for memory operations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno and Palmer and Canepa with those of King. King teaches using strobe signals to indicate a command type for a first and second memory operation. The command types selected will control the latency between the commands, as each of the different command types may have different processing requirements and speed. This allows the system far greater flexibility and performance when accounting for latency periods, rather than setting a singular latency period for any two command types (King paragraph [0013], Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines).
Regarding claim 11, Duan in view of Eno in further view of Palmer in further view of Canepa and further in view of King teaches The system of claim 7, wherein the plurality of time intervals further comprises: a first time interval associated with the first memory operation being a program operation and the second memory operation being a read operation; a second time interval associated with the first memory operation being an erase operation and the second memory operation being a program operation; and a third time interval associated with the first memory operation being a program operation and the second memory operation being an erase operation (King paragraphs [0012-0013], This control, at least partially, may require the control logic to analyze a received command to determine for which memory die it is intended, and then to control the intended memory die to access the common bus so that the data and/or command is captured by the intended memory die at the appropriate time. To activate the intended memory die, the control logic may provide an active strobe signal to the memory die at a time when the data/command is on the bus or when the data should be put on the bus (this directional aspect may be command dependent, e.g., reads, writes, refreshes, and etc.). The active strobe signal may cause the intended memory die to capture information on the common bus or drive information onto the common bus. For example, the active strobe signal may cause an output or input pad of the intended memory die that is connected to the common bus to activate. Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines. As stated in King, the strobe signals may be used to indicate a command type for a first and second memory device, which may be selected between erase, read, and program operations. The choices made will result in different latency periods, given the different processing times associated with each. This inherently means that each of the above claimed combinations will comprise a unique corresponding latency, as well as other potential combinations for memory operations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno and Palmer and Canepa with those of King. King teaches using a plurality of different command types and corresponding time intervals associated with each command operation/execution. The command types selected will control the latency between the commands, as each of the different command types may have different processing requirements and speed. This allows the system far greater flexibility and performance when accounting for latency periods, rather than setting a singular latency period for any two command types (King paragraph [0013], Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines).
Regarding claim 12, Duan in view of Eno in further view of Palmer in further view of Canepa and further in view of King teaches The system of claim 7, wherein periods of time corresponding to at least two of the plurality of time intervals are different (King paragraphs [0011-0013], Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines. As described above, different time intervals may be used for different command type combinations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Duan and Eno and Palmer and Canepa with those of King. King teaches using strobe signals to indicate a command type for a first and second memory operation. The command types selected will control the latency between the commands, as each of the different command types may have different processing requirements and speed. This allows the system far greater flexibility and performance when accounting for latency periods, rather than setting a singular latency period for any two command types (King paragraph [0013], Due to both the layout of a memory device including the multiple memory die and inherent differences between the operation of the multiple memory die, e.g., due to variations in processing, temperature, and voltages, their associated latency may be different. Each memory die may also have a different latency associated with the executing of different commands as well, e.g., a write latency may be different than a read latency. The latency of each memory die may be accounted for by the use of delays in providing the strobe signals. For example, if a memory die is processing a read command, the control logic may delay transmitting the strobe signal for providing the data to the common bus due to the time the memory die takes to process the read command and ready the data in relation to an expected time to provide the data to the common bus. To account for these differences in latency, the control logic may use programmable delays to provide strobe signals to the various memory die. Depending on the number of memory die in the memory device, the amount of area on the control logic die consumed by strobe line driver circuits may be appreciable. To save area and power consumption, the control logic may include multiple strobe line driver circuits (instead of a dedicated driver circuit for each strobe line) that can be selectively connected to and shared by any of the dedicated strobe lines).
Response to Arguments
Applicant’s arguments, see pages 1-2 (numbered pages 7-8), filed February 19th, 2026, with respect to the rejection(s) of claim(s) 1, 7 and 16 under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Duan et al. (US Publication No. 2020/0233606 -- "Duan") in view of Eno et al. (US Publication No. 2020/0097394 – “Eno”) in further view of Palmer (US Publication No. 2020/0210108 – “Palmer”) in further view of Canepa et al. (US Patent No. 10,140,027 – “Canepa”).
The applicant’s amendments to the claim have overcome the previous 35 U.S.C. 112(a) and 35 U.S.C. 112(b) Rejections; however, a 35 USC 103 Rejection has been added using the combination of references cited above. Specifically, the Canepa reference has been newly added to the amended claim limitation, specifying perform certain command types independent of a determined plurality of time intervals, as described in further detail above. In light of the above rationale and references, the 35 U.S.C. 103 Rejection is made.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nowak (US Publication No. 2016/0139626) teaches utilizing time intervals/delays for specific types or specific combinations of command types, as well as executing commands at the current time if not associated with a set delay timer (i.e., see Nowak paragraphs [0109-0110], The method of any combination of examples 8-10, wherein each threshold value of the plurality of threshold values is selected from a plurality of predetermined threshold values that each indicate a respective minimum amount of time between times at which the controller may issue various combinations of the plurality of types of command segments. The method of any combination of examples 8-11, wherein the particular type of command segments is a second type of command segments, wherein the command segment of the second type of command segments may be issued at the current time, and wherein the method further comprises: determining, based on the plurality of timers, that a command segment of a third type of command segments of the plurality of types of command segments may not be issued at the current time).
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/J.C.K./ Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/ Supervisory Patent Examiner, Art Unit 2133
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