DETAILED ACTION
Remarks
This office action is issued in response to communication filed on 3/4/2026. Claims 1-12 and 30-31 are pending in this office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 3/4/26 with respect to rejection of claims under 35 USC 103 have been considered and are not persuasive. The examiner respectfully traverses applicant’s argument.
Applicant argues: “However, Venkatesh does not teach PE circuits within the same group processing an input at different depths in parallel. The Examiner appears to consider the layers described in paragraph [0062] of Venkatesh to correspond to the claimed depths. However, even given the Examiner's interpretation, Venkatesh would still fail to teach the above-recited features of claim 1. While Venkatesh teaches that some PE circuits 202A may be assigned to nodes within a first layer, and other PE circuits 202A may be assigned to nodes within a third layer, Venkatesh fails to teach the circuits 202A performing any parallel processing for the nodes in the first and
third layers. Rather, Venkatesh describes at paragraph [0062] that the first group of PE circuits 202A may perform processing for a second node of the first layer during a second time window and the second group 202B may perform processing for a first node for a second layer of the neural network during the second time window. Thus, parallel processing is performed by different groups of PEs (PE circuits 202A and 202B), not by PEs within the same group.”(Applicant’s arguments at page 6-7)
The examiner respectfully disagrees. Venkatesh par [0062] teaches “ In some embodiments, the first group of PE circuits 202A may perform processing for a first node (or a first subset of nodes) of a first layer during a first time window, generate first output(s) for the first node (or the first subset of nodes), and then perform processing for a second node (or a second subset of nodes) of the first layer during a second/subsequent time window, and generate second output(s) for the second node (or the second subset of nodes). The second group of PE circuits 202B may receive the first output(s) and perform processing for a first node (or a first subset of nodes) for a second layer of the neural network during the second time window, generate first output(s) for the first node (or the first subset of nodes) of the second layer, and then perform processing for a second node (or a second subset of nodes) of the second layer during a third time window, and generate second output(s) for the second node (or the second subset of nodes) of the second layer”. Clearly Venkatesh teaches the parallel processing using PE circuits from 202A and 202B. The collection of circuits from 202A and 202B is considered “group of PEs”. In other words, even though 202A and 202B are two different groups, the combination of 202A and 202B is interpreted as “group” and therefore, Venkatesh teaches “each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths in a neural network, wherein a PE circuit of the plurality of PE circuits within a group of the plurality groups is configured to process an input at a depth of the plurality of depths, and wherein another PE circuit of the plurality of PE circuits within the group is configured to process, in parallel with the PE circuit, the input at another depth of the plurality of depths” as recited in claim.
Applicant’s remaining arguments with respect to claims are substantially encompassed in the argument above, therefore examiner responds with the same rationale as stated above. For at least the foregoing reasons, the examiner maintains prior art rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Volpe et al. (US Patent 11,422,773 B1, hereinafter “Volpe”) and further in view of Venkatesh et al.(US Patent Application Publication 2021/0012186 A1, hereinafter “Venkatesh”)
As to claim 1, Volpe teaches a processing circuit comprising a plurality of groups of processing element (PE) circuits (Volpe col 2, lines 28-40 teaches an array of processing elements (PEs) arranged into rows and columns , wherein: each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths in a neural network. (Volpe’s abstract teaches enabling parallelized multiply -accumulate operations ),
[each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths in a neural network, wherein a PE circuit of the plurality of PE circuits within a group of the plurality groups is configured to process an input at a depth of the plurality of depths, and wherein another PE circuit of the plurality of PE circuits within the group is configured to process, in parallel with the PE circuit, the input at another depth of the plurality of depths]
each PE circuit comprises: one or more multiplication circuits , each multiplication circuit being configured to calculate a partial product (Volpe Fig.2 and col 29, lines 30-45 teaches multiplier 208) , and a local accumulator having an input coupled to an output of the one or more multiplication circuits, the local accumulator being configured to generate a sum from the partial product calculated by each of the one or more multiplication circuits.(Volpe Fig.2 and col 29, lines 30-45 teaches adder 210. Volpe col 32, lines 58-65 teaches multiplier 208 may provide the adder 210 with product 250 to perform an addition operation between the product 250 and a stored input partial sum )
Volpe fails to expressly teach each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths in a neural network, wherein a PE circuit of the plurality of PE circuits within a group of the plurality groups is configured to process an input at a depth of the plurality of depths, and wherein another PE circuit of the plurality of PE circuits within the group is configured to process, in parallel with the PE circuit, the input at another depth of the plurality of depths.
However, Venkatesh teaches each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths in a neural network, wherein a PE circuit of the plurality of PE circuits within a group of the plurality groups is configured to process an input at a depth of the plurality of depths, and wherein another PE circuit of the plurality of PE circuits within the group is configured to process, in parallel with the PE circuit, the input at another depth of the plurality of depths.(Venkatesh par [0062] teaches some PE circuits 202A may be assigned or mapped to node(nodes) within the first layer, while other PE circuits 202A may be assigned or mapped to node(s) within a third layer). The neural network may include layers of one or more nodes and the PE circuits 202 may be configured to perform both pipelined and parallel computations for the nodes and/or layers)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Venkatesh with Volpe to achieve the claimed invention. One would have been motivated to make such combination to improve performance, processing throughput and energy efficiency (Venkatesh par [0054])
As to claim 11, Volpe and Venkatesh teach the processing circuit of claim 1, further comprising a plurality of global accumulators, wherein each global accumulator has an input coupled to an output of one of the groups of PE circuits. (Volpe col 14, lines 50-63 teaches the aggregator 130 includes 3 adders, each of which may be configured to add partial sums generated by the column 120 of PEs)
As to claim 12, Volpe and Venkatesh teach the processing circuit of claim 1, wherein the plurality of PE circuits is further configured to process in parallel a plurality of inputs at a plurality of depths.(Volpe col 4, lines 35-40 teaches parallel accumulation can occur with respect to each bus of a column)
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Volpe, Venkatesh and further in view of Liu et al.(US Patent Application Publication 2022/0383081 A1, hereinafter “Liu”)
As to claim 2, Volpe and Venkatesh teach the processing circuit of claim 1 but fail to teach wherein each PE circuit further comprises: a register having an input coupled to an output of the local accumulator.
However, Liu teaches wherein each PE circuit further comprises: a register having an input coupled to an output of the local accumulator.(Liu par [0006] teaches a third register coupled to the MAC unit to store an output for the MAC unit)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Liu with Volpe and Venkatesh to achieve the claimed invention. One would have been motivated to make such combination to improve the efficiency of the operation in neural network by reducing memory accesses and memory latencies (Liu par [0113])
As to claim 3, Volpe, Venkatesh and Liu teach the processing circuit of claim 2, further comprising a plurality of global accumulators (Volpe col 12, lines 47-50 teaches each column of PEs ay include an aggregator), wherein an output of the register in each PE circuit is coupled to the input of another register in another PE circuit in the group of PE circuits or to an input of one of the global accumulators.(Liu par [0006] teaches connecting output of a PE to an input of another PE )
As to claim 4, Volpe Venkatesh and Liu teach processing circuit of claim 3, further comprising a bus, wherein another output of the register in each PE circuit is coupled to the bus. (Liu par [0006] teaches connecting the first register of a PE to the first data bus)
As to claim 5, Volpe , Venkatesh and Liu teach the processing circuit of claim 4, wherein an output of each of the global accumulators is further coupled to the bus. ( Volpe col 2, lines 35-40 teaches the partial sum may accumulate in each column of the array such that an adder at the base of each column can combine the partial sums of each PE within the column to obtain final sum for the column. Volpe col 4, lines 35-40 teaches parallel accumulation can occur with respect to each bus of a column)
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Volpe, Venkatesh , Liu and further in view of Elmer.(US Patent 11,842,169 B1, hereinafter Elmer”)
As to claim 6, Volpe , Venkatesh and Liu teach the processing circuit of claim 2, wherein each PE circuit further comprises a first selection circuit having a first input coupled to the output of the local accumulator (Volpe col 33, lines 30-37 teaches the selector circuit 216 may receive the addition result 238 and the input partial sum 236 to generate an output partial sum 240) and having an output coupled to the input [of the register]. (Volpe Fig.2 and col 33, lines 30-40 teaches selector circuit 216 generates output partial sum 240)
Volpe, Venkatesh and Liu fail to expressly teach the output coupled to the input of the register.
However, Elmer teaches having an output coupled to the input of the register. (Elmer Fig.2 and col 10, lines 55-65 teaches input partial sum resister 218)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Volpe , Venkatesh , Liu and Elmer to achieve the claimed invention. One would have been motivated to make such combination to reduce gate count and dynamic power consumption.(Elmer col 4, lines 1-5)
As to claim 7, Volpe, Venkatesh , Liu and Elmer teach the processing circuit of claim 6, wherein the first selection circuit in each PE circuit has a second input coupled to an output of the register. (Elmer Fig.2 shows output of register 215 connects with selector 216 )
As to claim 8, Volpe, Venkatesh , Liu and Elmer teach the processing circuit of claim 7, wherein the first selection circuit comprises a 2:1 multiplexer, a tri-state buffer, or a plurality of switches. (Volpe col 33 , lines 30-40 teaches the selector circuit 216 may contain at least one multiplexer, the multiplexer may select the addition result 238 or the input partial sum 236 to be produced)
As to claim 9, Volpe, Venkatesh, Liu and Elmer teach the processing circuit of claim 6, wherein at least some of the PE circuits in each group of PE circuits further comprise a second selection circuit having an output coupled to the input of the register(Elmer Fig.2 and col 10, lines 55-65 teaches input partial sum resister 218 (when connects with second PE, the 218 register becomes the input that connects with the out of 240 of the current PE), having a first input coupled to an output of the register (Elmer Fig.2 shows selector 216 connects with output of register 218), and having a second input coupled to an output of another register in another PE circuit in the group of PE circuits. (Elmer Fig.2 shows selector 216 connects with register 215)
As to claim 10, Volpe, Venkatesh , Liu and Elmer teach the processing circuit of claim 9, wherein the second selection circuit comprises a 2:1 multiplexer, a tri-state buffer, or a plurality of switches. (Volpe col 33 , lines 30-40 teaches the selector circuit 216 may contain at least one multiplexer, the multiplexer may select the addition result 238 or the input partial sum 236 to be produced)
Claims 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Volpe, Venkatesh and further in view of Tran et al.(US Patent Application Publication 2023/0344962 A1, hereinafter “Tran”)
As to claim 30, Volpe and Venkatesh teach the processing circuit of claim 1 but fail to expressly teach wherein: the input comprises data from a three-dimensional space, a first dimension in the three-dimensional space corresponds to a horizontal dimension, a second dimension in the three-dimensional space corresponds to a vertical dimension, and a third dimension in the three-dimensional space corresponds to a depth dimension having the plurality of depths.
However, Tran teaches wherein: the input comprises data from a three-dimensional space, a first dimension in the three-dimensional space corresponds to a horizontal dimension, a second dimension in the three-dimensional space corresponds to a vertical dimension, and a third dimension in the three-dimensional space corresponds to a depth dimension having the plurality of depths. (Tran par [0024] teaches The CNN performing the interpolation may include any number of convolutional layers for encoding and decoding the video data, at least some of which perform three-dimensional (3D) convolution operations for each channel of the input video frames in the spatial and temporal dimensions. For example, each image frame may be of size W (width)×H (height) and may have multiple channels six frames of the stack in the temporal dimension, or “depth”, of the input feature set)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Volpe , Venkatesh and Tran to achieve the claimed invention. One would have been motivated to make such combination to significantly improve inference speed.(Tran par [0004])
As to claim 31, Volpe , Venkatesh and Tran teach the processing circuit of claim 30, wherein: the data from the three-dimensional space comprises video data, and the depth dimension corresponds to a temporal channel in the video data.(Tran par [0024] teaches each image frame may be of size W (width)×H (height) and may have multiple channels six frames of the stack in the temporal dimension, or “depth”, of the input feature set)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEN DUONG whose telephone number is (571)270-7335. The examiner can normally be reached Monday-Friday 8:00AM-5:00PM.
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/HIEN L DUONG/Primary Examiner, Art Unit 2147
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