DETAILED ACTION
Claims 1-3, 5-10 and 12-20 are pending in this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 8-10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hamlin et al. (US PGPUB No. 2017/0147801) [hereinafter “Hamlin”] in view of Woolley et al. (US PGPUB No. 2015/0199520) [hereinafter “Woolley”] in further view of Ansari et al. (WO-2022015347-A1) [hereinafter “Ansari”] in further view of Bryant-Rich (US PGPUB No. 2010/0205350) in further view of Doshi et al. (US PGPUB No. 2017/0185354) [hereinafter “Doshi”] in further view of Kotary et al. (US PGPUB No. 2020/0285403) [hereinafter “Kotary”].
As per claim 1, Hamlin teaches a system comprising: a memory device ([0014], mass storage device); and a processing device ([0014], processor), operatively coupled with the memory device, to perform operations ([0014] and Fig. 2, processor coupled to memory via bus) comprising: receiving, from a host system, an identification command ([0016], request for PBA object includes a request an identifier to locate object); transmitting an access command to the memory device ([0032], request a PBA object pointer to access a PBA object), the access command comprising an identification of a first physical super management unit (PSMU) at a first location of the memory device storing a security file system ([0015]-[0016], access request made to secure subsystem at a first location with an object directory which is interpreted act as a physical super “management unit”), wherein data for the host system is stored at a second location of the memory device ([0032], the request is a “pointer” where the actual object is at a second location in memory).
Hamlin does not explicitly teach responsive to transmitting the access command, receiving one or more security files from the security file system and executing the security procedure in response to receiving the one or more security files and concurrently with executing a power up initialization of the memory device. Woolley teaches responsive to transmitting the access command, receiving one or more security files from the security file system ([0034], using pointer to access command sequence file) and executing the security procedure in response to receiving the one or more security files ([0034], executing a series of security checks and rules after receiving command sequence file) and concurrently with executing a power up initialization of the memory device ([0033], steps are included a three phase secure boot sequence, i.e. power up see Abstract and [0002]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin with the teachings of Woolley, responsive to transmitting the access command, receiving one or more security files from the security file system and executing the security procedure in response to receiving the one or more security files and concurrently with executing a power up initialization of the memory device, to ensure that access is only given to known and trusted entities.
The combination of Hamlin and Wooley does not explicitly teach wherein data for the host system is stored at a second physical location of the memory device, and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system. Ansari teaches wherein data for the host system is stored at a second physical location of the memory device ([0040], private key and traffic data from a source, i.e. government authority see [0037], stored in its own separate memory), and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system ([0037], private key has its own separate secure memory and is separate from the memory storing the traffic data from the source see [0040]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin and Wooley with the teachings of Ansari, wherein data for the host system is stored at a second physical location of the memory device, and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system, to provide the additional benefits of hardware component security for the security-related files and the host data.
The combination of Hamlin, Wooley and Ansari does not explicitly teach the security files including controller identification data and mapping data. Bryant-Rich teaches the security files including controller identification data and mapping data ([0024], responsive to a memory command, a controller receives identification data and mapping data).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley and Ansari with the teachings of Bryant-Rich, the security files including controller identification data and mapping data, to provide the additional benefits of hardware component security for the security-related files and the host data.
The combination of Hamlin, Wooley, Ansari and Bryant-Rich does not explicitly teach wherein the security file system is made accessible independent of a media ready status for the host system data (Examiner Note: media ready status refers to inaccessible L2P table during pre-boot/boot stage after power event see specification at [0011]) therefore (Wooley; Abstract, teaches security processor and files made available during pre-boot/boot), while the host system data is inaccessible during
A power up initialization of the memory device. Doshi teaches a media ready status for the host system data ([0042], indications are sent to signal an updated table or a complete transaction); and the host system data is inaccessible during a power up initialization of the memory device ([0044], L2P table is inaccessible during booting after power event).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley, Ansari and Bryant-Rich with the teachings of Doshi, wherein the security file system is made accessible independent of a media ready status for the host system data, while the host system data is inaccessible during a power up initialization of the memory device, to provide the additional benefits of hardware component security for the security-related files and the host data during boot and pre-boot stages.
The combination of Hamlin, Wooley, Ansari, Bryant-Rich and Doshi does not explicitly teach transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device. Kotary teaches transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device ([0026] and [0029], a memory map attestation is performed by the secure map logic during BIOS initialization, see [0023] – the results of the attestation are returned to the host so that it may either access the memory or will be denied access see [0029]-[0030]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley, Ansari, Bryant-Rich and Doshi with the teachings of Kotary, transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device, to provide the additional benefits of hardware component security for the security-related files and the host data during boot and pre-boot stages.
As per claim 2, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 1, wherein the processing device is to receive the identification command from the host system after a reset of the memory device (Woolley; [0033], power-on-reset triggers various validations for various components) see also (Hamlin; [0016], identification of various associated data and applications involved in a pointer access request) (Claim interpretation – the BRI of “identification command” can include many types of commands that require an identification of data, entity or component).
As per claim 3, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 1, wherein the processing device is to perform operations further comprising: responsive to receiving the identification command, initiate the power up initialization procedure (Hamlin; [0032], power up, restart or initialize device based on PBA pointer request), wherein transmitting the access command is at least partially concurrent with executing the power up initialization ([0033], steps are included a three phase secure boot sequence, i.e. power up see Abstract and [0002]).
As per claim 8, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 9, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
As per claim 10, the substance of the claimed invention is identical or substantially similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
As per claim 15, Hamlin teaches a system comprising: a memory device ([0014], mass storage device); and a processing device ([0014], processor), operatively coupled with the memory device ([0014] and Fig. 2, processor coupled to memory via bus), to perform operations comprising: performing a power up initialization of the memory device; receiving an access command with a file identification ([0032], request a PBA object pointer to access a PBA object, i.e. file); determining the access command is associated with a physical super management unit (PSMU) at a first location of the memory device storing a security file system based on the file identification ([0015]-[0016], access request made to secure subsystem at a first location with an object directory which is interpreted act as a physical super “management unit”).
Hamlin does not explicitly teach transmitting security files stored at the PSMU in response to determining the access command is associated with the security files, wherein transmitting the security files is concurrent with executing the power up initialization of the memory device and part of the execution of a security procedure. Woolley teaches transmitting security files stored at the PSMU in response to determining the access command is associated with the security files ([0034], validating the pointer which is a part of the access instruction to the CSF file), wherein transmitting the security files is concurrent with executing the power up initialization of the memory device ([0033], steps are included a three phase secure boot sequence, i.e. power up see Abstract and [0002]) and part of the execution of a security procedure ([0034], executing a series of security checks and rules after receiving command sequence file).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin with the teachings of Woolley, security files stored at the PSMU in response to determining the access command is associated with the security files, wherein transmitting the security files is concurrent with executing the power up initialization of the memory device and part of the execution of a security procedure, to ensure that access is only given to known and trusted entities.
The combination of Hamlin and Wooley does not explicitly teach wherein data for the host system is stored at a second physical location of the memory device, and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system. Ansari teaches wherein data for the host system is stored at a second physical location of the memory device ([0040], private key and traffic data from a source, i.e. government authority see [0037], stored in its own separate memory), and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system ([0037], private key has its own separate secure memory and is separate from the memory storing the traffic data from the source see [0040]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin and Wooley with the teachings of Ansari, wherein data for the host system is stored at a second physical location of the memory device, and wherein the first physical location is reserved for security-related files and is separate from the second physical location storing the data for the host system, to provide the additional benefits of hardware component security for the security-related files and the host data.
The combination of Hamlin, Wooley and Ansari does not explicitly teach the security files including controller identification data and mapping data. Bryant-Rich teaches the security files including controller identification data and mapping data ([0024], responsive to a memory command, a controller receives identification data and mapping data).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley and Ansari with the teachings of Bryant-Rich, the security files including controller identification data and mapping data, to provide the additional benefits of hardware component security for the security-related files and the host data.
The combination of Hamlin, Wooley, Ansari and Bryant-Rich does not explicitly teach wherein the security file system is made accessible independent of a media ready status for the host system data (Examiner Note: media ready status refers to inaccessible L2P table during pre-boot/boot stage after power event see specification at [0011]) therefore (Wooley; Abstract, teaches security processor and files made available during pre-boot/boot), while the host system data is inaccessible during
A power up initialization of the memory device. Doshi teaches a media ready status for the host system data ([0042], indications are sent to signal an updated table or a complete transaction); and the host system data is inaccessible during a power up initialization of the memory device ([0044], L2P table is inaccessible during booting after power event).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley, Ansari and Bryant-Rich with the teachings of Doshi, wherein the security file system is made accessible independent of a media ready status for the host system data, while the host system data is inaccessible during a power up initialization of the memory device, to provide the additional benefits of hardware component security for the security-related files and the host data during boot and pre-boot stages.
The combination of Hamlin, Wooley, Ansari, Bryant-Rich and Doshi does not explicitly teach transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device. Kotary teaches transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device ([0026] and [0029], a memory map attestation is performed by the secure map logic during BIOS initialization, see [0023] – the results of the attestation are returned to the host so that it may either access the memory or will be denied access see [0029]-[0030]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Wooley, Ansari, Bryant-Rich and Doshi with the teachings of Kotary, transmitting, to the host system, a response indicating completion of the identification command, wherein the response is transmitted concurrently with executing the power up initialization of the memory device, to provide the additional benefits of hardware component security for the security-related files and the host data during boot and pre-boot stages.
Claims 5, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary in further view of Shaharabany et al. (US PGPUB No. 2020/0104067) [hereinafter “Shaharabany”].
As per claim 5, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 1, operations performed at least partially concurrent with executing the security procedure ([0034], executing a series of security checks and rules after receiving command sequence file).
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary does not explicitly teach wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table at least partially concurrent with executing the security procedure. Shaharabany teaches wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table ([0024], updating a logical to physical translation table during boot see Abstract) (Examiner Note: Shaharabany also teaches updating the translation table during boot operations).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary with the teachings of Shaharabany, wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table at least partially concurrent with executing the security procedure, to ensure that the memory access request is properly routed and serviced.
As per claim 12, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 20, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 1, operations performed at least partially concurrent with transmitting the security files (Woolley; [0034], security phase done concurrently with the transmission of the CSF file).
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary does not explicitly teach wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table at least partially concurrent with executing the security procedure. Shaharabany teaches wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table ([0024], updating a logical to physical translation table during boot see Abstract) (Examiner Note: Shaharabany also teaches updating the translation table during boot operations).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary with the teachings of Shaharabany, wherein the processing device is to operations further comprising: executing a rebuilding of a logical-to-physical (L2P) table at least partially concurrent with executing the security procedure, to ensure that the memory access request is properly routed and serviced.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Shaharabany in further view of Okano et al. (US PGPUB No. 2011/0185164) [hereinafter “Okano”].
As per claim 6, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Shaharabany teaches system of claim 5.
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Shaharabany does not explicitly teach receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data. Okano teaches receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data ([0032], booth completion notification function notifying a user of boot completion which would include the receiving of the security files during boot operations as taught by Woolley see claim 1).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Shaharabany with the teachings of Okano, receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data, to ensure that the memory access request is properly serviced at the correct time.
As per claim 13, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary in further view of Krygowski et al. (US Patent No. 5,632,013) [hereinafter “Krygowski”].
As per claim 7, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 1.
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary does not explicitly teach wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device. Krygowski teaches wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device (Col. 4, lines 9-15, there is a second backup copy of the initialization data stored at the second memory controller).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary with the teachings of Krygowski, wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device, to ensure that redundancy measures are in place to protect data integrity.
As per claim 14, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary in further view of Hoehler et al. (US PGPUB No. 2018/0095678) [hereinafter “Hoehler”].
As per claim 16, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 15.
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary does not explicitly teach refraining from performing a wear leveling operation on the PSMU storing the security file system. Hoehler teaches refraining from performing a wear leveling operation on the PSMU storing the security file system ([0015], to select the inclusion of logical portions of memory with physical portions used in wear leveling).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary with the teachings of Hoehler, refraining from performing a wear leveling operation on the PSMU storing the security file system, to allow a user to explicitly exclude other logical memory portions from use thru wear leveling.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler in further view of Okano.
As per claim 17, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler teaches the system of claim 16 as well as transmitting the security files stored at the PSMU (Woolley; [0034], using pointer to access command sequence file).
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler does not explicitly teach receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data. Okano teaches receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data ([0032], booth completion notification function notifying a user of boot completion which would include the receiving of the security files during boot operations as taught by Woolley see claim 1).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler with the teachings of Okano, receiving, after receiving the security files from the security file system, a ready notification associated with the second location of the memory device storing host data, to ensure that the memory access request is properly serviced at the correct time.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary in further view of Krygowski.
As per claim 18, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary teaches the system of claim 15.
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary does not explicitly teach wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device. Krygowski teaches wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device (Col. 4, lines 9-15, there is a second backup copy of the initialization data stored at the second memory controller).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi and Kotary with the teachings of Krygowski, wherein a copy of the security file system is stored at a second physical super management unit (PSMU) at the first location of the memory device, to ensure that redundancy measures are in place to protect data integrity.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler in further view of Krygowski.
As per claim 19, the combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler teaches the of claim 16.
The combination of Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler does not explicitly teach performing an error correction operation on the security file system stored at the PSMU of the first location of the memory device; responsive to performing the error correction operation, determining one or more errors associated with the security file system; and copying the security file system stored at a second PSMU at the first location of the memory device to a third PSMU at the first location of the memory device in response to determining the one or more errors. Krygowski teaches performing an error correction operation on the security file system stored at the PSMU of the first location of the memory device (Col. 4, lines 28-36, error correction is performed at a first memory location using a Hamming code for error detection); responsive to performing the error correction operation, determining one or more errors associated with the security file system (Col. 4, lines 28-36, error correction inherently includes determine errors); and copying the security file system stored at a second PSMU at the first location of the memory device to a third PSMU at the first location of the memory device in response to determining the one or more errors (Col. 4, lines 39-45, copying the data from a “good side” memory to overwrite a memory with detected errors).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Hamlin, Woolley, Ansari, Bryant-Rich, Doshi, Kotary and Hoehler with the teachings of Krygowski, performing an error correction operation on the security file system stored at the PSMU of the first location of the memory device; responsive to performing the error correction operation, determining one or more errors associated with the security file system; and copying the security file system stored at a second PSMU at the first location of the memory device to a third PSMU at the first location of the memory device in response to determining the one or more errors, to perform requisite steps of data integrity checks to improve efficiency and correctness.
Response to Arguments
Applicant’s arguments with respect to rejection of claims 1-20 under 35 U.S.C. 103 have been considered but are moot in light of the new prior art reference, Kotary.
Examiner is open to an after-final interview to discuss amendments to overcome the prior arts of record and other relevant prior arts to place the application in condition for allowance. Specifically,
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Edwards et al. (US PPGUB No. 2009/0138754), Chang (US PGPUB No. 2004/0111633), Thorsen (US Patent No. 10,922,415), Wang et al. ("A Survey of Secure Boot Schemes for Embedded Devices," 2022 24th International Conference on Advanced Communication Technology (ICACT), PyeongChang Kwangwoon_Do, Korea, Republic of, 2022, pp. 224-227, doi: 10.23919/ICACT53585.2022.9728840) and Streit et al. ("Secure Boot from Non-Volatile Memory for Programmable SoC Architectures," 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, USA, 2020, pp. 102-110, doi: 10.1109/HOST45689.2020.9300126) all disclose various aspects of the claimed invention including the accessing of security files during boot operations.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
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/PETER C SHAW/Primary Examiner, Art Unit 2493 April 19, 2026
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