CTNF 17/468,278 CTNF 83727 DETAILED ACTION This office action addresses Applicant’s response filed on 4 February 2026. Claims 1-24 are pending. 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 9-11, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Antwerpen (US 9,230,047) in view of Eccles (US 7,143,376), Nelson (US 2008/0288234), Yang (US 2009/0150136), Bellantoni (US 2005/0229170), Williams (US 6,631,508), Vedantam (US 2012/02110537), and Surprise (US 10,902,175) . Regarding claim 1 , Van Antwerpen discloses a method of data processing in a data processing system including a processor and data storage (Fig. 9), the method comprising: the processor of the data processing system constructing, within the data storage, a hierarchical integrated circuit design for an integrated circuit containing millions of transistors through execution of one or more electronic design automation (EDA) tools, wherein the hierarchical integrated circuit design includes a design hierarchy including a plurality of entity instances organized hierarchically in a plurality of levels including a lower level and a higher level (col. 1, lines 16-27; col. 3, lines 35-41; col. 6, lines 45-50), and wherein the constructing includes: the processor of the data processing system receiving a first plurality of hardware description language (HDL) files defining a first scope of design forming only a smaller subset of the hierarchical integrated circuit design (Fig. 8A, bottom-level netlist); the processor incorporating, in the first scope of design, technology-specific structures specific to a physical implementation of said first scope of design (col. 3, lines 42-49); based on the first plurality of HDL files and the technology-specific structures incorporated into the first scope of design, the processor generating a second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures (col. 3, lines 42-61); the processor forming a third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design (Fig. 8A, top-level netlist); and the processor processing the third plurality of HDL files to form a representation of the second scope of design, wherein the processing includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with a design entity (col. 4, lines 24-26). Van Antwerpen does not appear to explicitly disclose the design hierarchy including one or more intermediate levels. However, persons having ordinary skill in the art would understand that hierarchical designs such as those disclosed in Van Antwerpen would include intermediate levels. Eccles discloses design hierarchies including one or more intermediate levels (Fig. 6). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen and Eccles, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using hierarchical designs having top, intermediate, and bottom levels. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses hierarchical designs having at least top and bottom levels. Eccles discloses that hierarchical designs also have intermediate levels. The teachings of Eccles are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen’s hierarchical designs would similarly include intermediate levels in addition to top and bottom levels. Van Antwerpen does not appear to explicitly disclose pluralities of HDL files. However, persons having ordinary skill in the art would understand that design entities can be described in one or more HDL files, as taught by Nelson (¶¶65, 77). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen and Nelson, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of designing a circuit using multiple HDL files to define circuit entities. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses performing design operations on a hierarchical circuit design, in which different entities in the circuit are defined in HDL files. Nelson teaches that entities can be defined in one or more HDL files. The teachings of Nelson are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen would similarly define design entities in one or more HDL files. If Van Antwerpen is found to be unclear regarding HDL, Van Antwerpen discloses netlists (Fig. 8A), which persons having ordinary skill in the art would recognize are written in HDL. Eccles further provides evidence that netlists are written in HDL (col. 3, lines 40-42). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, and Nelson, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of performing circuit design processes using HDL netlists. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses netlists, which are conventionally written in HDL; Eccles discloses HDL netlists. The teachings of Eccles are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen’s design process would use typical HDL netlists. Van Antwerpen does not appear to explicitly disclose placing the first design entity within a third design entity that is a wrapper entity that instantiates the first design entity, wherein the wrapper entity includes shim logic configured to generate a suitable signal to interface at least one technology-specific structure in the first design entity and functional-intent logic external to the third design entity in the second scope of design, that the second design entity is replaced with the third design entity, and that the at least partially technology-elaborated simulation model includes the wrapper entity. Yang discloses placing the first design entity within a third design entity that is a wrapper entity that instantiates the first design entity that the second design entity is replaced with the third design entity, and that the at least partially technology-elaborated simulation model includes the wrapper entity (¶4, particularly progressive refinement design objects at one level of abstraction to a lower level of abstraction; ¶5, abstraction wrapper around lower-level objects to make them the same level of abstraction as higher-level model). Persons reading Yang would recognize that Yang’s abstraction wrapper would include shim logic configured to generate a suitable signal to interface at least one technology-specific structure in the first design entity and functional-intent logic external to the third design entity in the second scope of design, since the abstraction wrapper is used for a design object at a different level of abstraction from the surrounding design so that the design object is seen as the same level of abstraction as the surrounding design. Nevertheless, Bellantoni explicitly discloses that the wrapper entity includes shim logic configured to generate a suitable signal to interface at least one technology-specific structure in the first design entity and functional-intent logic external to the third design entity in the second scope of design (¶36). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, and Bellantoni, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of allowing higher-level simulation of lower-level design objects. KSR Int’l Co. v. Teleflex Inc ., 82 U.S.P.Q.2d 1385, 1396. Van Antwerpen discloses a method including replacing higher-level design entities with technology-specific design entities at a lower level of abstraction. Yang teaches progressive replacement where higher-level designs can include lower-level design objects by encapsulating the design objects in an abstraction wrapper that presents the lower-level object at the higher level of abstraction of the design. Bellantoni teaches that a wrapper encapsulating a lower-level object in a higher-level design includes additional interface logic to allow correct communication between the lower-level object and higher-level design in simulation. The teachings of Yang and Bellantoni are directly applicable to Van Antwerpen, so that Van Antwerpen would similarly use interface/abstraction wrappers to correctly interface technology-mapped elements to a higher-level design. Van Antwerpen does not appear to explicitly disclose the processor compiling the second scope of design to obtain an at least partially technology-elaborated simulation model and simulating, utilizing functional-only simulation, the second scope of design utilizing the at least partially technology-elaborated simulation model, wherein the functional-only simulation excludes technology-specific structures and focuses solely on verifying the logical correctness and functional intent of the second scope of design. Yang (¶¶2, 4-5) and Bellantoni (¶¶36-37) are both directed to functional (e.g. transaction- or RTL-level) simulations of high-level models that include lower-level objects, such as the technology-mapped objects of Van Antwerpen; both disclose the processor compiling the second scope of design to obtain an at least partially technology-elaborated simulation model and simulating, utilizing functional-only simulation, the second scope of design utilizing the at least partially technology-elaborated simulation model. Persons having ordinary skill in the art, reading Yang and Bellantoni, would recognize that the transaction-level or RTL-level simulations are functional-only simulations that exclude technology-specific structures and focus solely on verifying the logical correctness and functional intent of the second scope of design. Nevertheless, Williams explicitly discloses functional-only simulation that excludes technology-specific structures and focuses solely on verifying the logical correctness and functional intent of the second scope of design (col. 1, line 66 to col. 2, line 27; col. 4, lines 13-31). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, and Williams, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of quickly verifying designs including technology-specific components function correctly. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses generating a design having technology-specific entities. Yang and Bellantoni disclose functional simulations of high-level models including lower-level objects such as technology-specific entities. Williams teaches that the functional simulations exclude technology-specific structures and verifying logical and functional correctness of the designs. The teachings of Yang, Bellantoni, and Williams are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen would similarly compile the design having technology-specific entities into a high-level model and verify the design by functional simulation, in order to quickly determine that the design is functionally and logically correct. Van Antwerpen does not appear to explicitly disclose pre-routing one or more signals within the hierarchical integrated circuit design by establishing anchor points for the signals, routing the signals according to pre-routing directives, and overriding default signal routing for at least one signal based on the pre-routing such that the signal is routed through a path specified by the pre- routing directives instead of a default path. Vedantam discloses pre-routing one or more signals within the hierarchical integrated circuit design by establishing anchor points for the signals (¶¶40, 41, 46, 64), routing the signals according to pre-routing directives (Fig. 4, step 410; ¶44), and overriding default signal routing for at least one signal based on the pre-routing such that the signal is routed through a path specified by the pre- routing directives instead of a default path (¶¶20, 64, 70). If Vedantam is found to be unclear regarding discloses pre-routing one or more signals within the hierarchical integrated circuit design by establishing anchor points for the signals, Surprise also discloses the same (Figs. 2A, 2F). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, Williams, Vedantam, and Surprise, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of improving timing and congestion of selected routes. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses a hierarchical design. Vedantam and Surprise teach that selected signals in the design should be pre-routed using anchor points to improve timing and congestion of those signal routes. The teachings of Vedantam and Surprise are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen would similarly pre- route signals in the hierarchical design using anchor points to improve timing and congestion of those signal routes. Regarding claim 2 , Van Antwerpen discloses generating a fourth plurality of hardware description language (HDL) files defining a fourth design entity that is at the second scope of design (col. 3, lines 42-49). Regarding claim 3 , Van Antwerpen discloses performing logic synthesis on the fourth plurality of hardware description language HDL files to generate a gate list representation of the second scope of design (col. 12, lines 15-25). Claims 9-11 are directed to program products for performing the methods of claims 1-3, and are rejected under the same reasoning. Van Antwerpen further discloses program products for performing the claimed methods (Fig. 9). Claims 17-19 are directed to a system comprising processor and stored code for performing the methods of claims 1-3, and are rejected under the same reasoning. Van Antwerpen further discloses a computer system for performing the claimed methods (Fig. 9) . 07-21-aia AIA Claim (s) 4-7, 12-15, and 20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Antwerpen , Eccles , Nelson , Yang, Bellantoni , Williams , Vedantam , Surprise , and Meiyappan (US 7,100,133) . Regarding claims 4, 12, and 20 , Van Antwerpen discloses that the second scope of design includes an entire integrated circuit chip (col. 3, lines 32- 41; top -level). If Van Antwerpen is found to be unclear regarding this limitation, Meiyappan also discloses that the second scope of design includes an entire integrated circuit chip (col. 16, lines 25-40). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, Williams, Vedantam, Surprise, and Meiyappan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of designing a chip. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses a circuit design process that includes a top-level netlist, which persons having ordinary skill in the art would understand defines the chip. Meiyappan discloses a top-level netlist defining the chip and block-level netlists defining blocks of the chip. The teachings of Meiyappan are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen’s top-level netlist would be used to define the chip for hierarchical design. Regarding claims 5, 13, and 21 , Van Antwerpen does not appear to explicitly disclose that the first scope of design is a processor core of the integrated circuit chip. Meiyappan discloses these limitations (col. 11, lines 14-31; col. 16, lines 25-35). Motivation to combine remains consistent with claim 4. Regarding claims 6, 14, and 22 , Van Antwerpen discloses the processing includes processing an instance hierarchy of the hierarchical integrated circuit design in a bottom-up manner (col. 4, lines 20-26). If Van Antwerpen is found to be unclear regarding this limitation, Meiyappan also discloses the same (col. 16, lines 62-63). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, Williams, Vedantam, Surprise, and Meiyappan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of synthesizing a hierarchical design for simulation. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses synthesizing a hierarchical design. Meiyappan teaches that hierarchical designs are synthesized for simulation in a bottom-up manner. The teachings of Meiyappan are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen would similarly synthesize the hierarchical design in a bottom-up manner for simulation. Regarding claims 7, 15, and 23 , Van Antwerpen discloses updating the fourth plurality of hardware description language (HDL) files with logic synthesis information and compiling the fourth plurality of HDL files as updated (col. 4, lines 10-34 and lines 63-64), but does not appear to explicitly disclose obtaining a technology-elaborated simulation model. Meiyappan discloses compiling HDL files to obtain a technology-elaborated simulation model (col. 16, lines 25-45; col. 19, lines 51-65). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, Williams, Vedantam, Surprise, and Meiyappan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of verifying correct operation of a circuit design. KSR Int’l Co. v. Teleflex Inc. , 82 U.S.P.Q.2d 1385, 1395. Van Antwerpen discloses a hierarchical circuit design process that generate a complete design. Meiyappan discloses generating simulation models from the design of a hierarchical circuit, and simulating the design to verify correct operation. The teachings of Meiyappan are directly applicable to Van Antwerpen in the same way, to achieve the same result of verifying correct operation of Van Antwerpen’s design . 07-21-aia AIA Claim (s) 8, 16, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Antwerpen , Eccles , Nelson , Yang, Bellantoni , Williams , Vedantam , Surprise , and Knol (US 7,117,473) . Regarding claims 8, 16, and 24 , Van Antwerpen discloses that the processing includes removing from the representation of the second scope of a design a signal associated with the second design entity (Figs. 8A and 8B; col. 9, lines 10-23). If Van Antwerpen is found to be unclear regarding these limitations, Knol discloses the same (col. 7, lines 49-54). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Van Antwerpen, Eccles, Nelson, Yang, Bellantoni, Williams, Vedantam, Surprise, and Knol, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of removing unnecessary connections from a design. KSR Int’l Co. v. Teleflex Inc ., 82 U.S.P.Q.2d 1385, 1396. Van Antwerpen discloses a hierarchical design in which a higher-level block is modified by replacing a lower-level block. Persons having ordinary skill in the art would recognize that signals associated with the replaced block that are no longer needed should be removed from the higher-level block, as taught by Knol. The teachings of Knol are directly applicable to Van Antwerpen in the same way, so that Van Antwerpen would similarly remove signals associated with the second entity that are no longer needed from the second scope of design, such that signals that are no longer needed are not left in the design. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 29 May 2026 /ARIC LIN/ Examiner, Art Unit 2851 Application/Control Number: 17/468,278 Page 2 Art Unit: 2851 Application/Control Number: 17/468,278 Page 3 Art Unit: 2851 Application/Control Number: 17/468,278 Page 4 Art Unit: 2851 Application/Control Number: 17/468,278 Page 5 Art Unit: 2851 Application/Control Number: 17/468,278 Page 6 Art Unit: 2851 Application/Control Number: 17/468,278 Page 7 Art Unit: 2851 Application/Control Number: 17/468,278 Page 8 Art Unit: 2851 Application/Control Number: 17/468,278 Page 9 Art Unit: 2851 Application/Control Number: 17/468,278 Page 10 Art Unit: 2851 Application/Control Number: 17/468,278 Page 11 Art Unit: 2851 Application/Control Number: 17/468,278 Page 12 Art Unit: 2851 Application/Control Number: 17/468,278 Page 13 Art Unit: 2851 Application/Control Number: 17/468,278 Page 14 Art Unit: 2851 Application/Control Number: 17/468,278 Page 15 Art Unit: 2851 Application/Control Number: 17/468,278 Page 16 Art Unit: 2851
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