DETAILED ACTION
This office action addresses Applicant’s response filed on 22 April 2026. Claims 1, 3-5, 7, 8, 10-12, 14, 15, 17-19, 21-24, 26, 28, and 30 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 8, 10-12, 15, 17-19, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amundson (US 2012/0017186) in view of Verma (US 2022/0180033), Jiang (CN 112083897), Inata (WO 2015/075805), Han (CN 110209387), Chen (US 2011/0145779), Sun (US 2011/0107281), Sundararajan (US 8,650,517), and MacDonald (US 8,701,084).
Regarding claim 1, Amundson discloses a method of electronic design automation (EDA) processing in a data processing system including a processor (Fig. 19; ¶8), the method comprising:
a processor receiving, as input, a hardware description language (HDL) file defining a first entity forming a part of a modular circuit design for an integrated circuit and an expression of design refinement intent with regard to the first entity (Fig. 5, master VHDL 305 with intent region 306), wherein:
the expression of design refinement intent is provided within alternative region comments embedded as HDL comments within the HDL file and identifies an intent region within an implementation of the first entity and specifies replacement logic for the intent region (Fig. 5, intent region 306 replaced by implementations in custom decompositions 310 and 505);
the expression of design refinement intent references a particular signal not referenced in a definition of the first entity in the HDL file (Fig. 5, signal y_int);
the intent region has a beginning marked by a begin comment in the HDL file and has an end marked by a separate end comment in the HDL file (Fig. 5, intent region 306 delineated by begin and end comments);
within the alternative region comments, a plurality of alternative implementations for the intent region coexist, each corresponding to a different intent implementation (Figs. 4 and 5; 306, 310, and 505 are alternative implementations of the logic function in the intent region of master VHDL 305);
the HDL file further includes, within the alternative region comments, a use statement that specifies selection of one of the alternative implementations for application by the processor (Fig. 5, 401 specifies ‘swap and0’, corresponding to 403; similarly, work.ex_and in 310 corresponds to architecture ex_and in 505);
the processor processing the plurality of entities, wherein the processing includes: based on the expression of design refinement intent in the HDL file, the processor automatically generating a modified HDL file by replacing logic within the intent region marked by the begin and end comments with the replacement logic specified in the alternative region comments within the HDL file (Fig. 5, intent region 306 replaced by implementation specified in custom decomposition 310; ¶35);
the processor, prior to logic synthesis, excising from the modified HDL file all alternative implementations for the intent region other than the one specified by the use statement, such that only the selected implementation remains in the HDL file for synthesis (Fig. 5; ¶35, ‘replacement’ indicates that the implementation that is replaced does not remain);
the processor automatically updating, in the modified HDL file, a signal declaration section for the first entity based on replacement of the logic within the intent region by the replacement logic (Fig. 5, 505 signal declaration in architecture definition); and
thereafter, performing logic synthesis on the modified HDL file having the signal declaration section updated to generate a gate list representation of the modular circuit design (Fig. 2, steps 215-265).
If Amundson is found to be unclear regarding design refinement intent within alternative region comments embedded within the HDL file, Verma also discloses these limitations (¶¶26, 41). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson and Verma, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of expressing potential design modifications as comments in an HDL file. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson discloses a process for specifying design modifications in HDL. Verma teaches that design modifications to HDL files are written as comments in the HDL file. The teachings of Verma are directly applicable to Amundson in the same way, so that Amundson’s design modifications to HDL files would similarly be included as comments.
If Amundson is found to be unclear regarding the processor automatically updating, in the modified HDL file, a signal declaration section for the first entity based on replacement of the logic within the intent region by the replacement logic, Jiang also discloses these limitations (¶¶10, 27). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, and Jiang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of automatically generating correct signal declarations from design modules. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson discloses modification of entities can include signals not referenced in a definition of the entity. Jiang teaches that signal declarations for HDL entities can be automatically generated by analyzing the signals of the HDL entities. The teachings of Jiang are directly applicable to Amundson in the same way, so that Amundson’s modified HDL entities would similarly be analyzed to automatically generate the correct signal declarations for the signals of the modified HDL entities.
If Amundson is found to be unclear regarding the processor, prior to logic synthesis, excising from the modified HDL file all alternative implementations for the intent region other than the one specified by the use statement, such that only the selected implementation remains in the HDL file for synthesis, Inata (Fig. 5; ¶29 in published WIPO, p. 4, lines 151-158 in translated copy) and Han (p. 9, step 1023, pre-processing HDL to delete annotations and irrelevant code) disclose these limitations. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, and Han, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of preprocessing HDL files to place them in better form for subsequent steps in a design flow. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson modifying HDL to replace one implementation with a selected implementation, performing further circuit design process steps such as synthesizing the HDL into a netlist, performing placement and routing, etc. Verma teaches that the HDL modifications are specified in comments in the HDL file. Inata and Han teach that HDL should be preprocessed, including removing comments, annotations, irrelevant code, etc. The teachings of Inata and Han are directly applicable to Amundson and Verma in the same way, so that Amundson’s HDL would similarly be preprocessed prior to performing subsequent process steps such as synthesis, to place the HDL in better form for those subsequent steps.
Amundson does not appear to explicitly disclose that the modular circuit design comprises a hierarchical circuit design including a plurality of hierarchically arranged entities of differing design scopes, said plurality of hierarchically arranged entities including the first entity and a second entity that instantiates the first entity; the processor processing the plurality of hierarchically arranged entities in a top-down manner in which the processor processes the second entity to implement any design refinement intent and thereafter processes the first entity to implement any design refinement intent such that the processing accounts for any entity added or deleted by the design refinement intent. Chen teaches that the modular circuit design comprises a hierarchical circuit design including a plurality of hierarchically arranged entities of differing design scopes, said plurality of hierarchically arranged entities including the first entity and a second entity that instantiates the first entity (Fig. 2), and entities added or deleted by the design refinement intent (claims 4 and 7). Sun teaches the processor processing the plurality of hierarchically arranged entities in a top-down manner in which the processor processes the second entity to implement any design refinement intent and thereafter processes the first entity to implement any design refinement intent such that the processing accounts for any entity added or deleted by the design refinement intent (¶70).
Specifically, as noted above, Amundson teaches the processor processing the plurality of arranged entities in which the processor processes an entity to implement any design refinement intent (Fig. 5; ¶35). Chen teaches that the arranged entities are hierarchically arranged and include a second entity that instantiates a first entity (Fig. 2), and that the design refinement intent includes adding or deleting entities (claims 4 and 7). Sun teaches that the processing is performed in a top-down manner in which the processor processes the second entity to implement any design refinement intent and thereafter processes the first entity to implement any design refinement intent such that the processing accounts for any change to the design (¶70), which would include changes such as the addition/deletion of entities taught by Chen. Furthermore, top-down processing necessarily accounts for entities that are added or deleted by definition; for example, if a child entity is deleted from the parent entity (for example, as taught by Chen), top-down processing could not then process the deleted child entity, since it doesn’t exist.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, and Sun, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of processing modifications to modular entities to add or remove functionality to meet designers’ goals, in known top-down hierarchical fashion to avoid unnecessary work or re-work. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Amundson discloses processing entities to implement design refinement intent. Chen teaches that the entities are arranged hierarchically, and design refinement intent includes adding/deleting entities. Sun teaches that processing of hierarchically-arranged entities should be done in a top-down fashion based on changes to entities and their child entities. The teachings of Chen and Sun are directly applicable to Amundson in the same way, so that Amundson would similarly add/delete entities through the design refinement intent to add/remove functionality to a design as desired by the designer, and would process the entities in a hierarchical top-down manner to avoid unnecessary processing.
Amundson does not appear to explicitly disclose that the HDL comments are ignored by an HDL compiler that compiles the HDL file; however, this is a known quality of HDL comments, as taught by Sundararajan (col. 6, lines 21-23). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, and Sundararajan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of processing HDL conventionally. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson teaches HDL comments, which persons having ordinary skill in the art would recognize are ignored by HDL compilers, as taught by Sundararajan. The teachings of Sundararajan are directly applicable to Amundson, so that Amundson’s HDL would be processed in the known manner by conventional compilers.
Amundson does not appear to explicitly disclose determining rule compliance of the intent region and the different intent implementations in the HDL file by performing a sequence of tests, the sequence of tests comprising: determining that the intent region and that the different intent implementations do not partially or fully overlap; determining that the intent region and the different intent implementations do not split any HDL logic statement; and determining that the intent region and the different intent implementations do not split any entity instantiation. However, these limitations are merely code error/syntax checking, as taught by MacDonald (col. 4, lines 27-32). Persons having ordinary skill in the art would immediately recognize that overlaps, split logic statements, and split entity instantiations are code errors that would cause code to fail to compile/function, and that it is conventional to check code for such errors; e.g. if a line of code or a function/entity definition were truncated into different sections, that would clearly throw an error.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, and MacDonald, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of verifying that code is error-free. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson discloses HDL code. Persons having ordinary skill in the art would know that code is checked for errors/syntax, such as overlaps, split logic statements, or split entity instantiations to ensure that the code will compile/function, as taught by MacDonald. The teachings of MacDonald are directly applicable to Amundson in the same way, so that Amundson would similarly check HDL code for errors to ensure that the code is error-free.
Regarding claim 3, Amundson discloses the processor implementing later stage refinements (Fig. 2, any of steps 215-255), but does not appear to explicitly disclose after the generating, the processor removing from the modified HDL file the comments providing the expression of design refinement intent and that the later stage refinements are implemented without impact by the expression of design refinement intent. Inata discloses these limitations (Fig. 5; ¶29 in published WIPO, p. 4, lines 151-158 in translated copy). Specifically, Inata discloses preprocessing HDL to remove comments prior to later synthesis/layout steps. Motivation to combine remains consistent with claim 1.
Regarding claim 4, Amundson discloses that the replacement logic comprises an alternative design for the intent region defined in an alternative region declaration that is expressed in HDL comments (Figs. 4 and 5; 306, 310, and 505 are alternative implementations of the logic function in the intent region of master VHDL 305). As discussed above with regard to claim 1, Verma also discloses alternative region HDL comments (¶¶26, 41). Motivation to combine remains consistent with claim 1.
Regarding claim 5, Amundson discloses that the replacement logic restructures an equation specified by the intent region (Fig. 5, replacement logic in 310 and/or 505 restructure equation 306).
Claims 8, 10-12 are directed to a computer program product for performing the methods of claims 1 and 3-5 and are rejected under the same reasoning. Amundson discloses a computer program product for performing the claimed methods (Fig. 19; ¶8).
Claims 15, 17-19 are directed to a computer system for performing the methods of claims 1 and 3-5 and are rejected under the same reasoning. Amundson discloses a computer system for performing the claimed methods (Fig. 19; ¶8).
Regarding claim 24, Amundson discloses that implementing later stage refinements comprises implementing physical design refinements for the integrated circuit (Fig. 2, any of steps 225-255).
Claim(s) 7, 14, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amundson in view of Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, and El-Zein (US 2019/0179974).
Regarding claims 7, 14, and 21, Amundson does not appear to explicitly disclose performing formal verification that the modular circuit design as modified is equivalent to the modular circuit design prior to the modifying; El-Zein discloses these limitations (¶¶3-4).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, and El-Zein, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of formally verifying that an optimized design still functions correctly. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson discloses a process for implementing design optimizations. El-Zein teaches that the optimized design should be formally verified to function equivalently to the pre-optimization design, which is directly applicable to Amundson in the same way, so that Amundson would formally verify that the optimized design still functions correctly.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amundson in view of Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, Takagi (US 2003/0033595), and Liu (US 7,028,280).
Regarding claim 22, Amundson discloses the processor generating the modified HDL file (Figs. 2 and 5, master VHDL modified by decompositions), but does not appear to explicitly disclose that the first entity includes one or more ports specified in the HDL file. However, persons having ordinary skill in the art, reading Amundson, would understand that typical HDL design files would include entities having ports, so that the entities could have inputs and outputs. Nevertheless, Takagi discloses that the entity includes one or more ports specified in the HDL file (Fig. 2, port declaration).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, and Takagi, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of designing HDL modules that can take inputs and produce outputs. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Amundson discloses HDLs designs having modules. Takagi teaches that HDL modules have ports to receive inputs and transmit outputs. The teachings of Takagi are directly applicable to Amundson in the same way, so that Amundson’s HDL design modules would similarly have ports to allow input/output.
Amundson does not appear to explicitly disclose that the method further comprises the processor determining whether the expression of design refinement intent alters any port of the first entity; and that generating the modified HDL file is based on determining that the expression of design refinement intent does not alter any port of the entity. Liu discloses these limitations (col. 1, lines 8-11; col. 2, lines 53-57; col. 8, lines 27-39). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, Takagai, and Liu, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of preventing modifications to a design that would alter ports, so that simulation/verifications results are comparable. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Amundson discloses modifying a design according to design refinement intent. Liu teaches that modifications to the ports of the design would prevent comparison of simulation/verification results, and so modifications should be checked to see if they modify ports. The teachings of Liu are directly applicable to Amundson in the same way, so that Amundson would similarly disallow modifications that modify ports, so that simulation/verification results would remain comparable.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amundson in view of Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, Takagi, and Parimi (US 7,926,012).
Regarding claim 23, Amundson discloses the processor generating the modified HDL file (Figs. 2 and 5, master VHDL modified by decompositions), but does not appear to explicitly disclose that the first entity includes one or more pins specified in the HDL file. However, persons having ordinary skill in the art, reading Amundson, would understand that typical HDL design files would include entities having pins, so that the entities could have inputs and outputs. Nevertheless, Takagi discloses that the entity includes one or more pins specified in the HDL file (Fig. 2, port declaration; ports define pins in HDL). Motivation to combine remains consistent with claim 22.
Amundson does not appear to explicitly disclose that the method further comprises the processor determining whether the expression of design refinement intent references a pin name that does not exist in the replacement logic; and that generating the modified HDL file is based on determining that the expression of design refinement intent does not reference any pin name that does not exist in the replacement logic. Parimi discloses these limitations (col. 9, lines 33-42). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, Takagai, and Parimi, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way of ensuring that design modifications do not reference components that don’t exist. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Amundson discloses HDL files comprising modules and expressions of design refinement intent setting forth modifications to those modules. Persons having ordinary skill in the art would understand that Amundson’s HDL modules would also include pins, as taught by Takagi, which was discussed above. Parimi teaches that modifications should be checked to ensure that they do not reference pins and I/O that don’t exist. The teachings of Parimi are directly applicable to Amundson and Takagi in the same way, so that Amundson’s HDL module modifications would similarly be checked to ensure that the modifications don’t reference pins that don’t exist, so that the resulting design will function properly.
Claim(s) 26, 28, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amundson in view of Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, and Liu.
Regarding claims 26, 28, and 30, Amundson does not appear to explicitly disclose prior to the generating and updating, checking that the expression of design refinement intent does not alter any port on the first entity; and performing the generating and updating based on the checking determining that the expression of design refinement intent does not alter any port on the first entity. Liu discloses these limitations (col. 1, lines 8-11; col. 2, lines 53-57; col. 8, lines 27-39). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Amundson, Verma, Jiang, Inata, Han, Chen, Sun, Sundararajan, MacDonald, and Liu, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of preventing modifications to a design that would alter ports, so that simulation/verifications results are comparable. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Amundson discloses modifying a design according to design refinement intent. Liu teaches that modifications to the ports of the design would prevent comparison of simulation/verification results, and so modifications should be checked to see if they modify ports. The teachings of Liu are directly applicable to Amundson in the same way, so that Amundson would similarly disallow modifications that modify ports, so that simulation/verification results would remain comparable.
Response to Arguments
Applicant's arguments filed 22 April 2026 have been fully considered but they are not persuasive.
Arguments pertaining to newly-added limitations are addressed above using additional prior art, and are not further addressed here.
Applicant asserts that Amundson that uses a side file instead of embedding HDL comments in the HDL file, and that though Verma is also cited, “the rejection does not persuasively identifying … these recited limitations”. Remarks 14. The examiner disagrees. The cited portions of Verma explicitly recite embedded HDL comments in the HDL file, and Applicant has not provided any specific arguments against Verma.
Applicant asserts that “the Office Action does not adequately show that the cited combination teaches or suggests the amended top-down hierarchical processing limitation”, noting that while Chen and Sun are cited for these limitations, “the Office Action does not persuasively explain why one of ordinary skill would have modified the cited references to arrive at these recited limitations.” Remarks 15. The examiner disagrees. The rejection clearly sets forth the reasoning for why these limitations are specifically taught by Chen and Sun, how the claim as a whole is obvious over the proposed combination, and why it persons having ordinary skill in the art would have found it obvious to combine the prior art teachings in the proposed manner. Applicant has provided no specific argument for why the cited teachings or their combination are deficient.
Similarly, Applicant asserts that the prior art fails to teach the recited sequence of the generating, excising, updating, and logic synthesis steps. Remarks 16. The examiner disagrees. Applicant provides no specific argument for why the cited portions of Inata, Han, and Jiang fail to teach the referenced limitations. Furthermore, Applicant’s reliance on ¶99 of the Specification is improper because limitations from the Specification are not read into the claim. Applicant also generically asserts that the prior art fails to teach the limitations of other claims without specifically addressed the cited portions of the prior art, which is similarly unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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16 June 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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