Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Applicant’s election without traverse of claims 1, 4-8, and 22-23 in the reply filed on 23 March 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-8, and 23-24
Claims 1, 4-8, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kinghorn et al. (2016/0291265; “Kinghorn”) in view of Shubin et al. (9,698,564; “Shubin”) further in view of Epitaux et al. (2021/0215897; “Epitaux”) and further in view of Wang et al. (2021/0255489; “Wang).
Regarding claim 1, Kinghorn discloses in figure 23, and related figures and text, for example, Kinghorn – Selected Text, electro-optic system embodiments comprising a chip sub-assembly comprising wherein a die 1150 is situated in a cavity in an interposer 1140, an optical fiber connector 1110/1120/1122 is coupled with the interposer; and the interposer is coupled to the die in a cavity in the interposer. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text.
Kinghorn – Figure 23
PNG
media_image1.png
277
377
media_image1.png
Greyscale
Kinghorn – Selected Text
Abstract. Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.
[0121] An example of the common carrier may be an optical interposer that may serve as a common carrier for multiple semiconductor chips. An interposer is known as an element that provides a high speed electrical interface routing from one electronic device or connection to another. An interposer provides a single plane where multiple devices can connect to each other with short connection lengths for good high speed signal performance. An optical interposer may serve as a common support and/or optical interface for optical devices and may incorporate optical signal routing. A desirable feature of a process of assembling optical devices on an interposer is an ability to perform the optical alignment quickly and accurately. Wafer and die stacking may be performed using a diffusion bonding process that maintains a high accuracy vertical placement required for optical device assembly. This process may however require that the chips are polished flat first, and is generally compatible with the use of flat alignment-stop surfaces defined in the chips as described herein. A different bonding solution may use solder pads that are recessed in a cavity on one of the chips that are bonded together with a vertical stop to provide the required vertical placement accuracy, as described hereinabove by way of example with reference to FIGS. 8-10. Advantageously, the use of bonding pads that are vertically offset from flat alignment-stop surfaces in the chips doesn't require special CMP planarization and is compatible with current high production assembly processes. This bonding process could be used with other bonding geometries as well where the chip surface is not able to be processed with CMP.
[0123] With reference to FIG. 23, there is illustrated a schematic diagram of an example geometry for the alignment of a fiber array 1110 and a gain chip 1150 to a photonic chip assembly 1130. The photonic chip 1130 and the gain chip 1150 may be attached via flip-chip bonding process, for example as described hereinabove. The bonding process for this geometry may be carried out using a diffusion bonding technique or a hard stop bonding technique described hereinabove. An assembly composing the photonic chip 1130 and gain chip 1150 may then be attached to an interposer 1140, again using a diffusion bonding technique or a hard stop bonding technique described hereinabove. Fibers of the optical fiber array 1110 may be placed in grooves in the interposer 1140 that align the fibers with respect to the photonic chip 1130. A glass plate 1120 is placed over the smaller diameter end portion of the fibers 1122 in order to secure them in place, and epoxy may be used to secure the glass plate 1120 to the interposer 1140. Electrical contact between the photonic chip 1150 and the interposer 1140 may facilitate electrical paths to other electronic chips 1160 and 1170 that may be bonded to the interposer 1140.
Further regarding claim 1, Shubin discloses in figure 1, and related figures and text, for example, Shubin – Selected Text, bridge chip embodiments 110 which support optical gain chips 112 and photonic chips 114. Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text.
Shubin – Figure 1
PNG
media_image2.png
403
609
media_image2.png
Greyscale
Shubin – Selected Text
Abstract. A multi-chip module (MCM) includes: an interposer, a photonic chip, an optical gain chip, and a waveguide-fiber connector. The photonic chip, which may be electrically coupled to the interposer, may be implemented using a silicon-on-insulator (SOI) technology, and may include an optical waveguide that conveys an optical signal. Moreover, the optical gain chip, which may be electrically coupled to the interposer, may include a III-V compound semiconductor, and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Furthermore, the waveguide-fiber connector may be mechanically coupled to the interposer, and remateably mechanically coupled to an optical fiber coupler that includes the optical fiber. The waveguide-fiber connector may convey the optical signal between the optical waveguide in the photonic chip and the optical fiber.
Column 2, lines 31-56.
(9) One embodiment of the present disclosure provides a multi-chip module (MCM). This MCM includes: an interposer having a top surface, a photonic chip, an optical gain chip, and a waveguide-fiber connector. The photonic chip includes: a substrate; a buried-oxide (BOX) layer disposed on the substrate; and a semiconductor layer disposed on the buried-oxide layer, where an optical waveguide is defined in the BOX layer and the semiconductor layer. Moreover, traces, disposed on the semiconductor layer, face and are electrically coupled to the top surface of the interposer. Furthermore, the optical gain chip includes a second optical waveguide defined in the second substrate, where a location of the second optical waveguide is vertically aligned with a location of the optical waveguide relative to the top surface of the interposer, and the second substrate faces and is electrically coupled to the top surface of the interposer. Additionally, the waveguide-fiber connector is mechanically coupled to the top surface of the interposer. The waveguide-fiber connector has a first end configured to remateably mechanically couple to an optical fiber coupler and a second end, where the waveguide-fiber connector includes a third optical waveguide that optically couples the first end and the second end and, at the second end, a location of the third optical waveguide is vertically aligned with a location of the optical waveguide relative to the top surface of the interposer.
Column 5, line 23 – column 8, line 3.
(14) The disclosed embodiments of the MCM may be assembled using high-precision flip-chip bonding equipment by: passively aligning and securing the chips based on their alignment features on applicable interfaces or surfaces; and/or actively aligning chips to each other. For example, the chips may be aligned while the secured and electrically connected light source (e.g., the optical gain chip) is powered on, and adapting or changing the position of the photonic chip and/or the waveguide-fiber connector to optimize the detected coupled light or the optical signal. The flip-chip bonding equipment may align the optical waveguides in the chips with high and sufficient accuracy (such as ±0.5 μm) to ensure a uniform bondline with respect to the interposer and/or the optional VLSI driver chip. This may be accomplished by first bonding the optical gain chip to the electrically active interposer while ensuring electrical connectivity to the chips bonded to it. Then, the optical gain chip may be powered up via the interposer to generate the optical signal. Next, the photonic chip may be brought into immediate edge contact (a so-called ‘active edge’ where light is either exiting or entering) with the edge of the optical gain chip and the optical signal is coupled into the optical waveguide(s) in the photonic chip. Similar operations may be performed with the waveguide-fiber connector and the photonic chip.
(15) Note that the photonic chip and/or the waveguide-fiber connector may have fixed or temporary electrical connectivity to allow the coupled light to be detected and measured externally, so that the position with the highest detected optical signal can be determined. Moreover, note that the MCM may be fabricated using individual chips or in wafer-scale integration. Furthermore, a permanent adhesive (such as epoxy) may be used in order to secure the aligned assembly.
(16) FIG. 1 presents a diagram illustrating a side view of an MCM 100. This MCM includes an interposer 110, an optical gain chip 112 and a photonic chip 114. For example, optical gain chip 112 may include a substrate 116 that includes a III-V compound-semiconductor and an optical waveguide 118. In an exemplary embodiment, optical gain chip 112 is a semiconductor optical amplifier and/or a laser. Furthermore, photonic chip 114 may be an SOI photonic chip. Therefore, photonic chip 114 may include: silicon substrate 120; a buried-oxide layer (BOX) 122 disposed on silicon substrate 120; and a semiconductor (silicon) layer 124 disposed on buried-oxide layer 122, where another optical waveguide 126 is defined in semiconductor layer 124. Note that photonic chip 114 may: provide optical feedback to optical gain chip 112; control and stabilize power/current delivery to optical gain chip 112; control and stabilize the operating laser wavelength; data-modulate the out-coming optical stream; and/or receive optical signals and encode data.
(17) Moreover, optical gain chip 112 and photonic chip 114 may be disposed on a top surface 128 of interposer 110, which is electrically coupled to optical gain chip 112 and photonic chip 114 by a matching set of electrical pads or connectors 130. For example, traces disposed on semiconductor layer 124 (i.e., on a top surface of photonic chip 114) may face and may be electrically coupled to top surface 128 of interposer 110. In addition, a top surface of optical gain chip 112 may be electrically coupled to top surface 128 of interposer 110. The matching set of electrical pads or connectors 130 may power up and provide data to the photonic chip 114, and may drive current through optical gain chip 112.
(18) Note that a location 132 (relative to top surface 128) of optical waveguide 118 may be vertically aligned with a location 134 of optical waveguide 126 (relative to top surface 128). For example, top surfaces of one or more of interposer 110, optical gain chip 112 and photonic chip 114 may include one or more optical-waveguide leveling spacers or spacer layers (such as spacer 108). The optical-waveguide leveling spacers may be located on one chip and/or the other in MCM 100 depending on the vertical positions of their optical modes and the fabrication technology used to fabricate components in MCM 100. Moreover, the optical-waveguide leveling spacers may have appropriate thickness (equal to a difference between the heights or thicknesses of optical gain chip 112 and photonic chip 114) to facilitate the vertical alignment. In some embodiments, the one or more optical-waveguide leveling spacers include: a metal, a polymer and/or a resin.
(19) In this way, optical gain chip 112 and photonic chip 114 may be brought into complete six-axis alignment and optically coupled. In some embodiments, optical gain chip 112 and/or photonic chip 114 include one or more optional optical spot-size converters (SSCs) 156 that, during operation, transition a spot size of an optical mode in optical waveguide 118 (e.g., by expanding the optical mode laterally and/or vertically) to a spot size of an optical mode in optical waveguide 126 (and vice versa).
(20) Furthermore, MCM 100 may include waveguide-fiber connector (WFC) 136, mechanically coupled to top surface 128 of interposer 110, having an end 138 configured to remateably mechanically couple to optical fiber coupler or assembly (OFC) 140 (which includes an optical fiber 142-1, such as a single-mode optical fiber) and an end 144. This may allow optical fiber 142-1 to be easily and accurately mechanically and optically coupled to MCM 100. For example, waveguide-fiber connector 136 may include an optical waveguide 146 that optically couples ends 138 and 144 (and that, during operation, conveys the optical signal between ends 138 and 144). Additionally, a location 148 of optical waveguide 146 may be vertically aligned with a location 134 of optical waveguide 118 (relative to surface 128), and a location 150 of optical waveguide 146 may be vertically aligned with a location 152 of optical fiber 142-1. In particular, optical waveguide 146 may have a three-dimensional form with a varying vertical position (relative to surface 128) and, therefore, locations 148 and 150 may be at different vertical positions. By including waveguide-fiber connector 136, MCM 100 may simplify optical coupling between photonic chip 114 and optical fiber 142-1.
(21) In some embodiments, waveguide-fiber connector 136 includes a ferrule (such as an MT ferrule) for optical fiber 142-1 in optical fiber coupler 140. Moreover, waveguide-fiber connector 136 may include a material compatible with a reflow temperature exceeding a predefined threshold (such as 250 C). This may allow further thermal processing of MCM 100 without damaging waveguide-fiber connector 136. Furthermore, waveguide-fiber connector 136 may include mechanical alignment features (AF) 154 that mate with corresponding mechanical alignment features 154 (such as corresponding positive and negative alignment features, e.g., keys or pins and slots or holes) in optical fiber coupler 140, which may facilitate alignment and, thus, optical coupling in MCM 100.
(22) Note that assembly of an MCM may be complicated by the need to use pre-tested parts (so-called ‘known good die’) in order to maximize the overall packaging yield. However, as the number of die increases in the MCM, the risk of failure grows accordingly. The optical module of the transceiver in the embodiments of the MCM (which includes optical gain chip 112 and photonic chip 114) can only be tested after all optical and electrical chips have been bonded together powering it all up. It may be advantageous to first build, test, and validate an optical component in the transceiver prior to committing this part to flip-chip assembly with its already-validated optional VLSI driver chip.
(23) Interposer 110 may provide this capability. In particular, interposer 110 may provide a platform for optical gain chip 112 and photonic chip 114. Moreover, a passive interposer can be fabricated with somewhat relaxed fabrication tolerances (relative to VLSI and SOI processes) without active semiconductor elements. Furthermore, interposer 110 may provide: the optical-waveguide leveling spacers to vertically align components in MCM 100; electrical interconnects matching those of optical gain chip 112 and photonic chip 114; low-propagation-loss metal traces to provide high-fidelity data signaling at low power to photonic chip 114; mechanical strength; and/or additional options to thermally manage optical gain chip 112 and photonic chip 114.
(24) Note that multiple optical channels can be simultaneously created by coupling arrays of optical outputs from optical gain chip 112 into arrays of (optical spot-size-converter enabled) inputs of photonic chip 114. Thus, in MCM 100, there may be multiple instances of optical waveguides in optical gain chip 112, photonic chip 114 and waveguide-fiber connector 136. These optical waveguides may be routed with different pitches on the input and output interfaces, and their optical mode size can also be tailored to effectively match the optical waveguide modes of the mated devices, e.g., the optical modes of the SOI-tapered optical waveguides on one side and single-mode optical fibers on the other.
(25) In another embodiment, the MCM leverages the planar leveling provided by the interposer. In particular, the interposer may include micro-machined features that facilitate alignment and optical coupling to one or more optical fibers. For example, the micro-machined features may include V-shaped grooves (i.e., elongated, triangular trenches), which are integrated onto the interposer to facilitate accurate passive placement of single-mode optical fibers so that their optical cores are aligned with the optical waveguides in the photonic chips, thereby providing a light conduit in to and out of the MCM.
(26) The V-shaped grooves can be implemented in crystalline silicon using processing techniques, such as by using a silicon nitride hard mask and wet etching, with appropriate dimensions and orientation, and with sub-micron accuracies. For example, V-shaped grooves may be formed on a <100> oriented silicon substrate along the <110> direction. In hydroxide chemistries (such as potassium hydroxide or tetramethylammonium hydroxide), silicon etches anisotropically and forms pyramidal pits bounded by <111> planes that are angled at 54.7° relative to the <100> surface plane. An optical fiber having a diameter of 125 μm diameter can be housed in the resulting V-shaped groove. In embodiments where there are multiple optical fibers, the V-shaped grooves have a pitch that is almost as tight as the diameter of the optical fibers.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Kinghorn to disclose a bridge die, wherein the bridge die is coupled with the photonic die and the semiconductor die; a photonic die paired with a semiconductor die; wherein the bridge die is beneath both the photonic die and the semiconductor die, and wherein the bridge die is embedded in the interposer beneath both the photonic die and the semiconductor die; Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; because the resulting configuration would facilitate designing, fabricating, and deploying multichip modules. Shubin – Selected Text.
Further regarding claim 1, Kinghorn in view of Shubin does not inherently require that the interposer is a glass interposer.
However, Epitaux discloses in figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text, transparent interposer embodiments 28 comprising transparent sapphire layers 86. Epitaux, paragraph [0068] (“The optically transparent layer 86 can be made of any suitable optically transparent material, such as glass, silicon, fused silica, sapphire, borofloat, or any alternative optically transparent material suitable for forming optical waveguides.”).
Epitaux – Selected Text
[0016] With initial reference to FIG. 1, the present disclosure provides an assembly for high-bandwidth communication between an integrated circuit 22 and at least one optical fiber. For instance the at least one optical fiber may be part of at least one fiber cable 24, which may include a plurality of optical fibers. For instance, the high bandwidth communication can be from the integrated circuit 22 to the at least one optical fiber. Alternatively or additionally, the high bandwidth communication can be from the at least one optical fiber to the integrated circuit 22. The integrated circuit 22 can be configured as a microprocessor, field programmable gate array, or the like. Generally, the integrated circuit 22 can be referred to as an application specific integrated circuit (ASIC) 26. Thus, reference herein to the ASIC 26 can apply equally to the integrated circuit 22 unless otherwise indicated, and vice versa. The present disclosure provides an interposer 28 that is disposed between at least one photonic integrated circuit 27 and at least one optical fiber so as to provide for optical communication between the at least one photonic integrated circuit 27 and the at least one optical fiber. The interposer 28 can be configured as an optically transparent interposer 28. For instance, the at least one optically transparent interposer 28 can provide optical communication from the at least one photonic integrated circuit 27 to a respective at least one optical fiber. Alternatively or additionally, the optically transparent interposer 28 can provide optical communication from the at least one optical fiber to the at least one photonic integrated circuit 27. The at least one photonic integrated circuit can include a plurality of photonic integrated circuits. The at least one optical fiber can include a plurality of optical fibers. Additionally, the optically transparent interposer 28 can conduct electrical signals to and/or from an optical engine 32 that is mounted on the optically transparent interposer 28. The optical engine 32 can include the photonic integrated circuit 27. The optical engine 32 can include one or both of an optical transmitter and an optical receiver. The photonic integrated circuit 27 of the optical transmitter can be configured as a SiPho chip 30. Thus, reference herein to the SiPho chip 30 can apply equally to the photonic integrated circuit 27 unless otherwise indicated, and vice versa. The photonic integrated circuit 27 can also be configured as a vertical cavity surface emitting laser (VCSEL) in some examples. Optically transparent materials for use herein for optically transparent structures, including the interposer 28, can include glass or silicon, fused silica, sapphire, borofloat, or any alternative suitable optically transparent material. The assembly may be referred to as a photonically co-packaged ASIC 20 and vice versa.
[0037] The SiPho chip 30 can be positioned over the recessed region 52, such that the SiPho chip 30 is aligned with the recessed region 52 during alignment of the waveguides and electrical contacts of the SiPho chip 30 and the optically transparent interposer 28. The outer surface 23 can define the recessed region 52. Thus, the outer surface 23 defines a recessed portion at the recessed region 52 that can be recessed toward the inner surface 25 along the transverse direction T with respect to the outer surface 23 outside the recessed region 52. The outer surface 23 can define a second portion that is outside the recessed region 52. Optical coupling portions of the SiPho chip waveguides 48 can rest against the outer surface 23 of the optically transparent interposer 28 outside the recessed region 52 when the SiPho chip 30 is mounted to the optically transparent interposer 28. In particular, the electrical contact 53 of the SiPho chip 30 can be disposed above the recessed region 52 and aligned with the recessed region 52 along the transverse direction T.
[0038] While the optical waveguides 41 of the optically transparent interposer 28 are illustrated as straight and linear in FIG. 2A, it should be appreciated that optical circuitry of greater complexity may be fabricated on the optically transparent interposer 28. For instance, the waveguides 41 can curve. Further, the wavelength division multiplexers and/or demultiplexers 42 (see FIG. 1) can be incorporated into the waveguide circuitry. Also, as shown in FIG. 1, multiple optical engines 32, and thus multiple SiPho chips 30, can be mounted on a single optically transparent interposer 28. Similarly, multiple optical fiber cables 24 may mate with the single optically transparent interposer 28.
[0054] As illustrated in FIGS. 4A-4B, and as described above, the photonic integrated circuit 27 is configured to be mounted to the interposer 28, such that the photonic integrated circuit 27 is optically coupled to the interposer 28. In particular, the interposer 28 includes at least one optical waveguide 41 such as a plurality of waveguides 41. The photonic integrated circuit 27 similarly includes at least one waveguide 48 such as a plurality of waveguides 48. Each of the waveguides 41 and 48 can include respective adiabatic coupling regions. In one example, the adiabatic coupling regions of the waveguides 41 and 48 can be tapered in the manner described above. Alternatively, it is envisioned that either the waveguides 41 are tapered or the waveguides 48 are tapered at the respective adiabatic coupling regions, and the other waveguides are not tapered at the adiabatic coupling regions. The adiabatic coupling regions of one or both of the plurality of waveguides 41 and 48 can adiabatically couple the waveguides to each other.
[0055] Further, the photonic integrated circuit 27 can be electrically coupled to the interposer 28. Thus, the interposer 28 can be disposed between the photonic integrated circuit 27 and the underlying host substrate 34 (see FIG. 1), and can be electrically connected to each of the photonic integrated circuit 27 and the underlying host substrate 34. As discussed above, the assembly 58 can include at least one stud bump 50 such as a plurality of stud bumps 50 that are in electrical connection with each of the interposer 28 and the photonic integrated circuit 27. For instance, the interposer 28 can include at least one electrical contact pad 54 such as the plurality of electrical contact pads 54. Similarly, the photonic integrated circuit 27 can include at least one electrical contact pad 53 such as the plurality of electrical contact pads 53. The assembly 58 can include at least one stud bump 50 such as a plurality of stud bumps 50. The stud bumps 50 can be configured to be mounted to respective pairs of electrical contact pads. Each pair of electrical contact pads can be defined by a respective one of the electrical contact pads 54 and a respective one of the electrical contact pads 53.
[0067] The interposer body 35 can define a raised pedestal 88 so as to define a portion of the upper surface 23 of the interposer 28. In particular, the raised pedestal 88 can define a portion of the inner surface in the recessed region 52. The upper surface 23 of the raised pedestal 88 can be configured to establish an electrical connection with the SiPho chip 30 in the manner described above. For instance, the optically transparent interposer 28 can include the redistribution layer 90 that is formed on the upper surface 23 at the pedestal 88. The redistribution layer 90 may include one or more layers of conductive metal traces on a dielectric material, such as, but not limited to, polyimide or benzocyclobutene. The redistribution layer 90 can be configured to position the location of the electrically conductive mounts 50 so that they align with matching pads of the electrical contacts 53 of the SiPho chip 30. The pedestal 88 can have a height along the transverse direction T that is sufficient so as to at least partially define the recessed region 52 having a gap 92 between the upper surface 23 at the body 35 and the inner surface 37 of the SiPho chip 30 to accommodate the electrical mount 50 that can extend from the contact pad of the electrical contact 53 to the contact pad of the electrical contact 54. Thus, in the example illustrated in FIG. 7, the pedestal 88 can be configured such that the height of the pedestal 88 along the transverse direction T plus the compressed height of the electrically conductive mount 50 can equal the height of the optically transparent layer 86. The optically transparent layer 86 can define a hole that extends therethrough and is oriented along the transverse direction T, and is aligned with the pedestal 88 along the transverse direction T.
[0068] The optically transparent layer 86 can be made of any suitable optically transparent material, such as glass, silicon, fused silica, sapphire, borofloat, or any alternative optically transparent material suitable for forming optical waveguides. One example of a glass that is commercially available is Schott D263T; though any glass suitable for forming optical waveguides may be used. Schott D263T is commercially available by Schott Glass Technologies, Inc. having a place of business in Moosic, Pa. In some embodiments, the optically transparent layer may be formed from drawn glass having sufficiently flat and smooth opposing surfaces such that no polishing step is required prior to forming the optical waveguides 41. The thickness of the optically transparent layer can in the range of 100 to 400 microns, so that it has sufficient mechanical strength for convenient handling and processing. The optical waveguides 41 described in all examples herein may be formed from any known technique, such as, but not limited to, ion-exchange, laser processing, or micro-structuring. The optical waveguides 41 of the optically transparent interposer 28 that extend along the optically transparent layer can be disposed adjacent to and optically coupled with the optical waveguides 48 of the SiPho chip 30 in the manner described above. Accordingly, the optical waveguides 41 can be adiabatically coupled with the optical waveguides 48 of the SiPho chip. Thus, the interposer optically transparent layer can have a bore 94 that is aligned with the pedestal 88 of the body 35. To assemble the optically transparent interposer 28, the optically transparent layer can be placed over the body 35 so that the pedestal 88 of the body 35 is aligned with the bore 94 along the transverse direction T. The optically transparent layer can be bonded to the base using a bonding layer 96. The bonding layer 96 may, for example, be a thin adhesive.
Consequently, in light of Epitaux’s disclosure of transparent glass sapphire glass interposer embodiments, it would have been obvious to one of ordinary skill in the art to modify Kinghorn in view of Shubin to disclose: a glass interposer; and an electro-optic modulator integrated with the glass interposer and coupled between the optical fiber connector and the photonic die; Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; because the resulting configuration would facilitate designing, fabricating, and deploying multichip modules; Shubin – Selected Text. Wangs figs 10 and 11; characterized by transparent sapphire layers; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; which would facilitate designing, fabricating, and deploying lithium niobate optical modulators. Wang – Selected Text (disclosing LN Mach-Zehnder modules formed on thin sapphire layers).
Wang – Selected Text
[0086] The techniques described herein are applicable to a broad range of integrated electro-optic devices based on thin film LN devices, including Mach-Zehnder interferometer based modulators, switches, and linear modulators. The same fabrication methods are applicable where waveguide-based interferometers are used instead of micro-resonators, so that a much larger optical operation bandwidth can be achieved. The contact electrodes may be placed much closer to each other than alternative bulk LN modulators due to much better light confinement, thus reducing the modulation voltage. Moreover, the small bending radius allows wiring the waveguides and reduces the overall RF propagation length and electronic capacitance, enabling ultra-high speed and low energy consumption modulators. The same device configurations are also applicable to high on/off-ratio, low insertion loss optical switches. Unlike the plasma dispersion effect in silicon and the quantum-confined Stark effect in indium phosphide, the Pockels effect is intrinsically linear. High-speed linear modulators may be built without expensive signal post-processing, which is crucial in analog circuits and communications.
[0087] Referring now to FIGS. 10-11, microwave transmission line velocity matching is illustrated in cross-sectional views of exemplary waveguides according to the present disclosure. Velocity matching is not supported in alternative LN modulators because the microwave dielectric permittivity of LN is very high (˜28). This results in a low microwave group velocity in comparison to light being guided on the LN chip. In alternative modulators, low permittivity SiO.sub.2 buffer layers may be used to increase microwave group velocity, which results in reduced modulation efficiency. In thin film designs as set forth herein, because the optical mode is confined in the LN thin film, the substrate is not required to be high permittivity. Thus, the bulk substrate can be a low RF index material such as Si, quartz, silica, sapphire, or a combination thereof, so that the optical and microwave group velocity can be perfect matched.
[0088] In FIG. 10, LN waveguide 1001 has high permittivity, resulting in a high index (about 5). The optical index of the optical mode 1002 is about 2.2. As a result, velocity matching is difficult. As described above, in various exemplary embodiments, electrodes 1003 may be gold.
[0089] In FIG. 11, LN waveguide 1101 is arranged on SiO.sub.2 layer 1104, which in turn is arranged on substrate wafer 1105. In various embodiments, the substrate may be silicon, quartz, silica, sapphire, or a combination thereof. The optical index of the optical mode 1102 is about 2.2. SiO.sub.2 layer 1104 and substrate 1105 (e.g., silicon) have a low index (3.4 for silicon, 2.0 for quartz and silica, 3.0-3.3 for sapphire) so the optical and microwave velocity can be matched. As described above, in various exemplary embodiments, electrodes 1003 may be gold.
[0090] Due to the improved modulation efficiency obtained through shorter electrodes and better velocity matching, higher bandwidth (of about 100 GHz or greater) with a lower drive voltage (about 2V or less) may be obtained as compared to alternative approaches.
[0091] As noted above, LN displays a wide bandgap (high transparency) and a large second order (χ2) electro-optic coefficient (about 30 pm/V). In contrast to silicon and Indium phosphide (InP), the χ2 process in LN changes its index of refraction linearly with an applied electrical field, at femtosecond timescale. The efficiency of this process is determined by the overlap of the optical and the electrical fields. Alternative ion-diffused LN waveguides suffer from the low refractive index contrast (Δn<0.02) between core and cladding, resulting in large optical modal volumes and bending radii. As a result, the photonic structures are large and the radio-frequency (RF) electrodes have to be placed far away from the optical mode to prevent detrimental waveguide propagation loss, significantly reducing electro-optic switching efficiency.
Regarding dependent claims 4-8 and 23-24, it would have been obvious to one of ordinary skill in the art to modify Kinghorn in view of Shubin further in view of Epitaux and further in view of Wang, as applied in the rejection of claim 1, to disclose:
4. The electro-optic system of claim 1, wherein the glass interposer includes an electro-optical material layer and wherein the electro-optic modulator includes a pair of parallel waveguides that have at least portions in the electro-optical material layer. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
5. The electro-optic system of claim 4, wherein the electro-optical material layer includes lithium, niobium, and oxygen. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
6. The electro-optic system of claim 1, wherein the photonic die is within a cavity in the glass interposer. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
7. The electro-optic system of claim 1, wherein the glass interposer includes an electro-optical material layer and wherein the electro-optic modulator includes a pair of parallel waveguides that have at least portions in the electro-optical material layer, and further including one or more electrodes of the electro-optic modulator, wherein the one or more electrodes include portions of a metallic layer on the electro-optical material layer. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
8. The electro-optic system of claim 1, further including a wirebond coupled between the photonic die and the electro-optic modulator. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text. (The examiner notes that wire bonding is a well-known, well-characterized, and often-used design and fabrication technique.)
23. The electro-optic system of claim 1, wherein the bridge die couples the photonic die and the semiconductor die. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
24. The electro-optic system of claim 6, wherein the glass interposer includes an electro-optical material layer and wherein the photonic die in the cavity in the glass interposer is aligned with at least one waveguide in the electro-optical material layer. Kinghorn, figure 23, and related figures and text, for example, Kinghorn – Selected Text; Shubin, figure 1, and related figures and text, for example, Shubin – Selected Text; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; Wang – Selected Text, and related figures and text.
because the resulting configurations would facilitate designing, fabricating, and deploying multichip modules; Shubin – Selected Text. Wangs figs 10 and 11; characterized by transparent sapphire layers; Epitaux, figures 1, 3, and 5-7, and related figures and text, for example, Epitaux – Selected Text; which would facilitate designing, fabricating, and deploying lithium niobate optical modulators. Wang – Selected Text (disclosing LN Mach-Zehnder modules formed on thin sapphire layers).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached on M-Th 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg, can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, See http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/PETER RADKOWSKI/Primary Examiner, Art Unit 2874