Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This Final Rejection is filed in response to Applicant Arguments/Remarks Made in an Amendment filed 12/18/2025.
Claims 1 and 11 are amended.
Claims 1-18 remain pending.
Response to Arguments
Argument 1, Applicant argues in Applicant Arguments/Remarks Made in an Amendment filed 12/18/2025, on pg. 6-8 that the prior art fails to teach the primary claim limitation, “the integrated circuit being associated with one or more circuit parameters and comprising hardware circuitry implementing at least a portion of a convolutional neural network”.
Response to Argument 1, applicant’s arguments have been considered, however in light of the amendments a newly found combination of prior art (Salami, B., et al. (2020). An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration. UPCommons Institutional Repository (Universitat Politècnica de Catalunya). https://doi.org/10.1109/dsn48063.2020.00032, hereinafter “Salami”, and further in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”) is applied to updated rejections.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, B., et al. (2020). An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration. UPCommons Institutional Repository (Universitat Politècnica de Catalunya). https://doi.org/10.1109/dsn48063.2020.00032, hereinafter “Salami”, and further in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”.
Claim 1:
Salami teaches a method for managing computing resource utilization, the method comprising:
iteratively performing steps comprising:
operating an integrated circuit at a voltage the integrated circuit being associated with one or more circuit parameters and comprising hardware circuitry implementing at least a portion of a convolutional neural network (i.e. pg. 139, [1.1 Contributions], “this paper experimentally studies the power-performance-accuracy characteristics of CNN accelerators with greatly reduced supply voltage capability implemented in real FPGAs. In summary, we achieve a total of more than 3X power-efficiency improvement for FPGA-based CNN accelerators”, wherein FGPA’s of a CNN are iteratively operated lower and lower undervolted parameters. Wherein the FPGA’s are hardware that are part of a FPGA-based CNN)
at the voltage, applying known input data to the portion of the CNN to obtain an inference result (i.e. pg. 142, [3.3.2 Undervolting methodology], “the voltage scaling capability is provided using an on-board voltage regulator that can convert an input voltage level of 12V into different voltage levels… In this paper, we focus on on-chip voltage rails: VCCINT and VCCBRAM… we monitor the power consumption of each voltage rail as well as the on-chip temperature”, where a known voltage is applied to the VCCINT and VCCBRAM hardware of the CNN to obtain a CNN accuracy); comparing the inference result to a corresponding reference result to determine whether the integrated circuit satisfies one or more metrics (i.e. pg. 143, [4. Overal Voltage Behavior], “we observe that Vmin = 570mV (on average) is the minimum safe voltage level of the accelerator, where there is no accuracy loss”, wherein an accuracy result is compared to a corresponding normally powered CNN accuracy result to determine a loss metric); in response to determining that the integrated circuit satisfies the one or more metrics, lowering the voltage to obtain one or more values for a set of operational parameters that comprises a reduced voltage (i.e. pg. 143, [4.2 Overall Voltage Behavior], “As we further undervolt below Vmin, we enter a region called the critical region in which the reliability of the hardware and, in turn, the accuracy of the CNN starts to decrease significantly”, wherein voltage is iteratively lowered while the accuracy metric is met to obtain lower and lower operational undervolting parameters)
in response to the determining that the integrated circuit, operated at the reduced voltage, does not satisfy at least some of the one or more metrics (i.e. pg. 143, [4.2 Overall Voltage Behavior], “When we undervolt down to a specific point, called Vcrash, the FPGA becomes non-functional and starts to hang”, wherein a circuit may cease functioning and not satisfy accuracy metrics), determining a safety margin (i.e. pg. 143, [4.2 Overall Voltage Behavior], “43% further power-efficiency gain is due to further undervolting in the critical region, which has an associated CNN accuracy loss cost”, wherein the BRI for a safety margin encompasses operating circuitry at above the critical or crash region, wherein accuracy of a CNN starts to have a loss cost or results in failure of the CNN); and
operating the CNN at the operating voltage to obtain a CNN output (i.e. pg. 147, [8.2.2 Hardware-level Techniques], “Undervolting has been shown to provide significant power-efficiency benefit for CNNs when applied to SRAMs”, wherein the CNN may be undervolted to within the guard band level of voltage to obtain an CNN output accuracy above a threshold).
While Salami teaches operating a CNN at different voltages depending on a comparable accuracy metric and identifying a voltage safety margin to operate the CNN so that an accuracy level is reached, Salami may not explicitly teach,
determining a safety margin to be added to the reduced voltage to obtain an operating voltage;
However, Qureshi teaches
in response to determining that the integrated circuit (i.e. para. [0007], FIG. 1 in block diagram form is an integrated circuit having memory with dynamic voltage adjustment), operated at the reduced voltage (i.e. para. [0018], Fig. 4, In a step 88 a determination is made by the test circuit 70 whether the test memory 60 has correctly functioned in a write and a read operation. If the test memory 60 has correctly functioned, the test supply voltage V.sub.Test is lowered by a gradated amount in a step 90), does not satisfy at least some of the one or more metrics (i.e. para. [0018], “the test memory 60 continues to pass a write and read operation with the lowered V.sub.Test, the V.sub.Test is again lowered, steps 84-86 are repeated and so on until the test memory 60 fails at a lowered V.sub.Test supply voltage value”, wherein the BRI for one or more metrics encompasses a test memory),
Qureshi further teaches
determining a safety margin to be added to the reduced voltage to obtain an operating voltage (i.e. para. [0018], Thus a safety margin is added in. In a step 94, the supply voltage V.sub.DD1 is adjusted upward by making V.sub.DD1 equal to the newly determined value of V.sub.operating).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, in response to the determining that the integrated circuit, operated at the reduced voltage, does not satisfy at least some of the one or more metrics, determining a safety margin to be added to the reduced voltage to obtain an operating voltage, to Salami’s CNN circuit voltage control, with how when a threshold metric is not satisfied, a circuits operating voltage is reduced by a determined safety margin and an operating voltage is obtained, as taught by Qureshi. One would have been motivated to combine the conditional determination of a safety voltage reduction of Qureshi with the CNN voltage control of Salami in order to have a failure metric determination action be a determined voltage reduction by a safety margin, and would have had a reasonable expectation of success as the combination enhances the protection of a circuit by providing an accurate programmatic voltage control.
Claim 8:
Salami and Qureshi teach the method of claim 1.
Salami further teaches wherein the method for increasing [managing] computing capacity in CNNs is performed in response to a change in a target application (i.e. pg. 11, Section 5.3, “when operating at reduced-voltage levels, accuracy loss is relatively high due to lower precision; ii) power-efficiency is proportional to voltage as well as quantization levels. In conclusion, combining low-precision and low-voltage operation can significantly deliver higher power efficiency. However, it comes at the cost of accuracy loss”, wherein the using low-voltage operation may be performed in response to a change to a low-precision application of the CNN).
Claim 11:
Claim 11 is the system claim reciting similar limitations to Claim 1 and is rejected for similar reasons.
Salami further teaches
A power supply having a voltage (i.e. pg. 139, [1.1 Contributions], “this paper experimentally studies the power-performance-accuracy characteristics of CNN accelerators with greatly reduced supply voltage capability implemented in real FPGAs”, wherein the power supply to the FGPAs may operate at a reduced voltage);
an integrated circuit having one or more circuit parameters, the integrated circuit comprising: A memory device; A convolution neural network (CNN) coupled to the memory device (i.e. pg. 142, [3.3.1 Prototype FPGA platform], ZCU102isequipped with an 8GB64-bit DDR-4 off-chip memory. In our implementation, this memory contains input images and CNN parameters);
A controller being coupled to the CNN and the power supply comprising a comparator (i.e. pg. 142, [3.3.2 Undervolting Methodology], “To access these voltage rails for monitoring and regulation, we use a PMBus adapter and the provided API [65]. Using a similar approach and different PMBus commands, we monitor the power consumption of each voltage rail as well as the on-chip temperature”, wherein different power supplies may be compared):
One or more sensors coupled to the integrated circuit (i.e. pg. 142, [3.3.2 Undervolting Methodology], the voltage scaling capability is provided using an on-board voltage regulator that can convert an input voltage level of 12V into different voltage levels. The voltage level of the output lines, usually called volt age rails, is fully configurable and also addressable).
Claim(s) 2, 7, & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”, as applied to claim 1 and 11 above, and further in view of U.S. Patent Application Publication NO. 20100097855, “Bayle”.
Claim 2:
Salami and Qureshi teach the method of claim .
While Salami-Qureshi teach determining that a circuit satisfies the one or more metrics, Salami-Qureshi may not explicitly teach,
in response to the integrated circuit satisfying the one or more metrics, using a controller coupled to the circuit to cause the voltage to increase by a predetermined amount.
However, Bayle teaches
in response to the integrated circuit (i.e. para. [0063], “the non-volatile semiconductor memory device determines and sets the programming start voltage for programming according to a programming pulse number at the moment the verifying process passes in the preceding programming”, wherein the BRI for an IC encompasses a semiconductor device with associated control circuit) satisfying the one or more metrics, using a controller coupled to the integrated circuit to cause the voltage to increase by a predetermined amount (i.e. para. [0007, 0063], “increasing the programming voltage from a predetermined programming start voltage by a predetermined voltage increment gradually and verifying it at the same time”, wherein the BRI for satisfying one more metrics encompasses how the verifying process is determining if the threshold voltage of the memory cell is within the threshold voltage range of corresponding write-in state).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, in response to the integrated circuit satisfying the one or more metrics, using a controller coupled to the integrated circuit to cause the voltage to increase by a predetermined amount, to the circuit inference model and power controls of Salami-Qureshi, with how a circuit voltage may be increased by a predetermined amount when a circuit satisfies metric such as a safe voltage threshold range, as taught by Bayle. One would have been motivated to combine Bayle with Salami-Qureshi and would have had a reasonable expectation of success as the combination increases the likely hood of protecting a circuit from becoming overly degraded as the voltage may be raised in a gradual and controlled manner.
Claim 7:
Salami, Qureshi, and Bayle teach the method of claim 2.
Bayle further teaches further comprising using the controller to adjust the voltage to the predetermined amount (i.e. para. [0007], “increasing the programming voltage from a predetermined programming start voltage by a predetermined voltage increment gradually”, wherein the BRI for a predetermined amount encompasses a predetermined voltage increment).
Claim 12:
Claim 12 is the system claim reciting similar limitations to Claim 2 and is rejected for similar reasons.
Claim(s) 3-5, 9-10, & 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”, and further in view of U.S. Patent Application Publication NO. 20100097855, “Bayle”, as applied to claim 2 above, and further in view of U.S. Patent Application Publication NO. 20140300189, “Nakano”.
Claim 3:
Salami, Qureshi, and Bayle teach the method of claim 2.
Salami, Qureshi, and Bayle may not explicitly teach
using one or more detection circuits coupled to the controller to determine one or more physical parameters
Nakano further comprising using one or more detection circuits coupled to the controller to determine one or more physical parameters (i.e. para. [0093], “when the DC received voltage Vdc detected by the voltage detection section 22 is equal to or higher than a predetermined threshold voltage Vth (Vdc.gtoreq.Vth), the control section 27 in the electronic unit 2 performs the following voltage reduction control”, wherein the BRI for a physical parameter encompasses voltage).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, using one or more detection circuits coupled to the controller to determine one or more physical parameters, to the CNN circuit inference model and power controls of Salami-Qureshi-Bayle, with using one or more detection circuits coupled to the controller to determine one or more physical parameters, as taught by Nakano. One would have been motivated to combine Nakano with Salami-Qureshi-Bayle and would have had a reasonable expectation of success as the combination provides more accurate and appropriate control during power feeding.
Claim 4:
Salami, Qureshi, and Bayle teach the method of claim 2.
Salami, Qureshi, and Bayle may not explicitly teach
using the controller to adjust the one or more circuit parameters based on at least one measured physical parameter.
However, Nakano teaches comprising
using the controller to adjust the one or more circuit parameters based on at least one measured physical parameter (i.e. para. [0093], “the control section 27 may use one or more of the dummy loads in the dummy load circuit 23 to perform such voltage reduction control”, wherein the BRI to adjust a circuit parameter encompasses to increase a circuit load to perform a voltage reduction control).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, using the controller to adjust the one or more circuit parameters based on at least one measured physical parameter, to the CNN circuit inference model and power controls of Salami-Qureshi-Bayle, with using the controller to adjust the one or more circuit parameters based on at least one measured physical parameter, as taught by Nakano. One would have been motivated to combine Nakano with Salami-Qureshi-Bayle and would have had a reasonable expectation of success as the combination provides more accurate and appropriate control during power feeding.
Claim 5:
Salami, Qureshi, Bayle, and Nakano teach the method of claim 4.
Nakano further teaches wherein the safety margin that accounts for at least one of the one or more physical parameters or for at least one of the one or more circuit parameters (i.e. para. [0098], “the value of such an increased DC received voltage Vdc is controlled to be lower than the element withstanding voltage Vb (is avoided from exceeding the element withstanding voltage Vb). For example, in the case where the element withstanding voltage Vb is 24 V, the threshold voltage Vth may be considered to be set to about 10 V in consideration of a margin”, wherein the voltage reduction control accounts for parameters such as voltage).
Claim 9:
Salami, Qureshi, Bayle, and Nakano teach the method of claim 3,
Salami further teaches
wherein the at least the portion of the CNN, represents a computational path in the integrated circuit (i.e. pg. 142, [3.3.2 Undervolting methodology], “Each voltage rail feeds one or more components of the FPGA platform. ZCU102 is equipped with three voltage regulators… In this paper, we focus on on-chip voltage rails: VCCINT and VCCBRAM, as shown in Figure 2”, wherein Vccint and Vccbram represent the path of the power supply voltage to the IC and RAM of the FGPA circuits.
Claim 10:
Salami, Qureshi, Bayle, and Nakano teach the method of claim 9.
Salami further teaches wherein the known input data comprises a test pattern configured to test the computational path (i.e. pg. 140, [2.2 Undervolting], “the Vnom of Xilinx FPGAs is 1V, 0.9V, and 0.85V for implementations in 28nm, 20nm, and 16nm technology nodes, respectively. The aim of our undervolting technique is to reduce the supply voltage below the default Vnom”, wherein the BRI for a test patten encompasses an iterative voltage reduction pattern that is configured to test the computational path of the CNN to failure) and
further comprises at least one of configuration data or weight data that have been selected to increase data processing efficiency (i.e. pg. 139, [1.1 Contributions], “Our experiments show that the most energy-efficient operating point is the one with the maximum frequency and minimum safe voltage, namely, Vmin. However, lower voltage and lower frequency lead to better power-efficiency”, wherein the BRI for a configuration data encompasses a voltage level selected to data power-efficiency) .
Claim 14:
Claim 14 is the system claim reciting similar limitations to Claim 10 and is rejected for similar reasons.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”, and further in view of U.S. Patent Application Publication NO. 20100097855, “Bayle”, and further in view of U.S. Patent Application Publication NO. 20140300189, “Nakano”, as applied to claim 14 above, and further in light of U.S. Patent Application Publication NO. 20190277913, “Honda”.
Claim 15:
Salami, Qureshi, Bayle, and Nakano teach the system of claim 14.
While Salami teaches detecting a level at which a circuit fails in a test pattern, Salami, Qureshi, Bayle, and Nakano may not explicitly teach
wherein the test pattern is configured to detect a location of a circuit
However, Honda teaches
wherein the test pattern is configured to detect a location of a circuit (i.e. Para. [0025], all the individual integrated circuits that have been formed on the wafer are tested for functional defects, for example, by applying test patterns using a wafer probe. Circuits may either pass or fail the testing procedure, and failed circuits will be marked or otherwise identified, e.g., stored in a file that represents the location of the failed circuits on a wafer map).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, wherein the test pattern is configured to detect a location of a circuit, to the test pattern of Salami-Qureshi-Bayle- Honda, with a test pattern may include marking the location of the failed circuits, as taught by Honda. One would have been motivated to combine Honda with Salami-Qureshi-Bayle-Nanako and would have had a reasonable expectation of success as the combination leverages data to improve efficiencies in the semiconductor and electronics industries by providing user’s with more detailed information.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”, as applied to claim 11 above, and further in view of U.S. Patent Application Publication NO. 20140300189, “Nakano”.
Claim 16:
Salami and Qureshi teach the system of claim 11.
Salami and Qureshi may not explicitly teach
wherein the controller adjusts the one or more circuit parameters based on at least one measured physical parameter obtained from one or more detection circuits parameter.
However, Nakano teaches wherein the controller adjusts the one or more circuit parameters based on at least one measured physical parameter obtained from one or more detection circuits parameter (i.e. para. [0093], “the control section 27 may use one or more of the dummy loads in the dummy load circuit 23 to perform such voltage reduction control”, wherein the BRI to adjust a circuit parameter encompasses to increase a circuit load to perform a voltage reduction control based on an obtained voltage within a threshold range).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, wherein the controller adjusts the one or more circuit parameters based on at least one measured physical parameter obtained from one or more detection circuits parameter, to the CNN circuit inference model and power controls of Salami-Qureshi, with wherein the controller adjusts the one or more circuit parameters based on at least one measured physical parameter obtained from one or more detection circuits parameter, as taught by Nakano. One would have been motivated to combine Nakano with Salami-Qureshi and would have had a reasonable expectation of success as the combination provides more accurate and appropriate control during power feeding.
Claim(s) 6 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salami, in view of U.S. Patent Application Publication NO. 20090016140, “Qureshi”, in view of U.S. Patent Application Publication NO. 20100097855, “Bayle”, and further in view of U.S. Patent Application Publication NO. 20140300189, “Nakano”, as applied to claim 5 above, and further in view of U.S. Patent Application Publication NO. 20210016080, “Minogue”.
Claim 6:
Salami, Qureshi, Bayle, and Nakano teach the method of claim 5.
Salami-Qureshi-Nakano-Bayle may not explicitly teach
further comprising, deriving the safety margin based on a statistical model that uses a distribution of samples related to the one or more physical parameters to calculate a confidence interval.
However, Minogue teaches
deriving the safety margin based on a statistical model that uses a distribution of samples related to the one or more physical parameters to calculate a confidence interval (i.e. para. [0095], “A sample population of users can be assessed to measure the actual voltage waveform in response to a series of pulses across of range of current amplitudes. A statistical model is built of the mean and 95% confidence interval for upper end of the expected voltage envelope for a given current”, wherein a confidence interval is based on a distribution of samples from users related to a physical parameter such as measured voltage waveforms).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add, deriving the safety margin based on a statistical model that uses a distribution of samples related to the one or more physical parameters to calculate a confidence interval, to the circuit inference model and power controls of Salami-Qureshi-Bayle-Nakano, with how a safety margin is calculated based on a statistical model using a distribution of user samples related to one or more physical parameters to calculate a confidence interval, as taught by Minogue. One would have been motivated to combine Minogue with Salami-Qureshi-Bayle-Nakano and would have had a reasonable expectation of success as the combination provides more data security than a single point estimate and result in a more statistically significant number.
Claim 17:
Claim 17 is the system claim reciting similar limitations to Claim 4 and is rejected for similar reasons.
Claim 18:
Salami, Qureshi, Bayle, Nakano, and Minogue teach the system of claim 17.
Minogue further teaches wherein the one or more physical parameters comprise at least one of an environmental condition or a circuit impedance (i.e. para. [0123], “An abnormal condition can therefore be detected when a voltage is measured outside the predefined normal range. It is known that electrode impedance can change during the course of a stimulation session”, wherein impedance related to a measured circuit may be used in identifying an abnormal voltage range).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication NO. 20140289553 "Takano" teaches in para. [0174], The failure diagnostic device 18 is equipped with a test pattern generator 48 for the plurality of scanning path circuits 47 and a compressor 49. The compressor 49 compresses the responses to a test pattern coming from the scanning path circuits 57.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID H TAN whose telephone number is (571)272-7433. The examiner can normally be reached M-F 7:30-4:30.
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/D.T./Examiner, Art Unit 2145
/CESAR B PAULA/Supervisory Patent Examiner, Art Unit 2145