DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to the amendment filed on 5/19/2026.
Claims 8, 11, 19 and 23 have been canceled.
Claim 24 has been added.
Claims 1, 9, 15 and 20 have been amended.
Claims 1-7, 9-10, 12-18, 20-22 and 24 are pending for consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/19/2026 has been entered.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1-7, 9-10, 12-18, 20-22 and 24 have been considered but are moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Iqbal (US 20240171179) (hereinafter Iqbal) in view of OCHERETNY (US 20220156410) (hereinafter OCHERETNY), and further in view of Shlomo et al. (US 20220014180) (hereinafter Shlomo).
Regarding claim 1, Iqbal discloses a device comprising:
base registers that receive input signals (Iqbal: fig. 2, elements 204, 226, paragraphs 0027-0029),
shadow registers that correspond to the base registers (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]), wherein the shadow registers receive inverted input signals (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027, any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]),
attack detector logic that receives the first respective output signals from the base registers (Iqbal fig. 2 element R2, paragraphs 0003 and 0027-0029, “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.”; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3), receives the second respective output signals from the shadow registers (Iqbal fig. 2 R1B, paragraphs 0027-0029) and generates an alarm signal based on the first respective output signals and the second respective output signals (Iqbal fig. 2, element 228, paragraphs 0003 and 0027-0029, “any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch …e.g., bi-stable latch”, NOTE: the voting logic is ALSO used for DECTECTION of error/failure).
Iqbal does not explicitly disclose the following limitations which are disclosed by OCHERETNY, receives a reset signal (OCHERETNY: fig.5 rst, paragraph 0039, that is flip-flops with asynchronous reset), receive an inverted reset signal (OCHERETNY: fig. 5, paragraph 0039 (
Y
1
¯
->
X
2
¯
,
Y
2
¯
→
X
3
¯
), by registers which have inverted reset inputs), and wherein the second respective output signals are based on the inverted input signals and the inverted reset signal (OCHERETNY: fig. 5, paragraph 39, [examiner remark: each output is the result of information coming from each corresponding inputs and the inverted rst signal]).
Iqbal and OCHERETNY are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal and OCHERETNY before him or her, to modify the system of Iqbal to include a reset signal, an inverted reset signal, and an output signal based on an inverted input signal and an inverted reset signal of OCHERETNY. The suggestion/motivation for doing so would have been for improved protection against fault attacks in circuits (OCHERETNY: paragraph 0001).
Iqbal and OCHERETNY does not explicitly disclose the following limitation which is disclosed by Shlomo, alarm latch logic that receives the alarm signal from the attack detector logic and stores the alarm signal to provide a latched alarm signal (Shlomo: figure 4, figure 7 and paragraphs 0035, 0042-0043, 0045, 0053-0054, 0056 and 0071-0076, “The voltage-glitch-detection-block 418 includes in addition to the glitch-detector 420 and at least a first voltage-glitch protected S/R latch 422a. The first voltage-glitch protected S/R latch 422a has a set (S) input coupled to the voltage-glitch-detector 420 to receive the PULSE therefrom, an output connected to the first CMOS level-detector 414a to couple the PULSE_LATCHED signal thereto”… “The voltage-glitch-detector 420 can include any suitable voltage or current based comparator capable of detecting a SCA (side channel voltage-glitch attack) or a voltage-glitch with similar properties”… “enabling the glitch-isolated latch 700 to provide its own supply voltage once a voltage-glitch has been detected by the voltage-glitch-detector 600 and the PULSE_Latched signal generated, thereby isolating voltage-glitch-isolated latch from extreme voltage-glitch conditions, and increasing reliability of the voltage-glitch detection and protection circuit.”).
Iqbal in view of OCHERETNY and Shlomo are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal in view of OCHERETNY and Shlomo before him or her, to modify the system of Iqbal in view of OCHERETNY to include an alarm latch logic that receives the alarm signal from the attack detector logic and stores the alarm signal to provide a latched alarm signal of Shlomo. The suggestion/motivation for doing so would have been for detecting and protecting against a side channel voltage-glitch attack (Shlomo: paragraph 0009).
Regarding claim 2, Iqbal as modified discloses
wherein: each of the shadow registers receives a respective inverted reset value provided by the inverted reset signal (OCHERETNY: fig. 5, paragraph 0039, by registers which have inverted reset inputs,
Y
1
¯
,
Y
2
¯
), receive an inverted reset signal (OCHERETNY: fig. 5, paragraph 0039, by flip-flops with asynchronous set);
the attack detector logic is configured to sense a malicious attack based on the first respective output signals and the second respective output signals, and the attack detector logic is configured to generate the alarm signal based on sensing the malicious attack (Iqbal: paragraphs 0027-0029, 0046 and 0051, “detect whether R1 or one of the R2 stages failed and use another stage as a dummy replacement, thereby enabling the complementary 2(N)-bit redundant circuitry 118 to implement error detection and correction”… “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected”). The same motivation to modify Iqbal in view of OCHERETNY and Shlomo, as applied in claim 1 above, applies here.
Regarding claim 3, Iqbal as modified discloses wherein: the base registers and the shadow registers are arranged in corresponding pairs of a respective base register and a respective shadow register (OCHERETNY: see figure 5 and paragraph 0039, “The circuits in the above examples contain only combinatorial logic. FIG. 5 illustrates an example where the original circuit includes sequential logic (i.e., registers). The system 500 in FIG. 5 is similar to the system of FIG. 3, but instead the original circuit 505 includes sub-circuits 531, 533, 535, which are implemented as combinatorial logic, and register stages 532, 534 between the sub-circuits. The dual circuit 510 is derived from the original circuit 505”). The same motivation to modify Iqbal in view of OCHERETNY and Shlomo, as applied in claim 1 above, applies here.
Regarding claim 4, Iqbal as modified discloses wherein: polarity of the reset signal and the inverted reset signal alternate for each subsequent pair of a respective corresponding pair (OCHERETNY: see figure 5, items 532534, 542 and 544 and paragraph 0039, “registers of the original circuit are replaced by registers which have inverted reset inputs (that is flip-flops with asynchronous reset are replaced by flip-flops with asynchronous set, and vice versa), so that after reset they will contain inverted values in comparison to the values in the registers in the original circuit.”). The same motivation to modify Iqbal in view of OCHERETNY and Shlomo, as applied in claim 1 above, applies here.
Regarding claim 5, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first respective output signals and the second respective output signals from the corresponding pairs of base registers and shadow registers, and the first logic is configured to provide intermediate alarm signals based on the first respective output signals and the respective second output signals (Iqbal: Figure 2 and paragraphs 0027 and 0028, “R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like”… “Respective outputs of the registers 202, 204, and 206 can be coupled to the voting logic 124 either directly or through another instance of the data inversion logic 122 to provide data values or complemented data values to the voting logic 124, which can be configured as described herein (e.g., with reference to FIG. 3) to provide an output data value to a data output 228 of the complementary 2(N)-bit redundant circuitry”).
Regarding claim 6, Iqbal as modified discloses wherein: the attack detector logic includes second logic that is configured to receive the intermediate alarm signals from the first logic (Iqbal: paragraphs 0016-0017 and 0029-0031, “the circuit may include voting logic that is configurable to enable voting functionality from one or more of the complementary logic paths (e.g., R1B and/or R2B). As described herein, aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claim 24, Iqbal as modified discloses wherein the alarm signal is generated in response to a mismatch between at least one of the first respective output signals and at least one of the second respective output signals (Shlomo: figure 4, figure 7 and paragraphs 0035, 0042-0043, 0045, 0053-0054, 0056 and 0071-0076, “The voltage-glitch-detection-block 418 includes in addition to the glitch-detector 420 and at least a first voltage-glitch protected S/R latch 422a. The first voltage-glitch protected S/R latch 422a has a set (S) input coupled to the voltage-glitch-detector 420 to receive the PULSE therefrom, an output connected to the first CMOS level-detector 414a to couple the PULSE_LATCHED signal thereto”… “The voltage-glitch-detector 420 can include any suitable voltage or current based comparator capable of detecting a SCA (side channel voltage-glitch attack) or a voltage-glitch with similar properties”… “enabling the glitch-isolated latch 700 to provide its own supply voltage once a voltage-glitch has been detected by the voltage-glitch-detector 600 and the PULSE_Latched signal generated, thereby isolating voltage-glitch-isolated latch from extreme voltage-glitch conditions, and increasing reliability of the voltage-glitch detection and protection circuit.”). The same motivation to modify Iqbal in view of OCHERETNY and Shlomo, as applied in claim 1 above, applies here.
Claims 9-10, 12-18 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Iqbal (US 20240171179) (hereinafter Iqbal) in view of OCHERETNY (US 20220156410) (hereinafter OCHERETNY), and further in view of Baum et al. (US 20220100601) (hereinafter Baum).
Regarding claim 9, Iqbal discloses a device comprising:
a base register that receives an input signal (Iqbal: fig. 2, elements 204, 226, and paragraphs 0027-0029),
a first shadow register that corresponds to the base register (Iqbal: fig. 2 element 202, paragraphs 0027-0029; (Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal: paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 29]), wherein the first shadow register receives an inverted input signal (Iqbal: fig. 2, element 230, paragraphs 0027-0029),
a second shadow register that corresponds to the base register (Iqbal: fig. 2, element 206, paragraphs 0027-0029), wherein the second shadow register receives the input signal (Iqbal: fig. 2, element 226, paragraphs 0027-0029),
attack detector logic (Iqbal: fig. 2, element 124, paragraphs 0003 and 0027-0029) that separately: receives the first output signal from the base register (Iqbal: fig. 2 element R2, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3), receives the second output signal from the first shadow register (Iqbal: fig. 2 R1B, paragraphs 0027-0029), receives the third output signal from the second shadow register (Iqbal: fig. 2 element R3, paragraphs 0027-0029) and generates one or more alarm signals based on the first output signal, the second output signal and the third output signal (Iqbal: fig. 2, element 228, paragraphs 0027-0029).
Iqbal does not explicitly disclose the following limitations which are disclosed by OCHERETNY, receives a reset signal (OCHERETNY: fig.5 rst, paragraph 0039, that is flip-flops with asynchronous reset), receive an inverted reset signal distinct from the reset signal (OCHERETNY: fig. 5, paragraph 0039 (
Y
1
¯
->
X
2
¯
,
Y
2
¯
→
X
3
¯
), by registers which have inverted reset inputs), provides an output signal based on the inverted input signal and the inverted reset signal (OCHERETNY: fig. 5, paragraph 39, [examiner remark: each output is the result of information coming from each corresponding inputs and the inverted rst signal]) and provides an output signal based on the input signal and the reset signal (OCHERETNY: fig. 5, X2, X3, paragraph 0039).
Iqbal and OCHERETNY are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal and OCHERETNY before him or her, to modify the system of Iqbal to include a reset signal, an inverted reset signal, an output signal based on an inverted input signal and an inverted reset signal and an output signal based on an input signal and a reset signal of OCHERETNY. The suggestion/motivation for doing so would have been for improved protection against fault attacks in circuits (OCHERETNY: paragraph 0001).
Iqbal in view of OCHERETNY does not explicitly disclose the following limitation, which is disclosed by Baum, wherein the one or more alarm signals are generated in response to a mismatch between the first output signal and at least one of the second output signal or third output signal (Baum: paragraphs 0025-0027, 0387, 0421, 0450-0451, 0456-0457 and 0462, “providing a plurality of redundant hardware resources in the neural network processor, allocating a main computational path from the plurality of redundant hardware resources, the main computational path to be protected from end to end failures, allocating one or more redundant computational paths from the plurality of redundant hardware resources, the one or more redundant computational paths operative to protect the main computational path from end to end failures, calculating cyclic redundancy code (CRC) checksums on tensor stream data output from the main computational path and the one or more redundant computational paths, and detecting an error if the calculated CRC checksums do not match”…“By suitable configuration of the target comparison multiplexer 1450, the checksum calculated by the CRC engine 1448 can be compared to a preconfigured expected CRC checksum 1454 via comparator 1452. An error signal 1457 is raised if a mismatch is detected”).
Iqbal in view of OCHERETNY and Baum are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal in view of OCHERETNY and Baum before him or her, to modify the system of Iqbal in view of OCHERETNY to include one or more alarm signals are generated in response to a mismatch between a first output signal and at least one of a second output signal or third output signal of Baum. The suggestion/motivation for doing so would have been to provide a level of safety to improve system immunity (Baum: paragraph 0016).
Regarding claim 15, claim 15 discloses a device claim that is substantially equivalent to the device of claims 1 and 9. Therefore, the arguments set forth above with respect to claim 15 are equally applicable to claims 1 and 9 and rejected for the same reasons. Iqbal as modified further discloses the at least three registers are configured to provide distinct output signals (Iqbal: fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal para. 27,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029])), attack detector logic configured to: receive the distinct output signals from the first base register and each of: the first and the second shadow registers (Iqbal fig. 2, R1B is distinct from R3, paragraphs 0027-0029); and generate one or more alarm signals based on the distinct output signals (Iqbal fig. 2, element 228, paragraphs 0027-0029).
Regarding claims 10 and 16, Iqbal as modified discloses the attack detector logic is configured to sense a malicious attack based on the first output signal, the second output signal and the third output signal, and the attack detector logic is configured to generate one or more alarm signals based on sensing the malicious attack, wherein the one or more alarm signals comprise first and second alarm signals: and wherein the attack detector logic is configured to: generate the first alarm signal based on the first output signal and the second output signal, and generate the second alarm signal based on the first output signal and the third output signal (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claims 12, Iqbal as modified discloses wherein: the first shadow register is disposed proximate to the corresponding base register in comparison to a disposition the second shadow register, and the second shadow register is disposed distant from their corresponding base register in comparison a disposition to the first shadow register (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]).
Regarding claim 13, Iqbal as modified discloses wherein: the alarm signal includes a first alarm signal that refers to a first type of malicious attack proximate to the base register, wherein the malicious attack is proximate to the base register in comparison to the disposition of the first shadow register, and the alarm signal includes a second alarm signal that refers to a second type of malicious attack distal from the base register, wherein the malicious attack is distal to the base register in comparison to the disposition of the second shadow register (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claim 14, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first output signal from the base register, receive the second output signal from the first shadow register and generate the first alarm signal, and the attack detector logic includes second logic that is configured to receive the first output signal from the base register, receive the third output signal from the second shadow register and generate the second alarm signal (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claim 17, claim 17 discloses a device claim that is substantially equivalent to the device of claim 9. Therefore, the arguments set forth above with respect to claim 17 are equally applicable to claim 9 and rejected for the same reasons.
Regarding claim 18, claim 18 discloses a device claim that is substantially equivalent to the device of claims 9 and 15. Therefore, the arguments set forth above with respect to claim 18 are equally applicable to claims 9 and 15 and rejected for the same reasons.
Regarding claim 20, Iqbal as modified discloses wherein each base register receives a corresponding input signal and provides a corresponding base register output signal, and each shadow register receives a corresponding input signal and provides a corresponding shadow register output signal (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]), and further comprising: alarm latch logic that receives the alarm signal from the attack detector logic, latches the alarm signal, and provides a latched alarm signal (Iqbal fig. 2, paragraphs 0027-0029).
Regarding claim 21, claim 21 discloses a device claim that is substantially equivalent to the device of claims 9 and 15. Therefore, the arguments set forth above with respect to claim 21 are equally applicable to claims 9 and 15 and rejected for the same reasons.
Regarding claim 22, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first base register output signal and the first shadow register output signal, the first logic is configured to provide an intermediate alarm signal based on the first register output signal and the first shadow register output signal, the attack detector logic has second logic that is configured to receive the intermediate alarm signal from the first logic and receive the second shadow register output signal from the second shadow register, and the second logic is configured to generate an alarm signal based on the intermediate alarm signal from the first logic and the second shadow register output signal from the second shadow register (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art has been incorporated into the record and does not disclose, individually or in reasonable combination, the features disclosed in claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG T DOAN whose telephone number is (571)272-0740. The examiner can normally be reached Monday-Friday 7-4 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn D Feild can be reached on (571)272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG T DOAN/Primary Examiner, Art Unit 2431
Prosecution Insights