DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to the amendment filed on 9/29/2025.
Claims 8, 11, 19 and 23 have been canceled.
Claims 1 and 7 have been amended.
Claims 1-7, 9-10, 12-18 and 20-22 are pending for consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot.
Applicant's arguments filed on 9/29/2025 have been fully considered but they are not persuasive.
Applicant argues on page 10 of the Remarks that Iqbal merely describes redundancy registers (R1, R2, R3). These registers are functionally identical storage elements used for redundancy and voting, not base and shadow registers configured with distinct input and reset behavior.
In response to the above argument, the Examiner respectfully disagrees. It is noted that neither the claims nor the specification provides an explicit definition of the terms “base and shadow registers”. Furthermore, claim 9 does not recite distinct input and reset behavior as stated in the Remarks. Therefore, Applicant’s argument is not persuasive. The combination of Iqbal and Ocheretny teaches at least three registers, each providing distinct outputs, with attack detector logic as claimed in claim 9 (See pages 9-11 of the office action mailed on 6/30/2025 or a detailed rejection below).
Applicant argues on page 10 of the Remarks that Iqbal does not contemplate (and therefore cannot teach or suggest) a three-register grouping in which one shadow register receives an inverted input and an inverted reset distinct from the base register, while a second shadow register receives the same input and reset as the base register. This per-register reset differentiation and three-register structural relationship is absent from Iqbal. Ocheretny does not cure this deficiency because its dual-circuit architecture only provides paired chains and comparators.
In response to the above argument, the Examiner respectfully disagrees. Applicant is reminded that one cannot show nonobviousness by attacking
references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981 ); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The combination of Iqbal and Ocheretney teaches at least three registers grouping in which one shadow register receives an inverted input and an inverted reset distinct from the base register, while a second shadow register receives the same input and reset as the base register (see pages 9-11 of the office action mailed on 6/30/2025 or a detailed rejection below).
Applicant argues on pages 10-11 of the Remarks that Iqbal does not operate on distinct outputs from a base register and two shadow registers… Iqbal's voter logic is designed to mask SEU faults by majority voting, not to generate alarms based on divergent outputs, and Ocheretny's duplication scheme again is limited to dual outputs compared at a final stage. Neither Iqbal nor Ocheretny envision the claimed arrangement.
In response to the above argument, the Examiner respectfully disagrees. Applicant is reminded that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981 ); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The Examiner notes that Iqbal's voter logic is designed to generate alarms based on divergent outputs (Iqbal: Abstract and paragraphs 0003, “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.”). Furthermore, the combination of Iqbal and Ocheretney does teach at least three registers, each providing distinct outputs, with attack detector logic (see pages 9-12 of the office action mailed on 6/30/2025 or a detailed rejection below).
Applicant argues on pages 11-12 of the Remarks that the combination is possible only with impermissible hindsight. As explained in MPEP § 2142 and § 2145, hindsight reconstruction occurs when the claims themselves are used as a roadmap to combine disparate teachings. Without Applicant's teachings, there is no articulated motivation or reasonable expectation of success to modify Iqbal's SEU voter logic into an attack detector with alarm generation, or to transform Ocheretny's duplication scheme into the claimed three-register architectures.
In response to the above argument, the Examiner respectfully disagrees. The Applicant does not establish why the proposed modification that would render the reference inoperable. The Applicant does not establish how a person of ordinary skill in the art would arbitrarily apply the teaching of Iqbal in the teaching of Ocheretny, or how a person of ordinary skill in the art would not be able to combine the two teachings. Iqbal teaches at least three registers with distinct outputs and an attack detector logic (See Figure 2, and paragraphs 0003 and 0027, “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.”… “Respective outputs of the registers 202, 204, and 206 can be coupled to the voting logic 124 either directly or through another instance of the data inversion logic 122 to provide data values or complemented data values to the voting logic 124, which can be configured as described herein (e.g., with reference to FIG. 3) to provide an output data value to a data output”). Ocheretny teaches a reset signal (OCHERETNY: fig.5 rst, paragraph 0039, that is flip-flops with asynchronous reset), an inverted reset signal (OCHERETNY: fig. 5, paragraph 0039 (
Y
1
¯
->
X
2
¯
,
Y
2
¯
→
X
3
¯
), by registers which have inverted reset inputs) and second respective output signals are based on inverted input signals and inverted reset signal (OCHERETNY: fig. 5, paragraph 39, [examiner remark: each output is the result of information coming from each corresponding inputs and the inverted rst signal]). Both Iqbal and OCHERETNY teaches art regarding error detection. It would be obvious to a person of ordinary skill in the art to use OCHERETNY’s reset/inverted signals in place of Iqbal’s input signals to generate outputs for error detection. Therefore, the rejection has been maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Iqbal (US 20240171179) (hereinafter Iqbal) in view of OCHERETNY (US 20220156410) (hereinafter OCHERETNY), and further in view of Chen et al. (US 20210042188) (hereinafter Chen).
Regarding claim 1, Iqbal discloses a device comprising:
base registers that receive input signals (Iqbal: fig. 2, elements 204, 226, paragraphs 0027-0029),
shadow registers that correspond to the base registers (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]), wherein the shadow registers receive inverted input signals (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027, any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]),
attack detector logic that receives the first respective output signals from the base registers (Iqbal fig. 2 element R2, paragraphs 0003 and 0027-0029, “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.”; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3), receives the second respective output signals from the shadow registers (Iqbal fig. 2 R1B, paragraphs 0027-0029) and generates an alarm signal based on the first respective output signals and the second respective output signals (Iqbal fig. 2, element 228, paragraphs 0003 and 0027-0029, “any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch …e.g., bi-stable latch”, NOTE: the voting logic is ALSO used for DECTECTION of error/failure).
Iqbal does not explicitly disclose the following limitations which are disclosed by OCHERETNY, receives a reset signal (OCHERETNY: fig.5 rst, paragraph 0039, that is flip-flops with asynchronous reset), receive an inverted reset signal (OCHERETNY: fig. 5, paragraph 0039 (
Y
1
¯
->
X
2
¯
,
Y
2
¯
→
X
3
¯
), by registers which have inverted reset inputs), and wherein the second respective output signals are based on the inverted input signals and the inverted reset signal (OCHERETNY: fig. 5, paragraph 39, [examiner remark: each output is the result of information coming from each corresponding inputs and the inverted rst signal]).
Iqbal and OCHERETNY are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal and OCHERETNY before him or her, to modify the system of Iqbal to include a reset signal, an inverted reset signal, and an output signal based on an inverted input signal and an inverted reset signal of OCHERETNY. The suggestion/motivation for doing so would have been for improved protection against fault attacks in circuits (OCHERETNY: paragraph 0001).
Iqbal and OCHERETNY does not explicitly disclose the following limitation which is disclosed by Chen, and alarm latch logic that receives the alarm signal from the attack detector logic, latches the alarm signal, and provides a latched alarm signal (Chen: paragraphs 0040, 0043-0045 and 0091-0092, “error signal 136 and may be latched”… “Error signals are generated and latched as second result 120 and sent to other circuits as error signals 136”).
Iqbal in view of OCHERETNY and Chen are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal in view of OCHERETNY and Chen before him or her, to modify the system of Iqbal in view of OCHERETNY to include an alarm latch logic that receives an alarm signal from an attack detector logic, latches the alarm signal, and provides a latched alarm signal of Chen. The suggestion/motivation for doing so would have been to initiate a repair operation to correct or replace any failing bit (Chen: paragraph 0045).
Regarding claim 2, Iqbal as modified discloses
wherein: each of the shadow registers receives a respective inverted reset value provided by the inverted reset signal (OCHERETNY: fig. 5, paragraph 0039, by registers which have inverted reset inputs,
Y
1
¯
,
Y
2
¯
), receive an inverted reset signal (OCHERETNY: fig. 5, paragraph 0039, by flip-flops with asynchronous set);
the attack detector logic is configured to sense a malicious attack based on the first respective output signals and the second respective output signals, and the attack detector logic is configured to generate the alarm signal based on sensing the malicious attack (Iqbal: paragraphs 0027-0029, 0046 and 0051, “detect whether R1 or one of the R2 stages failed and use another stage as a dummy replacement, thereby enabling the complementary 2(N)-bit redundant circuitry 118 to implement error detection and correction”… “the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected”). The same motivation to modify Iqbal in view of OCHERETNY and Chen, as applied in claim 1 above, applies here.
Regarding claim 3, Iqbal as modified discloses wherein: the base registers and the shadow registers are arranged in corresponding pairs of a respective base register and a respective shadow register (OCHERETNY: see figure 5 and paragraph 0039, “The circuits in the above examples contain only combinatorial logic. FIG. 5 illustrates an example where the original circuit includes sequential logic (i.e., registers). The system 500 in FIG. 5 is similar to the system of FIG. 3, but instead the original circuit 505 includes sub-circuits 531, 533, 535, which are implemented as combinatorial logic, and register stages 532, 534 between the sub-circuits. The dual circuit 510 is derived from the original circuit 505”). The same motivation to modify Iqbal in view of OCHERETNY and Chen, as applied in claim 1 above, applies here.
Regarding claim 4, Iqbal as modified discloses wherein: polarity of the reset signal and the inverted reset signal alternate for each subsequent pair of a respective corresponding pair (OCHERETNY: see figure 5, items 532534, 542 and 544 and paragraph 0039, “registers of the original circuit are replaced by registers which have inverted reset inputs (that is flip-flops with asynchronous reset are replaced by flip-flops with asynchronous set, and vice versa), so that after reset they will contain inverted values in comparison to the values in the registers in the original circuit.”). The same motivation to modify Iqbal in view of OCHERETNY and Chen, as applied in claim 1 above, applies here.
Regarding claim 5, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first respective output signals and the second respective output signals from the corresponding pairs of base registers and shadow registers, and the first logic is configured to provide intermediate alarm signals based on the first respective output signals and the respective second output signals (Iqbal: Figure 2 and paragraphs 0027 and 0028, “R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like”… “Respective outputs of the registers 202, 204, and 206 can be coupled to the voting logic 124 either directly or through another instance of the data inversion logic 122 to provide data values or complemented data values to the voting logic 124, which can be configured as described herein (e.g., with reference to FIG. 3) to provide an output data value to a data output 228 of the complementary 2(N)-bit redundant circuitry”).
Regarding claim 6, Iqbal as modified discloses wherein: the attack detector logic includes second logic that is configured to receive the intermediate alarm signals from the first logic (Iqbal: paragraphs 0016-0017 and 0029-0031, “the circuit may include voting logic that is configurable to enable voting functionality from one or more of the complementary logic paths (e.g., R1B and/or R2B). As described herein, aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Claims 9-10, 12-18 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Iqbal (US 20240171179) (hereinafter Iqbal) in view of OCHERETNY (US 20220156410) (hereinafter OCHERETNY).
Regarding claim 9, Iqbal discloses a device comprising:
a base register that receives an input signal (Iqbal: fig. 2, elements 204, 226, and paragraphs 0027-0029),
a first shadow register that corresponds to the base register (Iqbal: fig. 2 element 202, paragraphs 0027-0029; (Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal: paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 29]), wherein the first shadow register receives an inverted input signal (Iqbal: fig. 2, element 230, paragraphs 0027-0029),
a second shadow register that corresponds to the base register (Iqbal: fig. 2, element 206, paragraphs 0027-0029), wherein the second shadow register receives the input signal (Iqbal: fig. 2, element 226, paragraphs 0027-0029),
attack detector logic (Iqbal: fig. 2, element 124, paragraphs 0003 and 0027-0029) that separately: receives the first output signal from the base register (Iqbal: fig. 2 element R2, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3), receives the second output signal from the first shadow register (Iqbal: fig. 2 R1B, paragraphs 0027-0029), receives the third output signal from the second shadow register (Iqbal: fig. 2 element R3, paragraphs 0027-0029) and generates one or more alarm signals based on the first output signal, the second output signal and the third output signal (Iqbal: fig. 2, element 228, paragraphs 0027-0029).
Iqbal does not explicitly disclose the following limitations which are disclosed by OCHERETNY, receives a reset signal (OCHERETNY: fig.5 rst, paragraph 0039, that is flip-flops with asynchronous reset), receive an inverted reset signal distinct from the reset signal (OCHERETNY: fig. 5, paragraph 0039 (
Y
1
¯
->
X
2
¯
,
Y
2
¯
→
X
3
¯
), by registers which have inverted reset inputs), provides an output signal based on the inverted input signal and the inverted reset signal (OCHERETNY: fig. 5, paragraph 39, [examiner remark: each output is the result of information coming from each corresponding inputs and the inverted rst signal]) and provides an output signal based on the input signal and the reset signal (OCHERETNY: fig. 5, X2, X3, paragraph 0039).
Iqbal and OCHERETNY are analogous art because they are from the same field of endeavor, error detection. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Iqbal and OCHERETNY before him or her, to modify the system of Iqbal to include a reset signal, an inverted reset signal, an output signal based on an inverted input signal and an inverted reset signal and an output signal based on an input signal and a reset signal of OCHERETNY. The suggestion/motivation for doing so would have been for improved protection against fault attacks in circuits (OCHERETNY: paragraph 0001).
Regarding claim 15, claim 15 discloses a device claim that is substantially equivalent to the device of claims 1 and 9. Therefore, the arguments set forth above with respect to claim 15 are equally applicable to claims and 1 and 9 and rejected for the same reasons. Iqbal as modified further discloses the at least three registers are configured to provide distinct output signals (Iqbal: fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal para. 27,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029])), attack detector logic configured to: receive the distinct output signals from the first base register and each of: the first and the second shadow registers (Iqbal fig. 2, R1B is distinct from R3, paragraphs 0027-0029); and generate one or more alarm signals based on the distinct output signals (Iqbal fig. 2, element 228, paragraphs 0027-0029).
Regarding claims 10 and 16, Iqbal as modified discloses the attack detector logic is configured to sense a malicious attack based on the first output signal, the second output signal and the third output signal, and the attack detector logic is configured to generate one or more alarm signals based on sensing the malicious attack, wherein the one or more alarm signals comprise first and second alarm signals: and wherein the attack detector logic is configured to: generate the first alarm signal based on the first output signal and the second output signal, and generate the second alarm signal based on the first output signal and the third output signal (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claims 12, Iqbal as modified discloses wherein: the first shadow register is disposed proximate to the corresponding base register in comparison to a disposition the second shadow register, and the second shadow register is disposed distant from their corresponding base register in comparison a disposition to the first shadow register (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]).
Regarding claim 13, Iqbal as modified discloses wherein: the alarm signal includes a first alarm signal that refers to a first type of malicious attack proximate to the base register, wherein the malicious attack is proximate to the base register in comparison to the disposition of the first shadow register, and the alarm signal includes a second alarm signal that refers to a second type of malicious attack distal from the base register, wherein the malicious attack is distal to the base register in comparison to the disposition of the second shadow register (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claim 14, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first output signal from the base register, receive the second output signal from the first shadow register and generate the first alarm signal, and the attack detector logic includes second logic that is configured to receive the first output signal from the base register, receive the third output signal from the second shadow register and generate the second alarm signal (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Regarding claim 17, claim 17 discloses a device claim that is substantially equivalent to the device of claim 9. Therefore, the arguments set forth above with respect to claim 17 are equally applicable to claim 9 and rejected for the same reasons.
Regarding claim 18, claim 18 discloses a device claim that is substantially equivalent to the device of claims 9 and 15. Therefore, the arguments set forth above with respect to claim 18 are equally applicable to claims 9 and 15 and rejected for the same reasons.
Regarding claim 20, Iqbal as modified discloses wherein: an input signal comprises a number of input signals, a number of the input signals is the same as a number of the first base register output signals, an inverted input signal comprises a number of inverted input signals, a number of the inverted input signals is the same as a number of the first shadow register output signals (Iqbal fig. 2 element 202, paragraphs 0027-0029; Iqbal: paragraph 0029, the majority voter function could choose not to invert the R1B output, instead calculate a majority of R1, R2, and R3; Iqbal paragraph 0027,any data storage element (e.g., one-bit or two-bit storage element), including R1, R2, and/or R3 may be implemented as a latch (e.g. single latch), bi-stable latch, set-reset latch (SR latch), master-slave latch, D latch, flip-flop, D flip-flop, T-flip-flop, JK flip-flop, master-slave flip-flop, one-bit register, multi-bit register, data storage circuit, or the like; [Examiner remark: Iqbal teaches another embodiment of using R1 directly in the voting logic in paragraph 0029]), and further comprising: alarm latch logic that receives the alarm signal from the attack detector logic, latches the alarm signal, and provides a latched alarm signal (Iqbal fig. 2, paragraphs 0027-0029).
Regarding claim 21, claim 21 discloses a device claim that is substantially equivalent to the device of claims 9 and 15. Therefore, the arguments set forth above with respect to claim 21 are equally applicable to claims 9 and 15 and rejected for the same reasons.
Regarding claim 22, Iqbal as modified discloses wherein: the attack detector logic includes first logic that is configured to receive the first base register output signal and the first shadow register output signal, the first logic is configured to provide an intermediate alarm signal based on the first register output signal and the first shadow register output signal, the attack detector logic has second logic that is configured to receive the intermediate alarm signal from the first logic and receive the second shadow register output signal from the second shadow register, and the second logic is configured to generate an alarm signal based on the intermediate alarm signal from the first logic and the second shadow register output signal from the second shadow register (Iqbal fig. 2, element 228, paragraphs 0017 and 0027-0029, “aspects of complementary 2(N)-bit redundancy may prevent an SEU from affecting data stored by the replicated cells of the circuit and may also enable error detection and/or reconfigurable voting logic to address the detected errors”).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art has been incorporated into the record and does not disclose, individually or in reasonable combination, the features disclosed in claim 7 as a whole.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG T DOAN whose telephone number is (571)272-0740. The examiner can normally be reached Monday-Friday 7-4 ET.
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/TRANG T DOAN/Primary Examiner, Art Unit 2431
Prosecution Insights