DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 11, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0020650) hereinafter “Yang” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and in further view of Xiao (US 2020/0303399) hereinafter “Xiao”.
Regarding claim 1, Fig. 2 of Yang teaches a semiconductor device comprising: a plurality of first electrode layers (Items 126) spaced from one another in a first direction (Up and down across the page); a plurality of second electrode layers (Items 226) provided above the first electrode layers (Items 126), and spaced from one another in the first direction; a first columnar portion (Combination of Items 112, 110 and 108) extending in the first direction in the plurality of first electrode layers (Items 126), and including a first semiconductor layer (Item 110); a second columnar portion (Combination of Items 212, 210 and 208) provided on the first columnar portion, extending in the first direction in the plurality of second electrode layers (Items 226), and including a second semiconductor layer (Item 210); a first charge storage layer (Item 108) provided between the plurality of first electrode layers (Items 126) and the first semiconductor layer (Item 110); and a second charge storage layer (Item 208) provided between the plurality of second electrode layers (Item 226) and the second semiconductor layer (Item 210), wherein the second semiconductor layer (Item 210) is provided on the first semiconductor layer (Item 110) via a fourth semiconductor layer (Item 114), the first columnar portion includes a first portion (See Picture 1 below) having a first width (See Picture 1 below) in a second direction (Left to right across the page) intersecting the first direction, and a second portion (See Picture 1 below) provided above the first portion and having a second width (See Picture 1 below) larger than the first width in the second direction, and the second columnar portion includes a third portion (See Picture 1 below) having a third width (See Picture 1 below) in the second direction, and a fourth portion (See Picture 1 below) provided above the third portion and having a fourth width (See Picture 1 below), a width of the first columnar portion in the section direction increases in the first direction from the first portion to the second portion.
Yang does not teach where the fourth width is smaller than the third width in the second direction nor where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion.
Fig. 6 of Lee teaches a column (Item 130) of a memory device going through numerous groupings of alternating layers of electrodes (Item 121) and insulating layers (Item 122) where a first columnar portion of the column has a first portion having a first width and a second portion above the first portion having a second width, where the second width is larger than the first width, and a second columnar portion of the column has a third portion having a third width and a fourth portion above the third portion having a second width, where the fourth width is smaller than the third width (See Picture 4 below) and where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion (See Examiner’s Note 2 below).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each columnar portion of Yang comprise multiple tapered sections such that a fourth width is smaller than a third width in the second direction in the second columnar portion and where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion because the design of some vertical memory devices may have more than two stacked structures such that more memory cell strings are present (Lee Paragraph 0068).
Yang does not teach where a width of the fourth semiconductor layer in the second direction is larger than the second width, and larger than the third width.
Fig. 1A of Xiao teaches a fourth semiconductor layer (Item 110) between columnar portions where the width of the fourth semiconductor (Item 110) in a second direction (Left to right) is wider than either of the widest portions of the first and second columnar portions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a width of the fourth semiconductor layer in the second direction be larger than the second width, and larger than the third width because this allows for an interdeck plug that is wide enough to allow for any error when forming the columnar portions such that the interdeck plug electrically connects lower and upper semiconductor channels (Xiao Paragraph 0027).
Examiner’s Note: The Examiner notes that the claim language does not require that walls of the 1st columnar portion and 2nd columnar portion have constant tapers from a bottom surface of the column to a top surface of the column.
Examiner’s Note 2: The Examiner notes that the claim language merely requires that the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion. However, the claim language does not require that the width continuously decrease. Instead, the Lee reference shows where the width of the second columnar portion from the third portion to the fourth portion decreases in a stepwise manner.
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Picture 1 (Labeled version of a portion of Yang Fig. 2)
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Regarding claim 2, Fig. 2 of Yang further teaches where the plurality of first electrode layers (Items 126) are provided above a substrate (Item 100), and the first direction (Up and down across the page) is perpendicular to a surface of the substrate (Item 100).
Regarding claim 8, Fig. 2 of Yang further teaches where the second semiconductor layer (Item 210) is electrically connected to the first semiconductor layer (Item 110).
Regarding claim 11, Fig. 2 of Yang further teaches where a shape of an upper face of the first semiconductor layer (Item 110) and a shape of a lower face of the second semiconductor layer (Item 210) are each a hollow shape, and the first columnar portion includes an insulator (Item 112) in the upper face of the first semiconductor layer (Item 110) and the second columnar portion includes an insulator (Item 212) in the lower face of the second semiconductor layer (Item 210).
Regarding claim 21, Yang further teaches where the fourth semiconductor layer (Item 114) is electrically connected to the first semiconductor layer (Item 110) and the second semiconductor layer (Item 210).
Regarding claim 22, the combination of Yang, Lee and Xiao teaches all of the elements of the claimed invention as stated above except where the fourth semiconductor layer is wider than a widest portion of the first semiconductor layer and wider than a widest portion of the second semiconductor layer.
Fig. 1A of Xiao teaches a fourth semiconductor layer (Item 110) between columnar portions where the width of the fourth semiconductor (Item 110) in a second direction (Left to right) is wider than either of the widest portions of the first and second columnar portions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the fourth semiconductor layer be wider than a widest portion of the first semiconductor layer and wider than a widest portion of the second semiconductor layer because this allows for an interdeck plug that is wide enough to allow for any error when forming the columnar portions such that the interdeck plug electrically connects lower and upper semiconductor channels (Xiao Paragraph 0027).
Alternately, Claims 1, 2, 8, 9, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee”.
Regarding claim 1, Fig. 2 of Xiao teaches a semiconductor device comprising: a plurality of first electrode layers (Items 206 in Item 204A) spaced from one another in a first direction (Up and down across the page); a plurality of second electrode layers (Items 206 in Item 204B) provided above the first electrode layers, and spaced from one another in the first direction; a first columnar portion (Combination of Items 226, 216 and 227) extending in the first direction in the plurality of first electrode layers (Items 206 in Item 204A), and including a first semiconductor layer (Item 227); a second columnar portion (Combination of Items 228, 218, 229 and 210) provided on the first columnar portion, extending in the first direction in the plurality of second electrode layers (Items 206 in Item 204B), and including a second semiconductor layer (Item 229); a first charge storage layer (One of the layers of Item 226; Paragraph 0036) provided between the plurality of first electrode layers (Items 206 in Item 204A) and the first semiconductor layer (Item 227); and a second charge storage layer (One of the layers of Item 228; Paragraph 0036) provided between the plurality of second electrode layers (Items 206 in Item 204B) and the second semiconductor layer (Item 229), wherein the second semiconductor layer (Item 229) is provided on the first semiconductor layer (Item 227) via a fourth semiconductor layer (See Picture 2 below), the first columnar portion includes a first portion (See Picture 3 below) having a first width (See Picture 3 below) in a second direction (Left to right across the page) intersecting the first direction (Up and down across the page), and a second portion (See Picture 3 below) provided above the first portion and having a second width (See Picture 3 below) larger than the first width in the second direction, and the second columnar portion includes a third portion (See Picture 3 below) having a third width (See Picture 3 below) in the second direction, and a fourth portion (See Picture 3 below) provided above the third portion and having a fourth width (See Picture 3 below), a width of the first columnar portion in the section direction increases in the first direction from the first portion to the second portion, and where a width of the fourth semiconductor layer (See Picture 2 below) in the second direction (Left to right across the page) is larger than the second width and larger than the third width.
Xiao does not teach where the fourth width is smaller than the third width in the second direction nor where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion.
Fig. 6 of Lee teaches a column (Item 130) of a memory device going through numerous groupings of alternating layers of electrodes (Item 121) and insulating layers (Item 122) where a first columnar portion of the column has a first portion having a first width and a second portion above the first portion having a second width, where the second width is larger than the first width, and a second columnar portion of the column has a third portion having a third width and a fourth portion above the third portion having a second width, where the fourth width is smaller than the third width (See Picture 4 above) and where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion (See Examiner’s Note 2 below).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each columnar portion of Yang comprise multiple tapered sections such that a fourth width is smaller than a third width in the second direction in the second columnar portion and where the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion because the design of some vertical memory devices may have more than two stacked structures such that more memory cell strings are present (Lee Paragraph 0068)
Examiner’s Note: The Examiner notes that the claim language does not require that walls of the 1st columnar portion and 2nd columnar portion have constant tapers from a bottom surface of the column to a top surface of the column.
Examiner’s Note 2: The Examiner notes that the claim language merely requires that the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion. However, the claim language does not require that the width continuously decrease. Instead, the Lee reference shows where the width of the second columnar portion from the third portion to the fourth portion decreases in a stepwise manner.
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Regarding claim 2, Fig. 2 of Xiao further teaches where the plurality of first electrode layers (Items 206 in Item 204A) are provided above a substrate (Item 202), and the first direction (Up and down across the page) is perpendicular to a surface of the substrate (Item 202).
Regarding claim 8, Fig. 2 of Xiao further teaches where the second semiconductor layer (Item 229) is electrically connected to the first semiconductor layer (Item 227).
Regarding claim 9, Fig. 2 of Xiao further teaches where the second semiconductor layer (Item 229) is provided on the first semiconductor layer (Item 227) via the fourth semiconductor layer (See Picture 2 above) having a width larger than a width of an upper face of the first columnar portion in the second direction (Left to right across the page).
Regarding claim 21, Fig. 2 of Xiao further teaches where the fourth semiconductor layer (See Picture 2 above) is electrically connected to the first semiconductor layer (Item 227) and the second semiconductor layer (Item 229).
Regarding claim 22, Fig. 2 of Xiao further teaches the fourth semiconductor layer (See Picture 2 above) is wider than a widest portion of the first semiconductor layer (Item 227) and wider than a widest portion of the second semiconductor layer (Item 229).
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0020650) hereinafter “Yang” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and Xiao (US 2020/0303399) hereinafter “Xiao” and in further view of Barclay et al. (US 2020/0328222) hereinafter “Barclay”.
Regarding claim 3, the combination of Yang, Lee and Xiao teaches all of the elements of the claimed invention as stated above except where the device further comprises a first insulator provided in the first and second electrode layers, a second insulator provided in the first and second electrode layers, and a third insulator provided in only the second electrode layers out of the first and second electrode layers, positioned between the first and second insulators, and contacting none of second columnar portions in the second electrode layers.
Figs. 17 and 18 of Barclay teach a first insulator (Upper Item 48 in Fig. 17 between groups of columns) provided in a stack of electrode layers (Items 26), a second insulator (Lower Item 48 in Fig. 17 between groups of columns) provided in the stack of electrode layers (Items 26), and a third insulator (Item 82) provided in only an upper stack of electrode layers (Top Items 26) out of a lower and the upper stacks of electrode layers, positioned between the first and second insulators (Portion of Item 48 in Item 40), and contacting none of second columnar portions in the second electrode layers
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first insulator provided in the first and second electrode layers, a second insulator provided in the first and second electrode layers, and a third insulator provided in only the second electrode layers out of the first and second electrode layers, positioned between the first and second insulators, and contacting none of second columnar portions in the second electrode layers because the first and second insulators provide electrical insulation between blocks and the third insulator provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 4, the combination of Yang, Lee, Xiao and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach where the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the third insulator extends in the third direction between the first and second insulators.
Fig. 17 of Barclay teaches where the first and second insulators (Upper and Lower Item 48 in Fig. 17) extend in a third direction (Left to right across the page) intersecting the first direction (In and out of the page) and the second direction (Up and down across he page), and are adjacent to each other in the second direction (Up and down across the page), and the third insulator (Item 82) extends in the third direction (Left to right across the page) between the first and second insulators (Upper and Lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the third insulator extends in the third direction between the first and second insulators because the first and second insulators provide electrical insulation between blocks and the third insulator provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 5, the combination of Yang, Lee, Xiao and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach where the third insulator comprises a plurality of third insulators positioned between the first and second insulators.
Fig. 17 of Barclay further teaches where the third insulator (Item 82) comprises a plurality of third insulators (Items 82) positioned between the first and second insulators (Upper and lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third insulator comprise a plurality of third insulators positioned between the first and second insulators because this configuration allows for the third insulators to provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 6, the combination of Yang, Lee, Xiao and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach where the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the plurality of third insulators extend in the third direction between the first and second insulators, and are adjacent to each other in the second direction.
Fig. 17 of Barclay teaches where the first and second insulators (Upper and Lower Item 48 in Fig. 17) extend in a third direction (Left to right across the page) intersecting the first direction (In and out of the page) and the second direction (Up and down across the page), and are adjacent to each other in the second direction (Up and down across the page), and the plurality of third insulators (Items 82) extend in the third direction (Left to right across the page) between the first and second insulators (Upper and Lower Items 48), and are adjacent to each o the second direction (Up and down across the page).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the plurality of third insulators extend in the third direction between the first and second insulators, and are adjacent to each other in the second direction because the first and second insulators provide electrical insulation between blocks and the plurality of third insulators provide electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 7, the combination of Yang, Lee, Xiao and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach wherein a region between the first and second insulators corresponds to one finger of a memory, and the third insulator divides the one finger into a plurality of pages.
Fig. 17 of Barclay further teaches where a region (Item 58) between the first and second insulators (Upper and lower Items 48) corresponds to one block of a memory, and the third insulator divides the one block into a plurality of sub-blocks (Items 59).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a region between the first and second insulators correspond to one finger of a memory, and the third insulator divide the one finger into a plurality of pages because this configuration groups memory into blocks and sub blocks which may be electrically coupled or electrically isolated as desired (Barclay Paragraph 0029).
Alternatively, Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and in further view of Barclay et al. (US 2020/0328222) hereinafter “Barclay”.
Regarding claim 3, the combination of Xiao and Lee teaches all of the elements of the claimed invention as stated above except where the device further comprises a first insulator provided in the first and second electrode layers, a second insulator provided in the first and second electrode layers, and a third insulator provided in only the second electrode layers out of the first and second electrode layers, positioned between the first and second insulators, and contacting none of second columnar portions in the second electrode layers.
Figs. 17 and 18 of Barclay teach a first insulator (Upper Item 48 in Fig. 17 between groups of columns) provided in a stack of electrode layers (Items 26), a second insulator (Lower Item 48 in Fig. 17 between groups of columns) provided in the stack of electrode layers (Items 26), and a third insulator (Item 82) provided in only an upper stack of electrode layers (Top Items 26) out of a lower and the upper stacks of electrode layers, positioned between the first and second insulators (Portion of Item 48 in Item 40), and contacting none of second columnar portions in the second electrode layers
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first insulator provided in the first and second electrode layers, a second insulator provided in the first and second electrode layers, and a third insulator provided in only the second electrode layers out of the first and second electrode layers, positioned between the first and second insulators, and contacting none of second columnar portions in the second electrode layers because the first and second insulators provide electrical insulation between blocks and the third insulator provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 4, the combination of Xiao, Lee and Barclay teach all of the elements of the claimed invention as stated above.
Xiao does not teach where the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the third insulator extends in the third direction between the first and second insulators.
Fig. 17 of Barclay teaches where the first and second insulators (Upper and Lower Item 48 in Fig. 17) extend in a third direction (Left to right across the page) intersecting the first direction (In and out of the page) and the second direction (Up and down across he page), and are adjacent to each other in the second direction (Up and down across the page), and the third insulator (Item 82) extends in the third direction (Left to right across the page) between the first and second insulators (Upper and Lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the third insulator extends in the third direction between the first and second insulators because the first and second insulators provide electrical insulation between blocks and the third insulator provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 5, the combination of Xiao, Lee and Barclay teach all of the elements of the claimed invention as stated above.
Xiao does not teach where the third insulator comprises a plurality of third insulators positioned between the first and second insulators.
Fig. 17 of Barclay further teaches where the third insulator (Item 82) comprises a plurality of third insulators (Items 82) positioned between the first and second insulators (Upper and lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third insulator comprise a plurality of third insulators positioned between the first and second insulators because this configuration allows for the third insulators to provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 6, the combination of Xiao, Lee and Barclay teach all of the elements of the claimed invention as stated above.
Xiao does not teach where the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the plurality of third insulators extend in the third direction between the first and second insulators, and are adjacent to each other in the second direction.
Fig. 17 of Barclay teaches where the first and second insulators (Upper and Lower Item 48 in Fig. 17) extend in a third direction (Left to right across the page) intersecting the first direction (In and out of the page) and the second direction (Up and down across the page), and are adjacent to each other in the second direction (Up and down across the page), and the plurality of third insulators (Items 82) extend in the third direction (Left to right across the page) between the first and second insulators (Upper and Lower Items 48), and are adjacent to each o the second direction (Up and down across the page).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second insulators extend in a third direction intersecting the first direction and the second direction, and are adjacent to each other in the second direction, and the plurality of third insulators extend in the third direction between the first and second insulators, and are adjacent to each other in the second direction because the first and second insulators provide electrical insulation between blocks and the plurality of third insulators provide electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 7, the combination of Xiao, Lee and Barclay teach all of the elements of the claimed invention as stated above.
Xiao does not teach wherein a region between the first and second insulators corresponds to one finger of a memory, and the third insulator divides the one finger into a plurality of pages.
Fig. 17 of Barclay further teaches where a region (Item 58) between the first and second insulators (Upper and lower Items 48) corresponds to one block of a memory, and the third insulator divides the one block into a plurality of sub-blocks (Items 59).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a region between the first and second insulators correspond to one finger of a memory, and the third insulator divide the one finger into a plurality of pages because this configuration groups memory into blocks and sub blocks which may be electrically coupled or electrically isolated as desired (Barclay Paragraph 0029).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0020650) hereinafter “Yang” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and Xiao (US 2020/0303399) hereinafter “Xiao” and in further view of Hwang et al. (US 10,727,244) hereinafter “Hwang”.
Regarding claim 10, the combination of Yang, Lee and Xiao teaches all of the elements of the claimed invention as stated above.
Fig. 2 of Yang further teaches where wherein a shape of an upper face of the first semiconductor layer (Item 110) and a shape of a lower face of the second semiconductor layer (Item 210) are each a hollow shape.
Yang does not explicitly teach where the first columnar portion includes a semiconductor layer in the upper face of the first semiconductor layer, and the second columnar portion includes a semiconductor layer in the lower face of the second semiconductor layer.
Hwang teaches where the first columnar portion (Lower Item VS) includes a semiconductor layer (Item 128 in Lower Item VS) in a first semiconductor layer (Item CP in Lower Item VS), and a second columnar portion (Upper Item VS) includes a semiconductor layer (Item 128 in Upper Item VS) in the second semiconductor layer (Item CP in Upper Item VS).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first columnar portion includes a semiconductor layer in the upper face of the first semiconductor layer, and the second columnar portion includes a semiconductor layer in the lower face of the second semiconductor layer because the semiconductor layer in the upper and lower face of the first and second semiconductor layers, respectively, act as a pad pattern to make contact with other conductive structures (Hwang Column 9, Lines 10-16).
Alternatively, Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and in further view of Hwang et al. (US 10,727,244) hereinafter “Hwang”.
Regarding claim 10, the combination of Xiao and Lee teaches all of the elements of the claimed invention as stated above.
Fig. 2 of Xiao further teaches where wherein a shape of an upper face of the first semiconductor layer (Item 227) and a shape of a lower face of the second semiconductor layer (Item 227) are each a hollow shape.
Xiao does not explicitly teach where the first columnar portion includes a semiconductor layer in the upper face of the first semiconductor layer, and the second columnar portion includes a semiconductor layer in the lower face of the second semiconductor layer.
Hwang teaches where the first columnar portion (Lower Item VS) includes a semiconductor layer (Item 128 in Lower Item VS) in a first semiconductor layer (Item CP in Lower Item VS), and a second columnar portion (Upper Item VS) includes a semiconductor layer (Item 128 in Upper Item VS) in the second semiconductor layer (Item CP in Upper Item VS).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first columnar portion includes a semiconductor layer in the upper face of the first semiconductor layer, and the second columnar portion includes a semiconductor layer in the lower face of the second semiconductor layer because the semiconductor layer in the upper and lower face of the first and second semiconductor layers, respectively, act as a pad pattern to make contact with other conductive structures (Hwang Column 9, Lines 10-16).
Alternatively, Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and in further view of Yang et al. (US 2021/0020650) hereinafter “Yang”.
Regarding claim 11, the combination of Xiao and Lee teaches all of the limitations of the claimed invention as stated above.
Fig. 2 of Xiao further teaches where wherein a shape of an upper face of the first semiconductor layer (Item 227) and a shape of a lower face of the second semiconductor layer (Item 227) are each a hollow shape.
Xiao does not teach where the first columnar portion includes an insulator in the upper face of the first semiconductor layer, or the second columnar portion includes an insulator in the lower face of the second semiconductor layer.
Fig. 2 of Yang teaches a first columnar portion includes an insulator (Item 112) in the upper face of the first semiconductor layer (Item 110) and the second columnar portion includes an insulator (Item 212) in the lower face of the second semiconductor layer (Item 210).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first columnar portion includes an insulator in the upper face of the first semiconductor layer, or the second columnar portion includes an insulator in the lower face of the second semiconductor layer because the insulator acts as a stability structure for the hollow semiconductor layers (Yang Paragraph 0050) and provides electrical insulation between upper and lower portions of a semiconductor channel portion.
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0020650) hereinafter “Yang” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and Xiao (US 2020/0303399) hereinafter “Xiao” and in further view of Liu et al. (US 2021/0399006) hereinafter “Liu”.
Regarding claim 12, the combination of Yang, Lee and Xiao teaches all of the elements of the claimed invention as stated above except where a plurality of third electrode layers are provided above the second electrode layers, and spaced from one another in the first direction, a third columnar portion provided on the second columnar portion, extending in the first direction in the plurality of third electrode layers, and including a third semiconductor layer, and a third charge storage layer provided between the plurality of third electrode layers and the third semiconductor layer, wherein the third semiconductor layer is directly provided on the second semiconductor layer, or is provided on the second semiconductor layer via a fifth semiconductor layer, and the third columnar portion includes a fifth portion having a fifth width in the second direction, and a sixth portion provided above the fifth portion and having a sixth width smaller than the fifth width in the second direction, a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion.
Liu teaches three different tiers (Items 232, 234 and 236) of electrode layers (Items 206) stacked on top of each other, each tier having respective columnar portions extending in a first direction (Up and down across the page).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of third electrode layers provided above the second electrode layers, and spaced from one another in the first direction, a third columnar portion provided on the second columnar portion, extending in the first direction in the plurality of third electrode layers, and including a third semiconductor layer, and a third charge storage layer provided between the plurality of third electrode layers and the third semiconductor layer, wherein the third semiconductor layer is directly provided on the second semiconductor layer, or is provided on the second semiconductor layer via a fifth semiconductor layer, and the third columnar portion includes a fifth portion having a fifth width in the second direction, and a sixth portion provided above the fifth portion and having a sixth width because this configuration allows for tuning of the pitches of the respective electrode layers and insulative layers in each tier (Liu Paragraph 0020) such that the height of the memory device can be controlled to prevent collapse (Liu Paragraph 0004).
Yang does not teach where the sixth width is smaller than the fifth width in the second direction nor a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion.
Fig. 6 of Lee teaches a column (Item 130) of a memory device going through numerous groupings of alternating layers of electrodes (Item 121) and insulating layers (Item 122) where a first columnar portion of the column has a first portion having a first width and a second portion above the first portion having a second width, where the second width is larger than the first width, and a second columnar portion of the column has a third portion having a third width and a fourth portion above the third portion having a second width, where the fourth width is smaller than the third width, a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion (See Picture 4 above).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each columnar portion of Yang comprise multiple tapered sections such that a sixth width is smaller than a fifth width in the second direction in the third columnar portion and where a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion because the design of some vertical memory devices may have more than two stacked structures such that more memory cell strings are present (Lee Paragraph 0068).
Regarding claim 15, the combination of Yang, Lee, Xiao and Liu teaches all of the elements of the claimed invention as stated above.
Fig. 2 of Yang further teaches where the second semiconductor layer (Item 210) is electrically connected to the first semiconductor layer (Item 110).
Yang does not explicitly tech where the third semiconductor layer is electrically connected to the second semiconductor layer.
Fig. 2B of Liu further teaches where a third semiconductor layer (Item 116 in Item 236) is electrically connected to a second semiconductor layer (Item 116 in Item 234).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third semiconductor layer be electrically connected to the second semiconductor layer because this allows for additional memory structures to be included in deck of the memory device (Liu Paragraph 0092).
Alternatively, Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and in further view of Liu et al. (US 2021/0399006) hereinafter “Liu”.
Regarding claim 12, the combination of Xiao and Lee teaches all of the elements of the claimed invention as stated above except where a plurality of third electrode layers are provided above the second electrode layers, and spaced from one another in the first direction, a third columnar portion provided on the second columnar portion, extending in the first direction in the plurality of third electrode layers, and including a third semiconductor layer, and a third charge storage layer provided between the plurality of third electrode layers and the third semiconductor layer, wherein the third semiconductor layer is directly provided on the second semiconductor layer, or is provided on the second semiconductor layer via a fifth semiconductor layer, and the third columnar portion includes a fifth portion having a fifth width in the second direction, and a sixth portion provided above the fifth portion and having a sixth width, a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion.
Liu teaches three different tiers (Items 232, 234 and 236) of electrode layers (Items 206) stacked on top of each other, each tier having respective columnar portions extending in a first direction (Up and down across the page).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of third electrode layers provided above the second electrode layers, and spaced from one another in the first direction, a third columnar portion provided on the second columnar portion, extending in the first direction in the plurality of third electrode layers, and including a third semiconductor layer, and a third charge storage layer provided between the plurality of third electrode layers and the third semiconductor layer, wherein the third semiconductor layer is directly provided on the second semiconductor layer, or is provided on the second semiconductor layer via a fifth semiconductor layer, and the third columnar portion includes a fifth portion having a fifth width in the second direction, and a sixth portion provided above the fifth portion and having a sixth width because this configuration allows for tuning of the pitches of the respective electrode layers and insulative layers in each tier (Liu Paragraph 0020) such that the height of the memory device can be controlled to prevent collapse (Liu Paragraph 0004).
Xiao does not teach where the sixth width is smaller than the fifth width in the second direction.
Fig. 6 of Lee teaches a column (Item 130) of a memory device going through numerous groupings of alternating layers of electrodes (Item 121) and insulating layers (Item 122) where a first columnar portion of the column has a first portion having a first width and a second portion above the first portion having a second width, where the second width is larger than the first width, and a second columnar portion of the column has a third portion having a third width and a fourth portion above the third portion having a second width, where the fourth width is smaller than the third width, a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion (See Picture 4 above).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each columnar portion of Xiao comprise multiple tapered sections such that a sixth width is smaller than a fifth width in the second direction in the third columnar portion and where a width of the third columnar portion in the second direction decreases in the first direction from the fifth portion to the sixth portion because the design of some vertical memory devices may have more than two stacked structures such that more memory cell strings are present (Lee Paragraph 0068).
Regarding claim 15, the combination of Xiao, Lee and Liu teaches all of the elements of the claimed invention as stated above.
Fig. 2 of Xiao further teaches where the second semiconductor layer (Item 229) is electrically connected to the first semiconductor layer (Item 227).
Yang does not explicitly tech where the third semiconductor layer is electrically connected to the second semiconductor layer.
Fig. 2B of Liu further teaches where a third semiconductor layer (Item 116 in Item 236) is electrically connected to a second semiconductor layer (Item 116 in Item 234).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third semiconductor layer be electrically connected to the second semiconductor layer because this allows for additional memory structures to be included in deck of the memory device (Liu Paragraph 0092).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0020650) hereinafter “Yang” in view of Lee et al. (US 2017/0345843) hereinafter “Lee”, Xiao (US 2020/0303399) hereinafter “Xiao” and Liu et al. (US 2021/0399006) hereinafter “Liu” and in further view of Barclay et al. (US 2020/0328222) hereinafter “Barclay”.
Regarding claim 13, the combination of Yang, Lee, Xiao and Liu teaches all of the elements of the claimed invention as stated above except where a first insulator is provided in the first, second and third electrode layers, a second insulator is provided in the first, second and third electrode layers, and a third insulator provided in only the third electrode layers among the first, second and third electrode layers, positioned between the first and second insulators, and contacting none of third columnar portions in the third electrode layers.
Figs. 17 and 18 of Barclay teach a first insulator (Upper Item 48 in Fig. 17 between groups of columns) provided in a stack of electrode layers (Items 26), a second insulator (Lower Item 48 in Fig. 17 between groups of columns) provided in the stack of electrode layers (Items 26), and a third insulator (Item 82) provided in only an upper stack of electrode layers (Top Items 26) out of a lower and the upper stacks of electrode layers, positioned between the first and second insulators (Portion of Item 48 in Item 40), and contacting none of second columnar portions in the second electrode layers
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first insulator provided in the first, second and third electrode layers, a second insulator provided in the first, second and third electrode layers, and a third insulator provided in only the third electrode layers among the first, second and third electrode layers, positioned between the first and second insulators, and contacting none of third columnar portions in the third electrode layers because the first and second insulators provide electrical insulation between blocks and the third insulator provides electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 14, the combination of Yang, Lee, Xiao, Liu and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach where the third insulator comprises a plurality of third insulators positioned between the first and second insulators.
Fig. 17 of Barclay further teaches where the third insulator (Item 82) comprises a plurality of third insulators (Items 82) positioned between the first and second insulators (Upper and lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third insulator comprise a plurality of third insulators positioned between the first and second insulators because this configuration allows for the third insulators to provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Alternatively, Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0303399) hereinafter “Xiao” in view of Lee et al. (US 2017/0345843) hereinafter “Lee” and Liu et al. (US 2021/0399006) hereinafter “Liu” and in further view of Barclay et al. (US 2020/0328222) hereinafter “Barclay”.
Regarding claim 13, the combination of Xiao, Lee and Liu teaches all of the elements of the claimed invention as stated above except where a first insulator is provided in the first, second and third electrode layers, a second insulator is provided in the first, second and third electrode layers, and a third insulator provided in only the third electrode layers among the first, second and third electrode layers, positioned between the first and second insulators, and contacting none of third columnar portions in the third electrode layers.
Figs. 17 and 18 of Barclay teach a first insulator (Upper Item 48 in Fig. 17 between groups of columns) provided in a stack of electrode layers (Items 26), a second insulator (Lower Item 48 in Fig. 17 between groups of columns) provided in the stack of electrode layers (Items 26), and a third insulator (Item 82) provided in only an upper stack of electrode layers (Top Items 26) out of a lower and the upper stacks of electrode layers, positioned between the first and second insulators (Portion of Item 48 in Item 40), and contacting none of second columnar portions in the second electrode layers
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first insulator provided in the first, second and third electrode layers, a second insulator provided in the first, second and third electrode layers, and a third insulator provided in only the third electrode layers among the first, second and third electrode layers, positioned between the first and second insulators, and contacting none of third columnar portions in the third electrode layers because the first and second insulators provide electrical insulation between blocks and the third insulator provides electrical insulation between sub-blocks (Barclay Paragraph 0023).
Regarding claim 14, the combination of Xiao, Lee, Liu and Barclay teach all of the elements of the claimed invention as stated above.
Yang does not teach where the third insulator comprises a plurality of third insulators positioned between the first and second insulators.
Fig. 17 of Barclay further teaches where the third insulator (Item 82) comprises a plurality of third insulators (Items 82) positioned between the first and second insulators (Upper and lower Items 48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third insulator comprise a plurality of third insulators positioned between the first and second insulators because this configuration allows for the third insulators to provided electrical insulation between sub-blocks (Barclay Paragraph 0023).
Response to Arguments
Applicant's arguments filed 04/30/2026 have been fully considered but they are not persuasive.
Specifically, the Applicant first argues that Yang fails to teach the fourth semiconductor layer. The Examiner disagrees. As stated in the current rejection Fig. 2 of Yang teaches a fourth semiconductor (Item114) between first and second semiconductor layers. This was also previously identified in the previous rejection of claim 1 as the “another semiconductor layer” recited previously in claim 1 which has been changed to the fourth semiconductor layer in the amended version of claim 1. As such, the Applicant’s argument is not persuasive.
The Applicant then argues that Yang does not teach the fourth portion narrower than the third portion but this is not persuasive as the Examiner does not rely on Yang for this but instead brings in the teaching in Lee.
The Applicant argues that Lee does not teach where the thickness moving away from the substrate decreases. However, as noted previously and in the current rejection of claim 1 above, the claim language merely requires that the width of the second columnar portion in the second direction decreases in the first direction from the third portion to the fourth portion. However, the claim language does not require that the width continuously decrease. Instead, the Lee reference shows where the width of the second columnar portion from the third portion to the fourth portion decreases in a stepwise manner. As such, the Applicant’s argument is not persuasive.
Lastly, Xiao is relied upon for the teaching that the width of the fourth semiconductor layer is wider than the second portion and the third portion as Xiao teaches where a fourth semiconductor layer between two columnar portions is wider than the widest portions of the columnar portions.
As such, the Applicant’s arguments are not persuasive and the Examiner continues to rely on the combination of Yang, Xiao and other secondary references to read on the amended claim language.
The Examiner also notes that the references should be considered as a combination as presented in the rejection and not individually.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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