DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s communication filed on 06/27/2025. Claims 1-14,18-20 have been examined. Claims 15-17 are withdrawn.
Response to Arguments
Applicant’s arguments, see Remarks – Pages 9-11 , filed on 06/27/2025 with respect to the rejections of claims 1 ,18 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Ansari.
With regards to 112 2nd, Applicant’s amendment overcomes the rejection. Therefore, the rejection is withdrawn.
With regards to objection (Abstract) , Applicant’s amendment overcomes the objection. Therefore, the objection is withdrawn.
Claim Objections
Claim 1 is objected to because of the following informalities:
With regards to claim 1, the claim recites “a unified adapter layer implemented processing circuitry..”. Examiner suggests amending the claim to recite “a unified adapter layer implemented in processing circuitry”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,3,11,14 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. Publication No. US 2005/0010710 A1 (Yim hereinafter) in view of Ansari et al. Publication No. US 2019/0268629 A1 ( Ansari hereinafter)
Regarding claim 1,
Yim teaches an apparatus comprising:
a unified adapter layer implemented processing circuitry to receive a first host data packet packetized in accordance with a host protocol and directed to a first device and decode the first host data packet to generate first and second data elements based on the first host data packet, the first device associated with a first device protocol (¶0008 - If the portable storage apparatus 2 is connected to the host 1, the host 1 transmits a command packet CMD PK for setting the data bus width. The packet receiving unit of the command packet decoder 30 receives a command packet CMD_PK through the command line 10 and divides the received command packet CMD PK into a command field CMD_FD and an argument field ARG_FD. The command field decoder 32 outputs command information CMD_IF by decoding the command field CMD_FD. The argument field decoder 33 outputs data bus width information BUS_IF by decoding the argument field ARG_FD – Note Fig.1 shows Packet receiving unit receiving command packet CMD PK and generating CMD FD and ARG_FD – Note: the host device and first device (storage memory) are associated with protocols in order to perform some type communication ).
a first bus controller implemented in hardware or firmware, coupled to the unified adapter layer and configured to be electrically connected to the first device via a first bus, the first bus controller to [..] and packetize the first data element in accordance with the first device protocol to generate a first device data packet for transmission to the first device in accordance with the first device protocol via the first bus (Fig.2, ¶ 0008 -The control unit 40 receives the command information CMD IF and recognizes this information as a command for setting the data bus width. Furthermore, the control unit 40 receives the data bus width information BUS IF and stores it at a first register 50. Thereafter, the control unit 40 transmits and receives data by selecting all or some of the plurality of data lines 20, based on the data bus width information BUS_IF. Moreover, the command field decoder 32 outputs a write or a read command by decoding the command field CMD FD when transmitting and receiving general data. The argument field decoder 33 outputs an address signal by decoding the argument field AR FD when transmitting and receiving the general data – Fig.1 shows a control unit coupled to packet receiving unit and to be coupled to flash memory via data bus).
However, Yim does not explicitly teach
the first bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the first data element
Ansari teaches
the first bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the first data element (¶ 0028 - Source domain 102 also includes bus controller circuitry 132 generally configured to exchange commands and data with a plurality of bus-connected devices 136. Bus controller circuitry 132 may comply or be compatible with the bus communications protocol, for example the aforementioned USB bus communications protocol. The bus controller circuitry 132 may include bandwidth allocation logic 134 configured to allocate bandwidth among the plurality of bus-connected devices 136. Bandwidth allocation may include, for 10 example, establishing bandwidth parameters for each bus connected device 136, for example establishing a maximum data rate and/or clock speed for a given link, establishing a minimum data rate and/or clock speed for a given link, etc. Bandwidth allocation logic 134 may be configured to dynamically adjust bandwidth parameters for the bus connected devices 136 to enable, for example, excess bandwidth on one device to be allocated to another device. bus controller circuitry 132 may assign a maximum data rate and/or clock speed for the source tunneling bridge circuitry 108 to transmit commands and data to the sink domain 104. For example, a TU 125 that has eliminated, the unchanged data payload sections, may be much smaller than a TU 125 that includes the encrypted data payload section(s), and a maximum data rate allocated to bus tunneling encoding circuitry 124 may be based on the largest expected size of TU 125).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Ansari. The motivation for doing so is to allow the system to allocate the unused bandwidth to other bus-connected devices. Thus, significant efficiency of bus controller circuitry may be achieved. (Ansari – ¶ 0028).
Regarding claim 2,
Yim teaches the second data element is to define the setting of bus controller ( ¶ 0009). However, Yim does not explicitly teach
a second data element is to define at least one of a clock speed setting of a bus controller clock of the first bus controller, a slew rate of the first bus controller, and a drive strength of the first bus controller
Ansari teaches
a second data element is to define at least one of a clock speed setting of a bus controller clock of the first bus controller, a slew rate of the first bus controller, and a drive strength of the first bus controller (¶ 0028 - Source domain 102 also includes bus controller circuitry 132 generally configured to exchange commands and data with a plurality of bus-connected devices 136. Bus controller circuitry 132 may comply or be compatible with the bus communications protocol, for example the aforementioned USB bus communications protocol. The bus controller circuitry 132 may include bandwidth allocation logic 134 configured to allocate bandwidth among the plurality of bus-connected devices 136. Bandwidth allocation may include, for 10 example, establishing bandwidth parameters for each bus connected device 136, for example establishing a maximum data rate and/or clock speed for a given link, establishing a minimum data rate and/or clock speed for a given link, etc. Bandwidth allocation logic 134 may be configured to dynamically adjust bandwidth parameters for the bus connected devices 136 to enable, for example, excess bandwidth on one device to be allocated to another device. bus controller circuitry 132 may assign a maximum data rate and/or clock speed for the source tunneling bridge circuitry 108 to transmit commands and data to the sink domain 104. For example, a TU 125 that has eliminated, the unchanged data payload sections, may be much smaller than a TU 125 that includes the encrypted data payload section(s), and a maximum data rate allocated to bus tunneling encoding circuitry 124 may be based on the largest expected size of TU 125).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Ansari. The motivation for doing so is to allow the system to allocate the unused bandwidth to other bus-connected devices. Thus, significant efficiency of bus controller circuitry may be achieved. (Ansari – ¶ 0028).
Regarding claim 3,
Yim further teaches
wherein the first data element comprises one of a command data element and a payload data element ¶ 0008 - If the portable storage apparatus 2 is connected to the host 1, the host 1 transmits a command packet CMD PK for setting the data bus width. The packet receiving unit of the command packet decoder 30 receives a command packet CMD_PK through the command line 10 and divides the received command packet CMD PK into a command field CMD_FD and an argument field ARG_FD. The command field decoder 32 outputs command information CMD_IF by decoding the command field CMD_FD. The argument field decoder 33 outputs data bus width information BUS_IF by decoding the argument field ARG_FD).
Regarding claim 11,
Yim further teaches
wherein the apparatus further comprises a packet buffer coupled to the unified adapter layer and the first bus controller and the unified adapter layer is to place the first and second data elements in the packet buffer for processing by the first bus controller (¶ 0054 - Referring back to FIG. 5, the control unit 440 is connected to the data buffer 460 through the data line 420. The data line 420 includes a plurality of data lines DLl through DLN – ¶ 0055 – 056 - The control unit 440 selects all or some of the plurality of data lines DLl through DLN, and transmits or receives the data through the selected data line, in response to the data bus width information BUS_IF. [0056] The control unit 440 stores data received from the host 300 in a flash memory 450 or reads the data requested by the host 300 from the flash memory 450).
Regarding claim 14,
Yim further teaches
wherein the unified adapter layer is to receive a plurality of related host data packets including the first host data packet prior to generation of data elements associated with each of the plurality of related host data packets (¶ 0011 - the apparatus comprising at least one non-volatile memory storing data; a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information - See Also Fig.1), and.
Claims 4-5,12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Ansari further in view of Hearn et al. Publication No. US 2016/0132453 A1 (Hearn hereinafter)
Regarding claim 4,
Yim does not explicitly teach
wherein the unified adapter layer is to receive a second host data packet packetized in accordance with the host protocol and associated with a second device and generate a third data element based on the second host data packet, the second device associated with a second device protocol; and a second bus controller coupled to the unified adapter layer and to be coupled to the second device via a second bus, the second bus controller to packetize the third data element in accordance with the second device protocol to generate a second device data packet for transmission to the second device via a second bus in accordance with the second device protocol
However, Hearn teaches
wherein the unified adapter layer is to receive a second host data packet packetized in accordance with the host protocol and associated with a second device and generate a third data element based on the second host data packet, the second device associated with a second device protocol; and a second bus controller coupled to the unified adapter layer and to be coupled to the second device via a second bus, the second bus controller to packetize the third data element in accordance with the second device protocol to generate a second device data packet for transmission to the second device via a second bus in accordance with the second device protocol (¶0058 - ¶0059 - configuration processor 514 intercepts the configuration packets from the host, and creates a virtual configuration to alter the apparent bus topology. In other words, processor 514 may create a virtual configuration apparent to the host system upstream, and corresponding to the physical configuration apparent to processor 514 downstream. Devices are selectively hidden and managed by the configuration processor 514, resulting in simplified complexity and bus depth. Since selectively transparent bridge 500 appears to the host as a transparent bridge – ¶ 0060 - PCI-to-PCI bridge is indicated to the host, and the host does generate configuration packets for configuring the PCie devices. In other words, because the host considers the devices that are to be configured to be PCie devices, a standard BIOS and driver stack may be used during operation, but the configuration packets generated by the host are intercepted before reaching their intended recipients, and a virtual topology may be created based on the actual physical topology present in the subsystem downstream from bridge - The configuration unit 502 translates the target BDFs, i.e. it converts the virtual topology into the corresponding physical topology (for the downstream devices), and handles all additional tasks necessary to program the HW "hidden" from the OS/host/ system. That is why configuration packets are also redirected t configuration unit 502. ¶ 0062 - the PCie devices are configured by generating downstream configuration packets based on the actual bus topology and at least partially based on the intercepted configuration packets, and transmitting the downstream configuration packets to the PCie devices -See ¶ 0015m See Also Fig.3-6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Hearn. The motivation for doing so is to allow system to intercept the configuration packets from the host to multiple devices, and create a virtual configuration by rewriting the configuration packets, to alter how the bus topology appears to the host so that the devices can be selectively hidden and managed resulting in simplified complexity and bus depth (¶ 0014 – Hearn).
Regarding claim 5,
Yim further teaches
wherein the unified adapter layer is coupled to a configuration circuit and the unified adapter layer is to receive a third host data packet packetized in accordance with the host protocol and determine whether the third host data packet is associated with one of the first device and the second device based in part on configuration data associated with the first and second devices stored at a configuration circuit (¶ 0011 – a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information, and wherein the control unit selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-volatile memory in response to the write command or the read command and the address information).
Regarding claim 12,
Yim does not explicitly teach
wherein the first bus controller is to be coupled to a second device associated with the first device protocol via the first bus, the first device comprising a first bridge device to be coupled to at least one device and the second device comprising a second bridge device to be coupled at least one second bridge device.
However, Hearn teaches
first bus controller is to be coupled to a second device associated with the first device protocol via the first bus, the first device comprising a first bridge device to be coupled to at least one device and the second device comprising a second bridge device to be coupled at least one second bridge device (Fig.6 – ¶ 0012 - Moving downstream from a host, the number (m) assigned to a given bus is expected to be greater than the number (n) assigned to a bus upstream from the given bus in the switch fabric. For example, if the bus number of a bus connecting a host to a bridge is '1 ' , then the bus number of a bus connecting the bridge to a downstream device is expected to be greater than '1 ', such as '2' or '3 ', etc. The bus/bridge may also have a corresponding bus number range indicating the number of downstream buses. There may be situations in which the bus number range may need to be reset to make enough bus numbers available to construct the desired system – ¶ 0067 - - FIG. 6 shows a topology configuration 630, which includes a physical topology 621 and a corresponding virtual topology 620. In various embodiments, the host may be presented by virtual topology 620 instead of the actual physical topology 621. More specifically, bridges A and B (612 and 610, respectively) may be hidden to the host. PCI endpoints may allocate small memory regions (e.g. 4K) whereas bridges may allocate a minimum of 1 MB regions – See Also Fig.4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Hearn. The motivation for doing so is to allow system to intercept the configuration packets from the host to multiple devices, and create a virtual configuration by rewriting the configuration packets, to alter how the bus topology appears to the host so that the devices can be selectively hidden and managed resulting in simplified complexity and bus depth (¶ 0014 – Hearn).
Regarding claim 13,
Yim does not explicitly teach
wherein the apparatus comprises a second bus controller coupled to the unified adapter layer, the first bus controller to be coupled to at least the first device upstream of the apparatus and the second bus controller to be coupled to at least a second device downstream of the apparatus.
However, Hearn teaches
apparatus comprises a second bus controller coupled to the unified adapter layer, the first bus controller to be coupled to at least the first device upstream of the apparatus and the second bus controller to be coupled to at least a second device downstream of the apparatus(¶ 0059 - e configuration processor 514 intercepts the configuration packets from the host, and creates a virtual configuration to alter the apparent bus topology. In other words, processor 514 may create a virtual configuration apparent to the host system upstream, and corresponding to the physical configuration apparent to processor 514 downstream. Devices are selectively hidden and managed by the configuration processor 514, resulting in simplified complexity and bus depth. Since selectively transparent bridge 500 appears to the host as a transparent bridge – ¶ 0060 - PCI-to-PCI bridge is indicated to the host, and the host does generate configuration packets for configuring the PCie devices. In other words, because the host considers the devices that are to be configured to be PCie devices, a standard BI OS and driver stack may be used during operation, but the configuration packets generated by the host are intercepted before reaching their intended recipients, and a virtual topology may be created based on the actual physical topology present in the subsystem downstream from bridge - The configuration unit 502 translates the target BDFs, i.e. it converts the virtual topology into the corresponding physical topology (for the downstream devices), and handles all additional tasks necessary to program the HW "hidden" from the OS/host/ system. That is why configuration packets are also redirected t configuration unit 502. ¶ 0062 - the PCie devices are configured by generating downstream configuration packets based on the actual bus topology and at least partially based on the intercepted configuration packets, and transmitting the downstream configuration packets to the PCie devices -See Fig.4,6 and ¶ 0015).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Hearn. The motivation for doing so is to allow system to intercept the configuration packets from the host to multiple devices, and create a virtual configuration by rewriting the configuration packets, to alter how the bus topology appears to the host so that the devices can be selectively hidden and managed resulting in simplified complexity and bus depth (¶ 0014 – Hearn).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Ansari further in view of Hearn further in view of Zhu et al. Publication No. US 2021/0377840 A1 (Zhu hereinafter).
Regarding claim 6,
Yim further teaches
wherein the unified adapter layer is to receive a third host data packet packetized in accordance with the host protocol and comprising a header determine whether the third host data packet is associated with one of the first device and the second device (¶ 0011 - the apparatus comprising at least one non-volatile memory storing data; a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information - See Also Fig.1)
However, Yim does not explicitly teach
a third host data packet including an adaption type and determine whether the third host data packet is associated with one of the first device and the second device based in part on the adaption type
Zhu teaches
a third host data packet including an adaption type and determine whether the third host data packet is associated with one of the first device and the second device based in part on the adaption type (Abstract - receiving, by a first entity of an adaptation layer in a network node, a data packet sent by an entity of a lower protocol layer of the adaptation layer, wherein the data packet comprising an adaptation layer header and an adaptation layer pay load; and processing the data packet in response to determining whether the network node is a destination node that the data packet is routed to at the adaptation layer. See ¶ 210-211 - The first entity of the network node determines, based on the routing information in the Adapt layer header of the data packet, whether the network node is the destination node to which the data packet is routed at the Adapt layer. ] In a first possible implementation of the manner 1, the routing information is an identifier of the destination node of the routing at the Adapt layer. In this case, if the identifier that is of the destination node and that is carried in the Adapt layer header of the data packet is an identifier of the network node, the first entity of the network node may determine that the network node is the destination node of the routing at the Adapt layer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Zhu. The motivation for doing so is to allow system to correctly process the data packet, thereby avoiding an error in the data packet processing process (¶ 0008 – Zhu).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Ansari further in view of Hearn further in view of Liu et al. Publication No. US 2018/0349236 A1 (Liu hereinafter).
Regarding claim 7,
Yim further teaches
wherein the unified adapter layer is to receive a third host data packet packetized in accordance with the host protocol and comprising a header and determine whether the third host data packet is associated with one of the first bus controller and the second bus controller (¶ 0011 - the apparatus comprising at least one non-volatile memory storing data; a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information - See Also Fig.1).
However, Yim does not explicitly teach
third host data packet including an adaption type and determine whether the third host data packet is associated with one of the first bus controller and the second bus controller based in part on the adaption type.
Liu teaches
third host data packet including an adaption type and determine whether the third host data packet is associated with one of the first bus controller and the second bus controller based in part on the adaption type (Abstract - The method includes: determining, by a dispatcher according to information that is about a first controller and that is included in a received request message, a corresponding first driver adaptation plug-in group, where the first controller is connected to at least one driver adaptation plug-in included in the first driver adaptation plug-in group; and selecting, by the dispatcher from the at least one driver adaptation plug-in, at least one to-be-selected driver adaptation plug-in whose running status is normal, and eventually sending the request message to the first controller by using one to-be-selected driver adaptation plug-in).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Liu. The motivation for doing so is to allow system to increase the reliability of transmitting the request (¶ 0022– Liu).
Claims 8,9 are rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Ansari further in view of Kodaka et al. Publication No. US 2009/0316714 A1 (Kodaka hereinafter)
Regarding claim 8,
Yim further teaches
wherein the first host data packet comprises a header, the unified adapter layer is to associate the first data element, and the first bus controller is to transmit the first device data packet to the first device (¶ 0011 - the apparatus comprising at least one non-volatile memory storing data; a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information - See Also Fig.1).
However, Yim does not explicitly teach
first host data packet comprises a header including a priority, the unified adapter layer is to associate the priority with the first data element, and the first bus controller is to transmit the first device data packet to the first device in accordance with the priority.
Kodaka teaches
first host data packet comprises a header including a priority, the unified adapter layer is to associate the priority with the first data element, and the first bus controller is to transmit the first device data packet to the first device in accordance with the priority (¶ 0011 – the present invention provides a packet relay apparatus equipped with a bandwidth controller wherein a queuing unit equipped in the bandwidth controller acquires user information for identifying a user and priority order information from a predetermined field in a received packet, and identifies a queue for storing the packet, in accordance with the user information and priority order information. – See ¶ 0048 –¶ 0049 -The header reference unit 410 judges whether the VLAN protocol ID 1030 of a received Tag-VLAN packet is coincident with Ox8100 or 0x9100 representative of a Tag-VLAN packet (Step 2010). If coincident, by referring to the packet header information, a VLAN ID 1043 is used as the user information (Step 2020), and a user priority order 1041 is used as the priority order information (Step 2030). By using the priority order information as a search key, the priority order mapping table 430 is searched to acquire the queue information 432 corresponding to the priority order information 431 – Claim 1 - a transmission controller for transmitting said packet stored in said queue in accordance with bandwidth information).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Kodaka. The motivation for doing so is to allow system to control a bandwidth by queuing a packet in accordance with its priority order (¶ 0002 – Kodaka).
Regarding claim 9,
Yim further teaches
wherein the first host data packet comprises a header, the unified adapter layer is to associate with the first data element, and the first bus controller is to transmit the first device data packet(¶ 0011 - the apparatus comprising at least one non-volatile memory storing data; a command packet decoder for receiving command packets through the command line and outputting command information by decoding the command packets; and a control unit for performing control operations in response to the command information, wherein the command packet decoder receives one of a data transmit command packet and a data request command packet and outputs one of a write command and a read command, address information, and data bus width information - See Also Fig.1).
However, Yim does not explicitly teach
first host data packet comprises a header including an ordering, the unified adapter layer is to associate the ordering with the first data element, and the first bus controller is to transmit the first device data packet to the first device in accordance with the ordering.
Kodaka teaches
first host data packet comprises a header including an ordering, the unified adapter layer is to associate the ordering with the first data element, and the first bus controller is to transmit the first device data packet to the first device in accordance with the ordering (¶ 0011 – the present invention provides a packet relay apparatus equipped with a bandwidth controller wherein a queuing unit equipped in the bandwidth controller acquires user information for identifying a user and priority order information from a predetermined field in a received packet, and identifies a queue for storing the packet, in accordance with the user information and priority order information. – See ¶ 0048 – 0049 -The header reference unit 410 judges whether the VLAN protocol ID 1030 of a received Tag-VLAN packet is coincident with Ox8100 or 0x9100 representative of a Tag-VLAN packet (Step 2010). If coincident, by referring to the packet header information, a VLAN ID 1043 is used as the user information (Step 2020), and a user priority order 1041 is used as the priority order information (Step 2030). By using the priority order information as a search key, the priority order mapping table 430 is searched to acquire the queue information 432 corresponding to the priority order information 431 – Claim 1 - a transmission controller for transmitting said packet stored in said queue in accordance with bandwidth information).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Kodaka. The motivation for doing so is to allow system to control a bandwidth by queuing a packet in accordance with its priority order (¶ 0002 – Kodaka).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Ansari further in view of Watanabe et al. Publication No. US 2021/0297511 A1 (Watanabe hereinafter)
Regarding claim 10,
Yim does not explicitly teach
wherein the first host data packet comprises a data header including error correction data and the unified adapter layer is to implement error correction associated with the first host data packet based in part on the error correction data.
However, Watanabe teaches
the first host data packet comprises a data header including error correction data and the unified adapter layer is to implement error correction associated with the first host data packet based in part on the error correction data (¶ 0124 - an error correction code is added to the header of each packet included in the communication frame FR so that the error correction of the header can be performed during the reception process by each device, thereby protecting the header of each packet – See Also ¶ 0127).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Watanabe. The motivation for doing so is to allow system to protect the header of each packet (¶ 0124 - Watanabe).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hearn in view of Ansari
Regarding claim 18,
Hearn teaches a system comprising
a host device associated with a host protocol; a first device associated with a first device protocol; a second device associated with a second device protocol; a bridge coupled to the host device, the bridge (Fig.3-6 shows host , downstream devices (first and second device), These devices are associated in protocols in order to communicate, and A bridge coupled to the host), comprising:
a unified adapter layer implemented in processing circuity to :receive a first host data packet packetized in accordance with the host protocol and directed to the first device; generate a first data element based on the first host data packet, receive a second host data packet packetized in accordance with the host protocol and directed to the second device; and generate a second data element based on the second host data packet (¶ 0058 - The configuration CPU 514 may respond to upstream configuration packets and initiate downstream configuration packets corresponding ( or according) to the upstream configuration packets, and may also implement a bridge CSR for the subsystem - ¶ 0059 - configuration processor 514 intercepts the configuration packets from the host, and creates a virtual configuration to alter the apparent bus topology. In other words, processor 514 may create a virtual configuration apparent to the host system upstream, and corresponding to the physical configuration apparent to processor 514 downstream. Devices are selectively hidden and managed by the configuration processor 514, resulting in simplified complexity and bus depth. Since selectively transparent bridge 500 appears to the host as a transparent bridge - Note: the host device and first device (endpoints) are associated with protocols in order to perform some type communication);
a first bus controller implemented in hardware or firmware coupled to the unified adapter layer and configured to be electrically connected to the first device via a first bus, the first bus controller to[,,] and packetize the first data element in accordance with the first device protocol to generate a first device data packet for transmission to the first device via the first bus in accordance with the first device protocol(Fig.5, ¶ 0058 - the alternate output ports from the TLP Type routers 304/310 are connected to a configuration block 502, which may include various internal components, for example a CSR 504, TLP registers 508/516, flash memory 510, RAM (random access memory) 512, and a CPU 514. Message packets are relayed through the configuration processor 514 to provide a path for the legacy interrupt messages to bypass NTB 306.The configuration CPU 514 may respond to upstream configuration packets and initiate downstream configuration packets corresponding ( or according) to the upstream configuration packets, and may also implement a bridge CSR for the subsystem - ¶ 0060 - PCI-to-PCI bridge is indicated to the host, and the host does generate configuration packets for configuring the PCie devices. In other words, because the host considers the devices that are to be configured to be PCie devices, a standard BI OS and driver stack may be used during operation, but the configuration packets generated by the host are intercepted before reaching their intended recipients, and a virtual topology may be created based on the actual physical topology present in the subsystem downstream from bridge - The configuration unit 502 translates the target BDFs, i.e. it converts the virtual topology into the corresponding physical topology (for the downstream devices), and handles all additional tasks necessary to program the HW "hidden" from the OS/host/ system. That is why configuration packets are also redirected t configuration unit 502. ¶ 0062 - the PCie devices are configured by generating downstream configuration packets based on the actual bus topology and at least partially based on the intercepted configuration packets, and transmitting the downstream configuration packets to the PCie devices -See ¶ 0015, Figs.3 -6); and
a second bus controller implemented in hardware or firmware coupled to the unified adapter layer configured to be electrically connected to the second device via a second bus, the second bus controller to […] packetize the second data element in accordance with the second device protocol to generate a second device data packet for transmission to the second device via the second bus in accordance with the second device protocol (¶ 0058 - The configuration CPU 514 may respond to upstream configuration packets and initiate downstream configuration packets corresponding ( or according) to the upstream configuration packets, and may also implement a bridge CSR for the subsystem - ¶ 0060 - PCI-to-PCI bridge is indicated to the host, and the host does generate configuration packets for configuring the PCie devices. In other words, because the host considers the devices that are to be configured to be PCie devices, a standard BI OS and driver stack may be used during operation, but the configuration packets generated by the host are intercepted before reaching their intended recipients, and a virtual topology may be created based on the actual physical topology present in the subsystem downstream from bridge - The configuration unit 502 translates the target BDFs, i.e. it converts the virtual topology into the corresponding physical topology (for the downstream devices), and handles all additional tasks necessary to program the HW "hidden" from the OS/host/ system. That is why configuration packets are also redirected t configuration unit 502. ¶ 0062 - the PCie devices are configured by generating downstream configuration packets based on the actual bus topology and at least partially based on the intercepted configuration packets, and transmitting the downstream configuration packets to the PCie devices -See ¶ 0015 – See Also Fig.3-6);
However, Hearn does not explicitly teach
the first bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the first data element , the second bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the second data element
Ansari teaches
the first bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the first data element, the second bus controller to adjust a bus controller parameter defining at least one of a clock speed, slew rate, or drive strength prior to packetizing the second data element (¶ 0028 - Source domain 102 also includes bus controller circuitry 132 generally configured to exchange commands and data with a plurality of bus-connected devices 136. Bus controller circuitry 132 may comply or be compatible with the bus communications protocol, for example the aforementioned USB bus communications protocol. The bus controller circuitry 132 may include bandwidth allocation logic 134 configured to allocate bandwidth among the plurality of bus-connected devices 136. Bandwidth allocation may include, for 10 example, establishing bandwidth parameters for each bus connected device 136, for example establishing a maximum data rate and/or clock speed for a given link, establishing a minimum data rate and/or clock speed for a given link, etc. Bandwidth allocation logic 134 may be configured to dynamically adjust bandwidth parameters for the bus connected devices 136 to enable, for example, excess bandwidth on one device to be allocated to another device. bus controller circuitry 132 may assign a maximum data rate and/or clock speed for the source tunneling bridge circuitry 108 to transmit commands and data to the sink domain 104. For example, a TU 125 that has eliminated, the unchanged data payload sections, may be much smaller than a TU 125 that includes the encrypted data payload section(s), and a maximum data rate allocated to bus tunneling encoding circuitry 124 may be based on the largest expected size of TU 125).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yim to include the teachings of Ansari. The motivation for doing so is to allow the system to allocate the unused bandwidth to other bus-connected devices. Thus, significant efficiency of bus controller circuitry may be achieved. (Ansari – ¶ 0028).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hearn in view of Ansari further in view of Yim
Regarding claim 19,
Hearn does not explicitly teach
wherein the unified adapter layer is to decode the first host data packet to generate a third data element defining a bus controller parameter setting and the first bus controller is to adjust a bus controller parameter in accordance with the bus controller parameter setting
However, Yim teaches
wherein the unified adapter layer is to decode the first host data packet to generate a third data element defining a bus controller parameter setting and the first bus controller is to adjust a bus controller parameter in accordance with the bus controller parameter setting(Fig.2, ¶ 0008 -The control unit 40 receives the command information CMD IF and recognizes this information as a command for setting the data bus width. Furthermore, the control unit 40 receives the data bus width information BUS IF and stores it at a first register 50. Thereafter, the control unit 40 transmits and receives data by selecting all or some of the plurality of data lines 20, based on the data bus width information BUS_IF. Moreover, the command field decoder 32 outputs a write or a read command by decoding the command field CMD FD when transmitting and receiving general data. The argument field decoder 33 outputs an address signal by decoding the argument field AR FD when transmitting and receiving the general data).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hearn to include the teachings of Yim. The motivation for doing so is to allow system to not require the data bus width to be set in advance and enabling free adjustment of the data bus width, if necessary (Abstract – Yim).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hearn in view of Ansari further in view of Niner et al. Publication No. US 2013/0104231 A1 ( Niner hereinafter).
Regarding claim 20,
Hearn does not explicitly teach
wherein the system comprises an automotive packet- based network transport system.
Niner teaches
system comprises an automotive packet- based network transport system (¶ 0006 - The method includes monitoring, by an electronic control unit, data packets on a bus in the automotive network).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hearn to include the teachings of Niner. The motivation for doing so is to allow system to enable seamless communication between various vehicle components, leading to improved safety, performance optimization, efficiency, and advanced features like driver assistance systems.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YOUNES NAJI/Primary Examiner, Art Unit 2445