DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed March 11th, 2026. Claims 1, 3-6, 10, 12-15, 19 are pending, of which claims 1, 3-6, 10, 12-15, 19 are currently rejected. Claims 2 and 11 have been cancelled by Applicant.
Response to Arguments
The amendment filed March 11th, 2026 has been entered. Claims 1, 3-6, 10, 12-15, 19 remain pending in the application.
Prior Art Rejections
Arguments have been fully considered and are not persuasive.
Applicant alleges that there is no dimension in Mobin et al. (6532273) (hereinafter “Mobin”), stating that a communication signal does not have dimensions (Applicant Remarks: Pg. 7). Examiner disagrees. As stated in Col. 3 Lines 7-20 of Mobin, the half decimation occurs on a quadrature signal which, as is known by a person of ordinary skill in the art, is two-dimensional. So, the ½ rate decimation of the quadrature signal in Mobin must be in a half dimension. Hence, Mobin does in fact disclose decimation by half a dimension.
Applicant also alleges that Cai (WO2020168508) (hereinafter “Cai”) is silent as to the exact structure of the hardware logic, pointing to how equations discussed earlier in the disclosure of Cai are not taken into consideration when describing the filters (Applicant Remarks: Pg. 7). Examiner respectfully disagrees. As can be seen in Cai (as attached to the Office Action mailed August 6th, 2025), Pgs. 4-5 describe the tap structure of the FIR filters with respect to tan(α), and this structure is further described in Pg. 6 of Cai with respect to the cascaded three-tap filters that would be dependent on the determine described in Pgs. 4-5 (with discussion of tan(α) and tap values). Therefore, Cai does in fact teach the exact structure of the hardware logic.
Applicant also points out how Cai has shift operations but also other mathematical operations, however Wendel et al. (6532483) (hereinafter “Wendel”) is relied upon for the multiplying by bit-shifting, not Cai.
Applicant alleges that there is no motivation to combine Mobin and Cai because the references are in different fields of endeavor. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, both Mobin and Cai are in the same field of FIR filtering. Thus, there would be motivation to combine the teachings with respect to the hardware aspect of FIR filter configuration. And additionally, as would be known to a person of ordinary skill in the art, increased adaptivity of hardware components while also remaining efficiency would be beneficial in wide array of circumstances.
Applicant alleges that there is no reason to combine Mobin, Cai, or Wendel because while Wendel relates to time division multiplexing, Mobin and Cai do not (Applicant Remarks Pg. 8). However, the reason for combining the three references is because they are all related to digital filtering. Hence, there is a motivation to combine.
Applicant additionally alleges that Wendel does not teach bit-shifting for multiplication operations, stating how the Wendel teaches exploiting the fact that multiplications by powers of 2 can be achieved by adding j zeros to the right of the number to be multiplied. This is exactly what bit shifting is, and to a person of ordinary skill in the art it would make sense to have bit shifting occurring for multiplications because doing so would require less computational resources for multiplying, and more computational resources being applied to other areas of computation. As such, Wendel does in fact teach multiplying exclusively by bit shifting.
Applicant alleges the combination of Mobin, Cai, and Wendel would not have been made by a skilled person because the circuitry of Wendel is not just for any circuitry, but for circuitry involved in reserving a separate filter for each original data train, and thus states that Wendel would not have been considered for any improvement of Cai or Mobin. Examiner respectfully disagrees. As previously, all references are directed towards digital filtering, making them analogous. Additionally, the circuitry reduction improvement provided by Wendel is for “reserving a separate filter” i.e., digital filtering circuitry. Hence, the improvement of Wendel does make sense to be included with the combination of Mobin and Cai.
Applicant further alleges that the motivations to combine for Mobin and Cai with respect to the motivation to combine of Mobin, Cai, and Wendel are contradictory, stating that it would not make sense to have increased adaptability while reducing circuitry (Applicant Remarks: Pg. 9). Examiner respectfully disagrees. As discussed previously with respect to the re-allocating of computational resources, to a person with ordinary skill in the art it would make sense to have an increased adaptability for filtering while also reducing circuitry for multiplications as the usual multipliers typically found in filters (more specifically finite impulse response filters) may take a lot more computational resources than multiplication being carried out by bit-shifting instead. For that reason, Examiner respectfully disagrees in the motivations being contradictory.
With regards to Applicant’s statement of combinations being “improperly motivated by an attempt to reconstruct the claimed invention”, i.e., improper hindsight, in response to applicant’s argument that the examiner’s conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant’s disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971
New grounds of rejection have been made as necessitated by amendments. See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 10-11, and 13-15, are rejected under 35 U.S.C. 103 as being unpatentable over Mobin et al. (6532273) (hereinafter “Mobin”) in view of Cai et al. (WO 2020168508 A1) (hereinafter “Cai”), in view of Wendel et al. (6532483) (hereinafter “Wendel”).
Regarding claim 1, Mobin teaches:
hardware logic configured to downscale by a half in a dimension (Mobin: Col. 3 Lines 7-19 decimation by a series of FIR filters, the decimation factor by ½).
Mobin does not explicitly teach three tap FIR filters.
However, Cai teaches:
hardware logic implementing a first three-tap finite impulse response (FIR) filter in the dimension (Cai: Pg. 6 Lines 20-28 cascaded 3 tap filters are used in the case that more than 3 taps is needed, example provided with 5 taps needed and instead of using a 5 tap filter, 2 3 tap filters are used; Pg. 8 Lines 11-12 processing is done in one dimension whether horizontal or vertical, the mode of horizontal or vertical being chosen prior to the actual processing), and
hardware logic implementing a second three-tap FIR filter in the dimension (Cai: Pg. 6 Lines 20-28 cascaded 3 tap filters are used in the case that more than 3 taps is needed, example provided with 5 taps needed and instead of using a 5 tap filter, 2 3 tap filters are used; Pg. 8 Lines 11-12 processing is done in one dimension whether horizontal or vertical, the mode of horizontal or vertical being chosen prior to the actual processing);
wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter (Cai: Pg. 6 Lines 20-28 cascaded 3 tap filters, output of one filter is input of the next).
In combining, Mobin with Cai, the FIR filters of Mobin would be followed by the FIR filters of Cai, thus this combination would have hardware logic comprising logic for decimation by a half as well as hardware logic implementing a first and second three-tap FIR filter.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the hardware logic for implementing three-tap filters as taught by Cai with the hardware logic for decimation by half as taught by Mobin both teachings are directed towards FIR filtering processing. One with ordinary skill in the art would be motivated to combine the teachings because doing so would allow for a more adaptive filtering scheme (Cai: Abstract).
Mobin in view of Cai does not explicitly teach multiplication by bit-shifting only.
However, Wendel teaches:
wherein each three-tap filter is implemented to perform its constituent multiplications using only bit shift operations (Wendel: Col. 7 Lines 65-67 multiplication by shifting).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the multiplying by solely bit shifting as taught by Wendel with the hardware downscaler as taught by Mobin in view of Cai as all teachings are directed towards FIR filtering processing. The improvement of Wendel lies in reducing the expense for circuitry (Wendel: Col. 1 Line 61).
Therefore, Mobin in view of Cai in view of Wendel teaches:
A hardware downscaler, for downscaling by a half in a dimension, the downscaler comprising:
hardware logic configured to downscale by a half in a dimension, the hardware logic comprising:
hardware logic implementing a first three-tap finite impulse response (FIR) filter in the dimension and hardware logic implementing a second three-tap FIR filter in the dimension;
wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter; and
wherein each three-tap filter is implemented to perform its constituent multiplications using only bit shift operations.
Regarding claim 4, Mobin in view of Cai in view of Wendel teaches:
The hardware downscaler of claim 1, wherein each three-tap filter is implemented with filter coefficients ¼, ½, ¼ (Cai: Pg. 4 Lines 40-41 each sub-filter has coefficients 1/4, 1/2, ¼).
Regarding claim 5, Mobin in view of Cai in view of Wendel teaches:
The hardware downscaler of claim 1, wherein the hardware logic configured to downscale by a half in a dimension further comprises hardware logic for implementing a decimation (Mobin: Col. 3 Lines 7-19 decimation by FIR filtering, the decimation factor by ½).
The motivation to combine with respect to claim 1 applies equally to claim 5.
Regarding claim 6, Mobin in view of Cai in view of Wendel teaches:
The hardware downscaler of claim 5, wherein the hardware logic for implementing the decimation is integrated with the hardware logic implementing the second three-tap FIR filter (Mobin: Col. 3 Lines 7-19 decimation by FIR filtering, the decimation factor by ½, each filter including the second filter i.e., hardware logic for implementing the second three-tap FIR filter would perform decimation by ½).
In having the combination of Mobin in view of Cai in view of Wendel, the hardware logic implementing a decimation by a half is followed by the hardware logic implementing the second three-tap filter, and thus the hardware logic for implementing a decimation is integrated with the hardware logic implementing the second three-tap filter.
The motivation to combine with respect to claim 1 applies equally to claim 6.
Mobin in view of Cai in view of Wendel therefore teaches:
The hardware downscaler of claim 5, wherein the hardware logic for implementing the decimation is integrated with the hardware logic implementing the second three-tap FIR filter.
Claims 10-11 and 13-15 recite the computer implemented method practiced by the hardware downscaler of claims 1-2 and 4-6 respectively and are therefore rejected for the same reasons therein.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mobin in view of Cai in view of Wendel further in view of Benvenuto et al. (“On the Design of FIR Filters with Powers-of-Two Coefficients”) (hereinafter “Benvenuto”).
Regarding claim 3, while Mobin in view of Cai in view of Wendel teaches the hardware downscaler of claim 1 as well as the three-tap filters (Cai: Pg. 6 Lines 20-28 cascaded 3 tap filters), Mobin in view of Cai in view of Wendel does not explicitly teach the filter coefficients being integer powers of 2.
However, Benvenuto teaches:
wherein each three-tap filter is implemented with filter coefficients that are integer powers of 2 (Benvenuto: Page 1299 Col. 2 Lines 19-20 “Moreover, the tap factors of the transversal filter [the FIR filter] d(n) are restricted to assume values in the set…”; Equation (1) Ab = {±2b, ±2b-1, …, ±1, 0}; Page 1304 Table II Integer values for b).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the integer powers of two for filter coefficients as taught by Benvenuto with the hardware downscaler as taught by Mobin in view of Cai in view of Wendel as all teachings are directed towards FIR filtering processing. One with ordinary skill in the art would be motivated to combine the teachings to allow for a reduction in the complexity of the multipliers (Benvenuto: Page 1299 Col. 1 Introduction Line 30) in the filters.
Claim 12 recites the computer implemented method practiced by the hardware downscaler of claim 3 and is therefore rejected for the same reasons therein.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mobin in view of Cai in view of Wendel further in view of Howson et al. (US 2020/0380755 A1) (hereinafter “Howson”).
While Mobin in view of Cai in view of Wendel teaches the hardware downscaler as set forth in claim 1, Mobin in view of Cai in view of Wendel does not explicitly teach a non-transitory computer readable storage medium having a dataset description of the downscaler which causes an integrated circuit manufacturing system to manufacture an integrated circuit embodying the downscaler.
However, Howson teaches:
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description (Howson: ¶ 0065 a non-transitory computer readable medium that stores an integrated circuit dataset description)
that when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit (Howson: ¶ 0066 a layout processing system processes the integrated circuit description and generates a circuit layout).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the computer readable dataset description and integrated circuit manufacturing system as taught by Howson with the hardware downscaler as taught by Mobin in view of Cai as all teachings are directed towards filtering. The improvement of Howson lies in that performance improvements can be traded-off against the physical implementation, thereby improving the method of manufacture (Howson: ¶ 0198).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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