DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/26/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
● Claim 26 recites “wherein the first solder ball is directly attached to the bump of one of the two semiconductor dies via a solder-free connection”. It is unclear because on one hand, it claims that the first “solder ball” is attached to the bump of one of the two semiconductor dies, and on the other hand, it claims that the attachment is “a solder-free” connection. In the other words, how can the attachment to the bump of one of the two semiconductor dies be considered as “a solder-free” connection when the bump is attached by a “solder ball”?
For the examination purpose, it is assumed that the first solder ball is directly attached to the bump of one of the two semiconductor dies via a solder connection.
● Claim 27 recites “wherein the first solder ball is directly attached to the bump of one of the two semiconductor dies via a solder-free connection”. It is unclear because of the same reasons as discussed above.
● Claim 28 recites “wherein the first solder ball is directly attached to the bump of one of the two semiconductor dies via a solder-free connection”. It is unclear because of the same reasons as discussed above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 8, 10, 22, 25-26 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih et al (US 2020/0075546).
Regarding claim 1, Shih (Fig. 5G) discloses a semiconductor device, comprising: two semiconductor dies 120C/120D ([0042]); a redistribution layer (230, 510, 600); a bridge die 400 ([0028]) located vertically below the two semiconductor dies and within the redistribution layer; the bridge die 400 comprising a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) and electrically coupled to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies; a dielectric material 510 (i.e., “insulating encapsulant”, [0053]) in direct contact with and surrounding the bridge die 400 within the redistribution layer; and a connection (250, 240) comprising a metal (i.e., copper, [0045] and [0017]) and located external to the ball grid array, the connection passing through the redistribution layer and electrically coupled to one or more of the two semiconductor dies via a solder-free connection (i.e., connection metal electrical coupled to dies by penetrating through dielectric layer 230).
Regarding claims 6, 8 and 10, Shih (Fig. 5G) further discloses: a passivation layer 430 ([0047]) between the two semiconductor dies 120C/120D and the bridge die 400; the redistribution layer comprises redistribution circuit traces 604 (labeled in Fig. 1P); and the bridge die 400 is arranged in a bridge die layer 510 and the connection 250 passes through the bridge die layer with a copper pillar ([0045]).
Regarding claim 22, Shih (Fig. 5G) discloses a semiconductor device, comprising: two semiconductor dies 120C/120D; a dielectric layer 510 (i.e., “insulating encapsulant”, [0053]) below the two semiconductor dies; a bridge die 400 ([0028]) within the dielectric layer, the bridge die 400 having a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) on a top side, the bridge die 400 electrically coupled to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies; a conductor layer 600 (i.e., “a redistribution structure”, [0032]) below the dielectric layer 510; and a connection (240, 250, and 606 within layer 600) located external to the bridge die 400, the connection comprising a metal (i.e., copper, [0045], [0032] and [0017]) and passing orthogonally through the conductor layer 600 and the dielectric layer 510, the connection electrically coupled to one of the two semiconductor dies via a solder-free connection (i.e., connection metal electrical coupled to dies by penetrating through dielectric layer 230).
Regarding claims 25-26 and 28, Shih (Fig. 5G) further discloses: a passivation layer 230 ([0044]) between the two semiconductor dies and the ball grid array of the bridge die 400; and the first solder ball 420 (labeled in Fig. 5D) is directly attached to the bump 128 of one of the two semiconductor dies via a solder connection (as assumed in 112-2nd rejection above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 21 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al (US 2020/0075546) in view of Ecton et al (US 2019/0304912).
Regarding claim 11, Shih (Fig. 5G) discloses a system, comprising: a semiconductor device comprising: two semiconductor dies 120C/120D arranged on a first plane, wherein at least one of the two semiconductor dies includes a processor (corresponding to dies 110C/110D in Fig. 4B, [0014]) ; a redistribution layer (230, 510, 600) under the first plane; an interconnect bridge 400 in the redistribution layer, the interconnect bridge 400 having a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) on a top side, the interconnect bridge 400 electrically coupled at the top side to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies; a connection (240, 250) comprising a metal (i.e., copper, [0045] and [0017]), the connection passing through the redistribution layer and electrically coupled to one or more of the two semiconductor dies via a solder-free connection (i.e., connection metal electrical coupled to dies by penetrating through dielectric layer 230).
Shih does not disclose the semiconductor device is attached to a motherboard.
However, Ecton (Fig. 5) teaches a system comprising a semiconductor device is attached to a motherboard 502 ([0062]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the semiconductor device of Shih to a mother board in order to provide the electrical communications between the semiconductor device and other electronic components formed on the mother board, according to the requirements of the system design.
Regarding claim 21, Ecton (Fig. 5) further teaches a storage medium i.e., MEMORY, DRAM, ROM), and a bus electrically coupled between the processor 504 and the storage medium (i.e., interconnected using a mother board, [0067]) in a computing system.
Regarding claim 27, Shih (Fig. 5G) further discloses the first solder ball 420 (labeled in Fig. 5D) is directly attached to the bump 128 of one of the two semiconductor dies via a solder connection (as assumed in 112-2nd rejection above).
Claims 1-6, 8-10, 22-26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 2021/0118758) in view of Shih et al (US 2020/0075546).
Regarding claim 1, Cheng (Fig. 3F) discloses a semiconductor device, comprising: two semiconductor dies 110/120 ([0017]); a redistribution layer (140, 190); a bridge die 150 ([0022]) located vertically below the two semiconductor dies and within the redistribution layer; the bridge die 150 comprising a ball grid array 159 (labeled in Fig. 3A and [0060]) and electrically coupled to the two semiconductor dies 110/120 via a first solder ball 159 ([0060]) of the ball grid array attached to a bump 114 (labeled in Fig. 1B) of one of the two semiconductor dies; a dielectric material 180 ([0031]) in direct contact with and surrounding the bridge die 150 within the redistribution layer; and a connection 144 comprising a metal (i.e., copper, [0019]) and located external to the ball grid array, the connection 144 passing through the redistribution layer and electrically coupled to one or more of the two semiconductor dies 110/120 via a solder-free connection (i.e., connection metal 144 electrical coupled to dies by penetrating through dielectric layer 142, also see Fig. 1B).
Cheng does not disclose the first solder ball 159 of the ball grid array directly attached to the bump 114 of one of the two semiconductor dies.
However, Shih (Fig. 5G) teaches a semiconductor device comprising: a bridge die 400 ([0028]) located vertically below the two semiconductor dies and within the redistribution layer; the bridge die 400 comprising a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) and electrically coupled to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng by attaching the first solder ball of the ball grid array directly to the bump of one of the two semiconductor dies because such modification would provide a short contact path between the bridge die and the semiconductor dies, according to the requirements of conductivities which are desired for the contact paths between the bridge die and the semiconductor dies.
Regarding claims 2-6, 8 and 10, Cheng (Fig. 3F) further discloses: the connection 144 (including vias) tapers from a first dimension distal from the two semiconductor dies to a second, smaller dimension at a location more proximal to the two semiconductor dies; a vertical interconnect 194a (including vias) coupled to the bridge die 150 through the redistribution layer, wherein the vertical interconnect 194a tapers from a first dimension distal from the bridge die to a second, smaller dimension more proximal to the bridge die; the redistribution layer comprises a conductor layer 190 (i.e., redistribution layer, [0032]) and a dielectric layer 192 adjacent to the bridge die; the vertical interconnect 194a tapers from the first dimension to the second, smaller dimension as the vertical interconnect passes through the conductor layer and tapers from the first dimension to the second, smaller dimension as the vertical interconnect passes through the dielectric layer 192; a passivation layer 126 (labeled in Fig. 1A, [0016]) between the two semiconductor dies and the bridge die; and the redistribution layer comprises redistribution circuit traces 194a (corresponding to wide top portion 194a); and the bridge die 150 is arranged in a bridge die layer and the connection (144, CF) passes through the bridge die layer with a copper pillar CF ([0021]).
Regarding claim 9, Cheng does not disclose the semiconductor device further comprising a third semiconductor die and a second connection comprising the metal, the second connection passing through the redistribution layer and electrically coupled to the third semiconductor die via a solder-free connection.
However, as discussed above, Cheng (Fig. 3F) discloses the connection 144 comprising a metal (i.e., copper, [0019]), the connection 144 passing through the redistribution layer and electrically coupled to one or more of the two semiconductor dies 110/120 via a solder-free connection. Cheng further discloses number of dies to be packed may be varied depending upon the design requirements ([0017]). Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a third semiconductor die and a second connection having configurations similar to the first connection because number of dies and connections could be varied depending upon the requirements of the circuit design.
Regarding claim 22, Cheng (Fig. 3F) discloses a semiconductor device, comprising: two semiconductor dies 110/120; a dielectric layer 180 ([0031]) below the two semiconductor dies; a bridge die 150 ([0022]) within the dielectric layer, the bridge die 150 having a ball grid array 159 (labeled in Fig. 3A and [0060]) on a top side, the bridge die 150 electrically coupled to the two semiconductor dies via a first solder ball 159 ([0060]) of the ball grid array attached to a bump 114 (labeled in Fig. 1B) of one of the two semiconductor dies; a conductor layer 190 (i.e., redistribution layer, [0032]) below the dielectric layer 180; a connection (144, CF, 194) located external to the bridge die, the connection comprising a metal ([0021] and [0032]) and passing orthogonally through the conductor layer and the dielectric layer, the connection (144, CF, 194) electrically coupled to one of the two semiconductor dies via a solder-free connection (i.e., connection metal portion 144 electrical coupled to dies by penetrating through dielectric layer 142, also see Fig. 1B).
Cheng does not disclose the first solder ball 159 of the ball grid array directly attached to the bump 114 of one of the two semiconductor dies.
However, Shih (Fig. 5G) teaches a semiconductor device comprising: a bridge die 400 ([0028]) located vertically below the two semiconductor dies and within the redistribution layer; the bridge die 400 comprising a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) and electrically coupled to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng by attaching the first solder ball of the ball grid array directly to the bump of one of the two semiconductor dies because such modification would provide a short contact path between the bridge die and the semiconductor dies, according to the requirements of conductivities which are desired for the contact paths between the bridge die and the semiconductor dies.
Regarding claims 23-25, Cheng (Fig. 3F) further discloses: the connection (i.e., portion 144 including vias) tapers from a first dimension distal from the two semiconductor dies to a second, smaller dimension at a location more proximal to the two semiconductor dies; an interconnect 194a (including vias) electrically coupled to the bridge die 150 through the dielectric layer 192 and the conductor layer 190, wherein the interconnect 194a tapers from a first dimension distal from the bridge die to a second, smaller dimension more proximal to the bridge die; and a passivation layer 126 (labeled in Fig. 1A, [0016]) between the two semiconductor dies and the ball grid array of the bridge die.
Regarding claims 26 and 28, Shih (Fig. 5G) further teaches the first solder ball 420 (labeled in Fig. 5D) is directly attached to the bump 128 of one of the two semiconductor dies via a solder connection (as assumed in 112-2nd rejection above).
Claims 11-15, 21 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 2021/0118758) in view of Shih et al (US 2020/0075546) and Ecton et al (US 2019/0304912).
Regarding claim 11, Cheng (Fig. 3F) discloses a system, comprising: a semiconductor device comprising: two semiconductor dies 110/120 arranged on a first plane, wherein at least one of the two semiconductor dies includes a processor ([0017]); a redistribution layer (140, 180, 190) under the first plane; an interconnect bridge 150 in the redistribution layer, the interconnect bridge 150 having a ball grid array 159 (labeled in Fig. 3A and [0060]) on a top side, the interconnect bridge 150 electrically coupled at the top side to the two semiconductor dies via a first solder ball 159 ([0060]) of the ball grid array attached to a bump 114 (labeled in Fig. 1B) of one of the two semiconductor dies; a connection 144 (including vias) comprising a metal , (i.e., copper, [0019]) the connection 144 passing through the redistribution layer and electrically coupled to one or more of the two semiconductor dies 110/120 via a solder-free connection (i.e., connection metal portion 144 electrical coupled to dies by penetrating through dielectric layer 142, also see Fig. 1B).
Cheng does not disclose the first solder ball 159 of the ball grid array directly attached to the bump 114 of one of the two semiconductor dies.
However, Shih (Fig. 5G) teaches a semiconductor device comprising: a bridge die 400 ([0028]) located vertically below the two semiconductor dies and within the redistribution layer; the bridge die 400 comprising a ball grid array 420 (labeled in Fig. 5D, also see [0028], “solder bumps”) and electrically coupled to the two semiconductor dies via a first solder ball 420 of the ball grid array directly attached to a bump 128 of one of the two semiconductor dies. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng by attaching the first solder ball of the ball grid array directly to the bump of one of the two semiconductor dies because such modification would provide a short contact path between the bridge die and the semiconductor dies, according to the requirements of conductivities which are desired for the contact paths between the bridge die and the semiconductor dies.
Neither Cheng nor Shih discloses the semiconductor device is attached to a motherboard.
However, Ecton (Fig. 5) teaches a system comprising a semiconductor device is attached to a motherboard 502 ([0062]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the semiconductor device of Cheng to a mother board in order to provide the electrical communications between the semiconductor device and other electronic components formed on the mother board, according to the requirements of the system design.
Regarding claims 12-15, Cheng (Fig. 3F) further discloses: a dielectric material 180 ([0031]) surrounding the interconnect bridge 150 within the redistribution layer, and wherein the connection 144 (including vias) is external to the ball grid array and tapers from a first dimension distal from the two semiconductor dies to a second, smaller dimension at a location more proximal to the two semiconductor dies; a vertical interconnect 194a (including vias) coupled to the interconnect bridge 150 through the redistribution layer, wherein the vertical interconnect 194a (including vias) tapers from a first dimension distal from the interconnect bridge to a second, smaller dimension more proximal to the interconnect bridge 150; the redistribution layer comprises a conductor layer 190 (i.e., redistribution layer, [0032]) and a dielectric layer 192; and the vertical interconnect 194a tapers from the first dimension to the second, smaller dimension as the vertical interconnect passes through the conductor layer 190 and tapers from the first dimension to the second, smaller dimension as the vertical interconnect passes through the dielectric layer 192.
Regarding claim 21, Ecton (Fig. 5) further teaches a storage medium i.e., MEMORY, DRAM, ROM), and a bus electrically coupled between the processor 504 and the storage medium (i.e., interconnected using a mother board, [0067]) in a computing system.
Regarding claim 27, Shih (Fig. 5G) further teaches the first solder ball 420 (labeled in Fig. 5D) is directly attached to the bump 128 of one of the two semiconductor dies via a solder connection (as assumed in 112-2nd rejection above).
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 11 and 22 have been considered but are moot because the new ground of rejection (i.e., new applied reference, new combinations) is applied in the current rejection.
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/PHAT X CAO/ Primary Examiner, Art Unit 2817