DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 has been entered. Claims 1-3, 5-10, 12-14, 16-17, and 19-25 are pending.
Drawings
The drawing objection noted in Final Rejection (mailed 3/2/2026) is withdrawn since the structure/limitation not shown in the figures as recited in claim 11 is canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8-10, 12, and 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino et al. (US 9,715,064 B1, herein “Gambino”) in view of Aleksov et al. (US 2020/0006235 A1, herein “Aleksov”) and Raj et al. (US 2013/0230272 A1, herein “Raj”).
Regarding claim 1, Gambino discloses an electronic package (100A in Fig. 1A), comprising:
a first layer (insulator layer 124, which may be a nitride layer or other dielectric materials such as oxide layers (Col. 4, line 57- Col. 5, line 8 ), wherein the first layer comprises glass (oxide layer with a lower refractive index than silicon is well-known in the art as silicon dioxide; chip 110 is formed on a silicon substrate with insulator layer such as a buried oxide (BOX) layer [Col. 4, lines 38-56]);
a second layer (dielectric layer 111 and 131) over the first layer (124),
a first photonic integrated circuit (chip 110 housing optical device 115 and light source 116) within the second layer (111/131);
a second PIC (chip 130 housing photodiode 135) within the second layer (111/131);
a waveguide (waveguide 127) in the first layer (124), wherein the waveguide optically couples to the first PIC (110) to the second PIC (130) via grating couplers (128/128’).
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Gambino does not disclose a second layer comprises a mold material nor does Gambino discloses a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side.
Aleksov teaches an electronic package comprising a first layer (package substrate 102), wherein the first layer comprises glass (Para [0036]); a second layer (molded material 127, Para [0026]) over the first layer (102). Aleksov further teaches first via (interconnect structure 1628, 1628a, and 1628b in Fig. 14) through multiple layers, and a second via continuous through multiple layers (interconnect structure 1628, 1628a, and 1628b in Fig. 14).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the package substrate wherein the layer is formed on glass substrate and the second layer is formed with molded material is for material benefits of glass and mold material. Glass is optical integration ready substrate possessing silicon matching thermal expansion coefficient, while mold material is thermal stable and extremely low-cost electronic packaging material. One would be motivated to form the waveguide on glass and the PIC chips in mold material to leverage the known material benefits of glass and leverage mature, high-volume mold material packaging and standard and optimized assembly flow.
Gambino in view of Aleksov do not teach a die over the second layer and vertically overlapping with the first PIC and the second PIC such that the first PIC are vertically intervening between the dies and the waveguide, wherein the die is electrically coupled to the first PIC and the second PIC.
Raj teaches a chip assembly configuration wherein a die (integrated circuit 218) over the second layer (substrate 210) and vertically overlapping with the first PIC (220-2 light source or photodiode, Para [0039]) and the second PIC (220-1 light source or photodiode, Para [0039]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention the integrated circuit (218) can be configured to overlap the PIC chips (integrated chip 110 and 130) in Gambino’s invention. The modified configuration would necessarily yield the first and second PIC (110 and 130 of Gambino) are vertically intervening between the die (integrated circuit 218 of Raj) and the waveguide (127 in Gambino), wherein the die is electrically coupled to the first PIC and second PIC (through the substrate 210 interconnects 216 of Raj). One motivation would be to provide small electrical connection between the integrated circuit which comprises of serializer-deserializer I/O is provided for both PIC chips which can reduce power requirements for I/O drivers (Raj, Para [0037]).
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Gambino in view of Aleksov and Raj do not explicitly teach the first via is laterally spaced apart from the first PIC and from the first side of the waveguide and the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side.
However, Gambino in view of Aleksov and Raj do not explicitly teach a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from a second side of the waveguide, the second side opposite the first side.
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Aleksov teaches through substrate vias (Fig. 14: 1628a, 1628b). Aleksov further teaches various interconnect structures such as interposer-to-package-substrate interconnects (128) have coarser pitch for lower density interconnects and die to interposer interconnects (120, 122) have finer pitch for higher density interconnects. Therefore, the placement of the first via and the second via laterally spaced apart from the first and second PIC and laterally spaced apart from the first and second side of the waveguide would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the placement of said vias is a design feature specific to the number of IC chips, PIC chips, and optical waveguides therein.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the through silicon vias of Gambino in view of Aleksov and Raj are electrically conductive vias that interconnect electrical signals to the various layers. The benefits of placing through substrate vias away from the PICs and the waveguide is to avoid optical-electrical interference and prevent metal absorption losses.
Claim 2. Gambino in view of Aleksov and Raj (herein “Gambino / Aleksov / Raj”) teach the invention of claim 1, and Gambino further teaches the first PIC (110) and the second PIC (130) are optically coupled to the waveguide by grating couplers (128, 128’).
Claim 8. Gambino / Aleksov / Raj teach the invention of claim 1, and Aleksov further teaches high bandwidth (HBW) interconnect (110) includes a waveguide, which is any linear structure that conveys electromagnetic waves between its endpoints; this includes optical waveguide. Furthermore, the HBW interconnected may be filled with a dielectric material, which would include glass the same material as substrate 102. Aleksov further discloses waveguide (110) has a different microstructure than the first layer such as rectangular block (Para [0028]).
Claims 9-10. Gambino / Aleksov / Raj teach the invention of claim 1, and Gambino further teaches the first PIC (110) and second PIC (130) are in contact with a top surface of the first layer (124) through active layer (114 of chip 110 and 134 of chip 130). Since light are coupled through the waveguides and gratings, as shown in Fig. 1, the examiner considers the first layer 124 and “in contact” with the active layers 114/134. Moreover, since the claims 9-10, dependent on claim 1 which recites—comprising—the examiner considers other intervening layers may be included within the contacted layers.
Claim 12. Gambino / Aleksov / Raj teach the invention of claim 1, and Aleksov further teaches the HBW waveguide (110) extends below the first PIC (120) and below the second PIC (125). See Aleksov Fig. 1.
Claim 23. Gambino discloses an electronic system, comprising:
a first layer (insulator layer 124, which may be a nitride layer or other dielectric materials such as oxide layers (Col. 4, line 57- Col. 5, line 8 ), wherein the first layer comprises glass (oxide layer with a lower refractive index than silicon is well-known in the art as silicon dioxide; chip 110 is formed on a silicon substrate with insulator layer such as a buried oxide (BOX) layer [Col. 4, lines 38-56]);
a second layer (dielectric layer 111 and 131) over the first layer (124),
a first photonic integrated circuit (chip 110 housing optical device 115 and light source 116) within the second layer (111/131);
a second PIC (chip 130 housing photodiode 135) within the second layer (111/131);
a waveguide (waveguide 127) in the first layer (124), wherein the waveguide optically couples to the first PIC (116) to the second PIC (135) via grating couplers (128/128’).
Gambino does not disclose a second layer comprises a mold material nor does Gambino discloses a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side. Gambino also does not disclose a board, a package substrate coupled to the board; and a patch coupled to the package substrate.
Aleksov teaches an electronic system (Fig. 15) comprising a board (1702); a package substrate (IC package 1724) coupled to the board (1702); a patch (1700) coupled to the package substrate (1724) via electrical interconnections on board (1702) wherein the patch (1700) may include any of the microelectronic assemblies 100 (Para [0075]). Patch (1700) with board (1702) has an IC package (1726) coupled thereon (Fig. 15)
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Aleksov further teaches an electronic package included in the patch comprising a first layer (package substrate 102), wherein the first layer comprises glass (Para [0036]); a second layer (molded material 127, Para [0026]) over the first layer (102). Aleksov further teaches first via (interconnect structure 1628, 1628a, and 1628b in Fig. 14) through multiple layers, and a second via continuous through multiple layers (interconnect structure 1628, 1628a, and 1628b in Fig. 14).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the package substrate wherein the layer is formed on glass substrate and the second layer is formed with molded material is for material benefits of glass and mold material. Glass is optical integration ready substrate possessing silicon matching thermal expansion coefficient, while mold material is thermal stable and extremely low-cost electronic packaging material. One would be motivated to form the waveguide on glass and the PIC chips in mold material to leverage the known material benefits of glass and leverage mature, high-volume mold material packaging and standard and optimized assembly flow. Moreover, Aleksov teaches the electronic system in Fig. 15 wherein the architecture of the patch allows the electronic system to be further integrated on both substrates of the board 1702. One motivation would be to increase the electronic system density since the miniaturization of the integrated photonic integrated circuits embedded within the molding material (cavity) allows for more chip integration without additional height penalty.
Gambino in view of Aleksov do not teach a die over the second layer and vertically overlapping with the first PIC and the second PIC such that the first PIC are vertically intervening between the dies and the waveguide, wherein the die is electrically coupled to the first PIC and the second PIC.
Raj teaches a chip assembly configuration wherein a die (integrated circuit 218) over the second layer (substrate 210) and vertically overlapping with the first PIC (220-2 light source or photodiode, Para [0039]) and the second PIC (220-1 light source or photodiode, Para [0039]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention the integrated circuit (218) can be configured to overlap the PIC chips (integrated chip 110 and 130) in Gambino’s invention. The modified configuration would necessarily yield the first and second PIC (110 and 130 of Gambino) are vertically intervening between the die (integrated circuit 218 of Raj) and the waveguide (127 in Gambino), wherein the die is electrically coupled to the first PIC and second PIC (through the substrate 210 interconnects 216 of Raj). One motivation would be to provide small electrical connection between the integrated circuit which comprises of serializer-deserializer I/O is provided for both PIC chips which can reduce power requirements for I/O drivers (Raj, Para [0037]).
Gambino in view of Aleksov and Raj do not explicitly teach the first via is laterally spaced apart from the first PIC and from the first side of the waveguide and the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side.
However, Gambino in view of Aleksov and Raj do not explicitly teach a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from a second side of the waveguide, the second side opposite the first side.
Aleksov teaches through substrate vias (Fig. 14: 1628a, 1628b). Aleksov further teaches various interconnect structures such as interposer-to-package-substrate interconnects (128) have coarser pitch for lower density interconnects and die to interposer interconnects (120, 122) have finer pitch for higher density interconnects. Therefore, the placement of the first via and the second via laterally spaced apart from the first and second PIC and laterally spaced apart from the first and second side of the waveguide would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the placement of said vias is a design feature specific to the number of IC chips, PIC chips, and optical waveguides therein.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the through silicon vias of Gambino in view of Aleksov and Raj are electrically conductive vias that interconnect electrical signals to the various layers. The benefits of placing through substrate vias away from the PICs and the waveguide is to avoid optical-electrical interference and prevent metal absorption losses.
Regarding claim 25, Gambino / Aleksov / Raj teach the invention of claim 23, and Aleksov further teach the waveguide comprises the same material as the first layer (glass, silicon dioxide as a constituent of a buried oxide layer), wherein the waveguide has a different microstructure than the first layer (Para [0028]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gambino / Aleksov / Raj as applied to claim 1 above, and further in view of Fish (US 2013/0230274 A1, herein “Fish”).
Gambino / Aleksov / Raj teach the invention of claim 1, but Gambino / Aleksov / Raj
Do not teach the first PIC and the second PIC are optically coupled to the waveguide by evanescent couplers.
Fish teaches coupling between photonic interconnect (300, 500) and photonic layer (302, 502) using evanescent coupling (Figs. 3A-3C).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the coupling technique of Fish would apply to the planar photonics integrated circuits of Gambino / Aleksov / Raj. One would be motivated to use evanescent coupler to minimize insertion loss and evanescent coupling is compatible in pact integration of multi-chip packaging.
Claim 5, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino / Aleksov / Raj as applied to claim 1 above, and further in view of Wang et al. (US 10,162,139 B1, herein “Wang”).
Regarding claim 5, Gambino / Aleksov / Raj teach the invention of claim 1, but Gambino / Aleksov / Raj do not teach a second die over the second layer, wherein the second die is coupled to the first PIC and a third die over the second layer, wherein the third die is coupled to the second PIC.
Wang teaches a chip package wherein a die (190) is over the second layer (molding compound 162) via redistribution structure (150), wherein the first die is electrically coupled to the PIC (130) by way of through interlayer via (TIV 148). Wang further teaches a second die (laser die 200) over the second layer (molding compound 162) via redistribution structure (150), wherein the second die is electrically coupled to the PIC (130) by way of through redistribution structure (150) and interlayer via (TIV 148).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the chip package assembly of Gambino / Aleksov / Raj to increase IC chip density by configure the package in the same arrangement as taught by Wang. The additional IC chip would have design specific function added to the package or increase computing capacity to the integrated package. One would be motivated to stack EIC over the second layer and electrically coupled it to the first and second PIC to shorten the electrical connection between the driver circuit 190 (Col. 5, lines 24-41) and the PIC chips, thus condensing the package size and increase the density of the chip assembly.
However, Wang does not teach a third die over the second layer, wherein the third die is coupled to the second PIC.
It would have been obvious to one of ordinary skill in the art at the time of filing to provide corresponding dies to drive the first and second PIC and provide laser die and photodiode die for the functioning of the first and second PICs per design specifications, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Claims 19 and 22. Gambino discloses a method of forming an electronic package, comprising:
forming the first layer comprises glass layer (chip 120 with insulator layer 124, which may be a nitride layer or other dielectric materials such as oxide layers (Col. 4, line 39- Col. 5, line 8 ), wherein the first layer comprises glass (oxide layer with a lower refractive index than silicon is well-known in the art as silicon dioxide; chip 110 is formed on a silicon substrate with insulator layer such as a buried oxide (BOX) layer [Col. 4, lines 38-56]);
attaching a plurality of photonics integrated circuits (PICS) to the first layer (chip 110, 130) to the first layer (chip 120);
disposing a second layer over the first layer and the plurality of PICS;
forming optical waveguides in the first layer (122, 127), wherein the optical waveguides optically couple the PICs together (via grating couplers 123, 128, 128’).
Gambino does not disclose a second layer is a mold material nor does Gambino discloses forming a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and forming a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from a second side of the waveguide, the second side opposite the first side.
Aleksov teaches an electronic package comprising a first layer (package substrate 102), wherein the first layer comprises glass (Para [0036]); a second layer (molded material 127, Para [0026]) disposed over the first layer (102). Aleksov further teaches forming first via (interconnect structure 1628, 1628a, 1628b in Fig. 14) through multiple layers, and forming a second via continuous through multiple layers (interconnect structure 1628, 1628a, 1628b in Fig. 14).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the package substrate wherein the layer is formed on glass substrate and the second layer is formed with molded material is for material benefits of glass and mold material. Glass is optical integration ready substrate possessing silicon matching thermal expansion coefficient, while mold material is thermal stable and extremely low-cost electronic packaging material. One would be motivated to form the waveguide on glass and the PIC chips in mold material to leverage the known material benefits of glass and leverage mature, high-volume mold material packaging and standard and optimized assembly flow.
Gambino in view of Aleksov do not teach disposing dies over the second layer, wherein one of the dies is over the second layer and vertically overlapping with a first PIC and a second PIC of the plurality of PICs.
Raj teaches a chip assembly configuration wherein a die (integrated circuit 218) is disposed over the second layer (substrate 210) and vertically overlapping with the first PIC (220-2 light source or photodiode, Para [0039]) and the second PIC (220-1 light source or photodiode, Para [0039]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention the integrated circuit (218) can be configured to overlap the PIC chips (integrated chip 110 and 130) in Gambino’s invention. The modified configuration would necessarily yield the first and second PIC (110 and 130 of Gambino) are vertically intervening between the die (integrated circuit 218 of Raj) and the waveguide (127 in Gambino), wherein the die is electrically coupled to the first PIC and second PIC (through the substrate 210 interconnects 216 of Raj). One motivation would be to provide small electrical connection between the integrated circuit which comprises of serializer-deserializer I/O is provided for both PIC chips which can reduce power requirements for I/O drivers (Raj, Para [0037]).
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Gambino in view of Aleksov and Raj do not explicitly teach forming a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and forming a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from a second side of the waveguide, the second side opposite the first side.
Aleksov teaches through substrate vias (Fig. 14: 1628a, 1628b). Aleksov further teaches various interconnect structures such as interposer-to-package-substrate interconnects (128) have coarser pitch for lower density interconnects and die to interposer interconnects (120, 122) have finer pitch for higher density interconnects.
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Therefore, the placement of the first via and the second via laterally spaced apart from the first and second PIC and laterally spaced apart from the first and second side of the waveguide would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the placement of said vias is a design feature specific to the number of IC chips, PIC chips, and optical waveguides therein.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the through silicon vias of Gambino in view of Aleksov and Raj are electrically conductive vias that interconnect electrical signals to the various layers. The benefits of placing through substrate vias away from the PICs and the waveguide is to avoid optical-electrical interference and prevent metal absorption losses.
Gambino / Aleksov / Raj do not teach disposing dies over the second layer.
Wang teaches a chip package wherein a die (190) is over the second layer (molding compound 162) via redistribution structure (150), wherein the first die is electrically coupled to the PIC (130) by way of through interlayer via (TIV 148). Wang further teaches a second die (laser die 200) over the second layer (molding compound 162) via redistribution structure (150), wherein the second die is electrically coupled to the PIC (130) by way of through redistribution structure (150) and interlayer via (TIV 148).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the chip package assembly of Gambino / Aleksov / Raj to increase IC chip density by configure the package in the same arrangement as taught by Wang. The additional IC chip would have design specific function added to the package or increase computing capacity to the integrated package. One would be motivated to stack EIC over the second layer and electrically coupled it to the first and second PIC to shorten the electrical connection between the driver circuit 190 (Col. 5, lines 24-41) and the PIC chips, thus condensing the package size and increase the density of the chip assembly.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gambino / Aleksov / Raj view of Wang as applied to claim 5 above, and further in view of Charles et al. (US 2020/0166720 A1, herein “Charles”).
Gambino / Aleksov / Raj and further in view of Wang (herein “Gambino / Aleksov / Raj / Wang”) teach the invention of claim 5. Gambino / Aleksov / Raj / Wang do not teach a first via coupled to the second die, wherein the first via coupled to the second die; and a second via coupled to the third die.
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Charles teaches photonics optoelectrical system (Fig. 3) wherein via VXA is provided therein to extend through photonics dielectric stack (200), bond layer (4016), and interposer (220).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the stacked architecture of optoelectrical packages demand more electrical interconnections such that interlayers electrical vias of Charles would have been obvious to one having ordinary skill in the art to modify for providing electrical driving and powering signals to stacked EIC chips and PIC chips. One would be motivated to provide through multiple substrate vias to reduce manufacturing cost.
Claims 7, 13-14, 16-17, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino / Aleksov / Raj as applied to claim 1 and 23 above, and further in view Janta-Polczynski et al. (US 2020/0279840 A1, herein “Janta”).
Claim 7. Gambino / Aleksov / Raj teach the invention of claim 1, but Gambino / Aleksov / Raj do not teach the first PIC and second PIC extend into the first layer.
Janta teaches a photonics package wherein PIC die (130) is disposed within a cavity (503) (Fig. 5C). Janta further teaches the implementation of embodiment of Fig. 5C can be replicated to multiple PIC chips as shown in Fig. 6. It would have been obvious to one having ordinary skill in the art to recognize the teaching of Janta for setting the PIC chip into the first layer is for alignment with the optical components and interconnection with the electrical components (Para [0004]). One motivation for providing a cavity for the photonic chip is to design alignments and interconnections onto the substrate or redistribution layer which would simplify the placement of the photonic chips (Para [0004], [0032]).
Claim 13. Gambino discloses an electronic package (100A in Fig. 1A), comprising:
a first layer (insulator layer 124, which may be a nitride layer or other dielectric materials such as oxide layers (Col. 4, line 57- Col. 5, line 8 ), wherein the first layer comprises glass (oxide layer with a lower refractive index than silicon is well-known in the art as silicon dioxide; chip 110 is formed on a silicon substrate with insulator layer such as a buried oxide (BOX) layer [Col. 4, lines 38-56]);
a second layer (dielectric layer 111 and 131) over the first layer (124),
a first photonic integrated circuit (chip 110 housing optical device 115 and light source 116) within the second layer (111/131);
a second PIC (chip 130 housing photodiode 135) within the second layer (111/131);
a waveguide (waveguide 127) in the first layer (124), wherein the waveguide optically couples to the first PIC (110) to the second PIC (130) via grating couplers (128/128’).
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Gambino does not disclose a second layer comprises a mold material nor does Gambino discloses a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side.
Aleksov teaches an electronic package comprising a first layer (package substrate 102), wherein the first layer comprises glass (Para [0036]); a second layer (molded material 127, Para [0026]) over the first layer (102). Aleksov further teaches first via (interconnect structure 1628, 1628a, and 1628b in Fig. 14) through multiple layers, and a second via continuous through multiple layers (interconnect structure 1628, 1628a, and 1628b in Fig. 14).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the package substrate wherein the layer is formed on glass substrate and the second layer is formed with molded material is for material benefits of glass and mold material. Glass is optical integration ready substrate possessing silicon matching thermal expansion coefficient, while mold material is thermal stable and extremely low-cost electronic packaging material. One would be motivated to form the waveguide on glass and the PIC chips in mold material to leverage the known material benefits of glass and leverage mature, high-volume mold material packaging and standard and optimized assembly flow.
Gambino in view of Aleksov do not teach a die over the second layer and vertically overlapping with the first PIC and the second PIC such that the first PIC are vertically intervening between the dies and the waveguide, wherein the die is electrically coupled to the first PIC and the second PIC.
Raj teaches a chip assembly configuration wherein a die (integrated circuit 218) over the second layer (substrate 210) and vertically overlapping with the first PIC (220-2 light source or photodiode, Para [0039]) and the second PIC (220-1 light source or photodiode, Para [0039]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention the integrated circuit (218) can be configured to overlap the PIC chips (integrated chip 110 and 130) in Gambino’s invention. The modified configuration would necessarily yield the first and second PIC (110 and 130 of Gambino) are vertically intervening between the die (integrated circuit 218 of Raj) and the waveguide (127 in Gambino), wherein the die is electrically coupled to the first PIC and second PIC (through the substrate 210 interconnects 216 of Raj). One motivation would be to provide small electrical connection between the integrated circuit which comprises of serializer-deserializer I/O is provided for both PIC chips which can reduce power requirements for I/O drivers (Raj, Para [0037]).
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Gambino in view of Aleksov and Raj do not explicitly teach the first via is laterally spaced apart from the first PIC and from the first side of the waveguide and the second via laterally spaced apart from the second PIC and from the second side of the waveguide, the second side opposite the first side.
However, Gambino / Aleksov / Raj do not explicitly teach a first via continuous through the first layer and the second layer, the first via laterally spaced apart from the first PIC and from a first side of the waveguide; and a second via continuous through the first layer and the second layer, the second via laterally spaced apart from the second PIC and from a second side of the waveguide, the second side opposite the first side.
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Aleksov teaches through substrate vias (Fig. 14: 1628a, 1628b). Aleksov further teaches various interconnect structures such as interposer-to-package-substrate interconnects (128) have coarser pitch for lower density interconnects and die to interposer interconnects (120, 122) have finer pitch for higher density interconnects. Therefore, the placement of the first via and the second via laterally spaced apart from the first and second PIC and laterally spaced apart from the first and second side of the waveguide would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the placement of said vias is a design feature specific to the number of IC chips, PIC chips, and optical waveguides therein.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the through silicon vias of Gambino in view of Aleksov and Raj are electrically conductive vias that interconnect electrical signals to the various layers. The benefits of placing through substrate vias away from the PICs and the waveguide is to avoid optical-electrical interference and prevent metal absorption losses.
Gambino / Aleksov / Raj is silent to the first and second PIC embedded in the first layer, the second layer, or the first layer and the second layer.
Janta teaches a photonics package wherein PIC die (130) is disposed within a cavity (503) (Fig. 5C). Janta further teaches the implementation of embodiment of Fig. 5C can be replicated to multiple PIC chips as shown in Fig. 6. It would have been obvious to one having ordinary skill in the art to recognize the teaching of Janta for setting the PIC chip into the first layer is for alignment with the optical components and interconnection with the electrical components (Para [0004]) would be modifiable to the invention of Aleksov / Molzer / Kim. One would etch a cavity into the substrate with predetermined interconnections for receiving the PIC chip as shown in Janta’s disclosure. One motivation for providing a cavity for the photonic chip is to design alignments and interconnections onto the substrate or redistribution layer which would simplify the placement of the photonic chips (Para [0004], [0032]).
Claims 14. Gambino / Aleksov / Raj further in view of Janta (herein “Gambino / Aleksov / Raj / Janta”) teach the invention of claim 13 and further teach the active layer is at a bottom surface of the first and second PIC and the waveguide. Gambino / Aleksov / Raj / Janta do not explicitly teach the first PIC and the second PIC are in the first layer wherein an active layer of the first PIC is at a top surface of the first PIC, and wherein an active layer of the second PIC is at a top surface of the second PIC. However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because choosing the surface for the active layer to make electrical connections do not change the function and operation of the first and second PIC. The benefits of this modification include selecting the shortest interconnection path(s) to reduce resistance.
Claim 16. Gambino / Aleksov / Raj / Janta teach the invention of claim 13 and the combined teaching further teaches the first PIC (120) and the second PIC (125) are in the first layer (Janta: embedded in a cavity), wherein an active layer of the first PIC (120) is at a bottom surface of the first PIC and wherein an active layer of the second PIC is at a bottom surface of the second PIC (Gambino teaches an active layer or “device layer” 134 and 114 is at the bottom surface of the first and second PIC 110, 130).
Claim 17. Gambino / Aleksov / Raj / Janta teach the invention of claim 16 and Gambino further teaches the waveguide (Fig. 1A: 127) is embedded in the first layer (124).
Regarding claim 24, Gambino / Aleksov / Raj / teach the invention of claim 23, Gambino / Aleksov / Raj do not teach the first PIC and the second PIC extend into the first layer.
Janta teaches a photonics package wherein PIC die (130) is disposed within a cavity (503) (Fig. 5C). Janta further teaches the implementation of embodiment of Fig. 5C can be replicated to multiple PIC chips as shown in Fig. 6. It would have been obvious to one having ordinary skill in the art to recognize the teaching of Janta for setting the PIC chip into the first layer is for alignment with the optical components and interconnection with the electrical components (Para [0004]) would be modifiable to the invention of Aleksov / Molzer / Kim. One would etch a cavity into the substrate with predetermined interconnections for receiving the PIC chip as shown in Janta’s disclosure. One motivation for providing a cavity for the photonic chip is to design alignments and interconnections onto the substrate or redistribution layer which would simplify the placement of the photonic chips (Para [0004], [0032]).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino / Aleksov / Raj in view of Wang as applied to claim 19 above, and further in view of Patel et al. (US 2020/0049890 A1, herein “Patel”).
Gambino / Aleksov / Raj / Wang teach the invention of claim 19, but Gambino / Aleksov / Raj / Wang do not teach forming the optical waveguides comprises exposing the first layer to a laser to account for misplacement of the plurality of PICs.
Patel teaches imparting a waveguide pattern by exposing the laser to the glass substrate by modifying the refractive index of the patterned glass. (Para [0037]).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the method step of patterning waveguides using laser as taught by Patel would be implemented to form the waveguide in the invention of Aleksov / Molzer / Kim in view of Wang. One would be motivated to use laser for patterning the waveguide since laser is precise and adjustments to the placement of the patterns can be adapted to alignment changes of the optical elements.
As for the limitation—a process to account for misplacement of the plurality of PICs—the examiner considers Patel teaches the same process of patterning using laser as recited in claim 20, the intended limitation—to account for misplacement—would necessarily be met since the process of Patel is the same as the broadly recited method step.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-10, 12-14, 16-17, and 19-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liao et al. (US 2020/0091124 A1) discloses a photonic integrated package structure having through substrate vias. Yu et al. (US 2020/0003950 A1) discloses a photonic semiconductor package with photonic die mounted on the interposer wherein the interpose comprises through substrate vias.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
