DETAILED ACTION
This office action is in response to applicant’s amendment filed on November 7, 2025. Claims 1-14, 16-17, and 19-25 are under consideration.
Drawings
In applicant’s response filed on September 21, 2021, applicant did not remark on the drawing objection and applicant did not file Replacement Drawing(s). The drawings remain deficient in disclosing “vias through the first PIC and the second PIC.”
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “vias through the first PIC and the second PIC” of claim 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without disclosing the formation of “through substrate via through the first PIC and the second PIC, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). A PIC, photonic integrated circuit, comprises electrical circuits and photonic components integrated into a chip. The disclosure, Specification and Drawings, do not show an embodiment wherein a through substrate via is formed through the PIC showing how a via would avoid interferences with the internal circuitry of the PIC. The Specification discloses embodiments wherein vias are form through substrates connecting with active layer such as ball grid array or conductive pad. The Specification is silent to a via form through a PIC. For this reason, the examiner is unable to determine a searchable scope for “vias through the first PIC and the second PIC.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 9, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov et al. (US 2020/0006235 A1, herein “Aleksov”) in view of Molzer et al. (US 9,252,077 B2, herein “Molzer”) and Kim (US 2020/0200987 A1, herein “Kim”).
Regarding claim 1, Aleksov discloses an electronic package (Fig. 1), comprising:
a first layer (package substrate 102, Para [0036]), wherein the first layer comprises glass;
a second layer (molded material 127) over the first layer (102), wherein the second layer comprises a mold material (Para [0026]);
the mold material (127) is formed over chip interposers (132-1, 132-2) and chip packages (114-1 … 114-6),
a waveguide (waveguide 110) in the first layer, wherein the waveguide optically couples the first chip package (left package) to the second chip package (right package).
In a separate embodiment, Example 21, Aleksov discloses the interposer includes a through-silicon via, and the circuitry of the first interposer is coupled to the waveguide by the through-silicon via (Para [0117]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize the through-silicon via can be duplicated to such that each via can be coupled to each side of the waveguide. The motivation would be to access the optical signal at each end of the waveguide effectively functioning as input and output coupling node of the waveguide.
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Aleksov is silent to the through-silicon via (TSV) is formed through the first layer (glass) and the second layer (mold material).
Molzer teaches in Fig. 12 package vias wherein through-mold via (TMV 128) and through-silicon via (TSV 29) are formed through the mold material (Fig. 3A and 3B show in more details, see also Col. 3, line 55 to Col. 4, line 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify conventional vias with TSVs and TMVs to provide interconnect through different materials. One would be motivated to design multi-chip packages with plurality of TSVs and TMVs to reduce cross-talk and external perturbation. TMVs and TSVs can shorten the signal path between circuitry thus reducing the overall package size that includes the benefit of reduce cross-talk (Col. 2, line 62 – Col. 3, line 3).
Aleksov and Molzer are silent to the chip packages shown in Fig. 1 as photonics integrated circuit (PIC) chips.
Kim teaches co-packaging with silicon photonics hybrid planar lightwave circuit wherein substrate (105) supports the first PIC (120) and the second PIC (125) and a waveguide in the first layer, wherein the waveguide optically couples with the first PIC to the second PIC (Fig. 1a and 1b).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the chips (114-1…114-6) can be interchanged with the photonics integrated circuit chips (120, 125) as disclosed by Kim. Aleksov and Molzer disclose an embodiment of larger integrated module shown in Aleksov’s Fig. 16 wherein one of the integrated chip is a communication chip (1812) such that there are optical components (Para [0087]). Therefore, it would have been within the skills of an ordinary practitioner of the art to recognize replacing the electronic chips in Aleksov and Molzer with photonics integrated chips of Kim, wherein both platforms are provided with electrical and optical interconnections. The motivation for co-packaging of electronic integrated circuits and photonic integrated circuits is reducing or minimization of power consumption (Kim: Col. 2, lines 38-58).
Claim 8. Aleksov in view of Molzer and Kim (herein Aleksov / Molzer / Kim) disclose high bandwidth (HBW) interconnect (110) includes a waveguide, which is any linear structure that conveys electromagnetic waves between its endpoints; this includes optical waveguide. Furthermore, the HBW interconnected may be filled with a dielectric material, which would include glass the same material as substrate 102. Aleksov further discloses waveguide (110) has a different microstructure than the first layer such as rectangular block (Para [0028]).
Claims 9-10. Aleksov / Molzer / Kim teach the first PIC (120) and second PIC (125) are in contact with a top surface of the first layer (102) through active layer (124). See Aleksov Fig. 1.
Claim 12, Aleksov / Molzer / Kim teach the HBW waveguide (110) extends below the first PIC (120) and below the second PIC (125). See Aleksov Fig. 1.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov / Molzer / Kim as applied to claim 1 above, and further in view of Fish (US 2013/0230274 A1, herein “Fish”).
Aleksov / Molzer / Kim teach the invention of claim 1, but Aleksov / Molzer / Kim are silent to the PICs are optically coupled to the waveguide grating couplers or evanescent couplers.
Fish teaches coupling between photonic interconnect (300, 500) and photonic layer (302, 502) using evanescent coupling (Figs. 3A-3C) and in a separate embodiment Fish teaches coupling using gratings (gratings 514, 524 in Figs. 5A-5B).
It would have been obvious to one having ordinary at the time of filing to recognize the coupling technique of Fish would apply to the planar photonics integrated circuits of Aleksov / Molzer / Kim. One would be motivated to use evanescent coupler and grating coupler to improve upon butt coupling and free space coupling problems that are not compatible in integrated photonics circuits (Fish: Para [0002]-[0004]).
Claims 4-5, 19, 22, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov / Molzer / Kim as applied to claim 1 above, and further in view of Wang et al. (US 10,162,139 B1, herein “Wang”).
Claim 4. Aleksov / Molzer / Kim teach the invention of claim 1, but Aleksov / Molzer / Kim do not teach a first die over the second layer, wherein the first die is electrically coupled to the first PIC and second PIC.
Wang teaches a semiconductor package wherein an EIC die (190) is over the second layer (molding compound 162) via redistribution structure (150), wherein the first die is electrically coupled to the PIC (130) by way of through interlayer via (TIV 148).
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It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the chip package assembly of Wang replace the chip package assembly of Aleksov / Molzer / Kim such that the EIC die over “the second layer” wherein the EIC die is electrically coupled to the first PIC (Kim: 120) and the second PIC (Kim: 125). One would be motivated to stack EIC over the second layer and electrically coupled it to the first and second PIC to shorten the electrical connection between the driver circuit 190 (Col. 5, lines 24-41) and the PIC chips, thus condensing the package size and increase the density of the chip assembly.
Claim 5. Wang further teaches a second die (laser die 200) over the second layer (molding compound 162) via redistribution structure (150), wherein the second die is electrically coupled to the PIC (130) by way of through redistribution structure (150) and interlayer via (TIV 148).
However, Wang does not teach a third die over the second layer, wherein the third die is coupled to the second PIC.
It would have been obvious to one of ordinary skill in the art at the time of filing to provide corresponding dies to drive the first and second PIC and provide laser die and photodiode die for the functioning of the first and second PICs per design specifications, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Claims 19 and 22. Aleksov discloses a method of forming an electronic package, comprising:
forming vias through a first layer (102), wherein the first layer comprises glass (Para [0036]);
attaching a plurality of integrated circuit chips to the first layer (114-1…114-6);
disposing a second layer (127) over the first layer and the plurality of integrated circuit chips (114-1…114-6), wherein the second layer is a mold layer (Para [0026]);
forming optical waveguides in the first layer (110), wherein the optical waveguides optically couple the integrated circuit chips together. The examiner notes, the method steps in claim 19 (e.g., forming, attaching, disposing etc.) do not patentably distinguish from the product since the assembly of the device would necessarily demonstrates the step of forming, attaching, disposing etc.
In a separate embodiment, Example 21, Aleksov discloses the interposer includes a through-silicon via, and the circuitry of the first interposer is coupled to the waveguide by the through-silicon via (Para [0117]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize the through-silicon via can be duplicated to such that each via can be coupled to each side of the waveguide. The motivation would be to access the optical signal at each end of the waveguide effectively functioning as input and output coupling node of the waveguide.
Aleksov is silent to the through-silicon via (TSV) is formed through the first layer (glass) and the second layer (mold material).
Molzer teaches in Fig. 12 package vias wherein through-mold via (TMV 128) and through-silicon via (TSV 29) are formed through the mold material (Fig. 3A and 3B show in more details, see also Col. 3, line 55 to Col. 4, line 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify conventional vias with TSVs and TMVs to provide interconnect through different materials. One would be motivated to design multi-chip packages with plurality of TSVs and TMVs to reduce cross-talk and external perturbation. TMVs and TSVs can shorten the signal path between circuitry thus reducing the overall package size that includes the benefit of reduce cross-talk (Col. 2, line 62 – Col. 3, line 3).
Aleksov and Molzer are silent to the chip packages shown in Fig. 1 as photonics integrated circuit (PIC) chips.
Kim teaches forming a first layer (105), wherein the first layer comprises glass (Col. 3, lines 25-43). Kim teaches forming vias (electronic interconnect 135) through a first layer (105), wherein Kim teaches attaching a plurality of photonics integrated circuits (120, 125) to the first layer (105).
It would have been obvious to one having skills in the art at the time of filing to recognize the chips in the invention of Aleksov and Molzer can be modified by replacing them with the PICs as shown by Kim since assembling a PIC in place of an EIC is within the skills of an ordinary artisan in the optoelectronic art. One would be motivated to exchange the EIC with the PIC to hybridize the device to perform optical processing and electrical processing.
Aleksov in view Molzer and Kim do not teach disposing dies over the second layer.
Wang teaches forming a semiconductor package wherein an EIC die (190) is disposed over the second layer (molding compound 162).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize EIC dies are necessary to provide driving signals to the PICs, such that disposing the EIC in over the second layer would place the EIC dies in close proximity to the PICs for efficient interconnection.
Claim 23. Aleksov discloses an electronic system (Fig. 15), comprising:
a board (1702);
a package substrate (IC package 1724) coupled to the board (1702);
a patch (1700) coupled to the package substrate (1724) via electrical interconnections on board (1702), wherein the patch (1700) may include any of the microelectronic assemblies 100 (Para [0075]) comprises:
a first layer (102), wherein the first layer comprises glass (Para [0036];
a second layer (molded material 127) over the first layer (102), wherein the second layer comprises a mold material (Para [0026]);
the mold material (127) is formed over chip interposers (132-1, 132-2) and chip packages (114-1 … 114-6),
a waveguide (waveguide 110) in the first layer, wherein the waveguide optically couples the first chip package (left package) to the second chip package (right package).
In a separate embodiment, Example 21, Aleksov discloses the interposer includes a through-silicon via, and the circuitry of the first interposer is coupled to the waveguide by the through-silicon via (Para [0117]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize the through-silicon via can be duplicated to such that each via can be coupled to each side of the waveguide. The motivation would be to access the optical signal at each end of the waveguide effectively functioning as input and output coupling node of the waveguide.
Aleksov is silent to the through-silicon via (TSV) is formed through the first layer (glass) and the second layer (mold material).
Molzer teaches in Fig. 12 package vias wherein through-mold via (TMV 128) and through-silicon via (TSV 29) are formed through the mold material (Fig. 3A and 3B show in more details, see also Col. 3, line 55 to Col. 4, line 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify conventional vias with TSVs and TMVs to provide interconnect through different materials. One would be motivated to design multi-chip packages with plurality of TSVs and TMVs to reduce cross-talk and external perturbation. TMVs and TSVs can shorten the signal path between circuitry thus reducing the overall package size that includes the benefit of reduce cross-talk (Col. 2, line 62 – Col. 3, line 3).
Aleksov and Molzer are silent to the chip packages shown in Fig. 1 as photonics integrated circuit (PIC) chips.
Kim teaches co-packaging with silicon photonics hybrid planar lightwave circuit wherein substrate (105) supports the first PIC (120) and the second PIC (125) and a waveguide in the first layer, wherein the waveguide optically couples with the first PIC to the second PIC (Fig. 1a and 1b).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the chips (114-1…114-6) can be interchanged with the photonics integrated circuit chips (120, 125) as disclosed by Kim. Aleksov and Molzer disclose an embodiment of larger integrated module shown in Fig. 16 wherein one of the integrated chip is a communication chip (1812) such that there are optical components (Para [0087]). Therefore, it would have been within the skills of an ordinary practitioner of the art to recognize replacing the electronic chips in the invention of Aleksov and Molzer with photonics integrated chips of Kim, wherein both platforms are provided with electrical and optical interconnections. The motivation for co-packaging of electronic integrated circuits and photonic integrated circuits is reducing or minimization of power consumption (Kim: Col. 2, lines 38-58).
Aleksov / Molzer / Kim do not teach a die coupled to the patch (1700).
Wang teaches a semiconductor package wherein an EIC die (190) is over the second layer (molding compound 162) via redistribution structure (150), wherein the first die is electrically coupled to the PIC (130) by way of through interlayer via (TIV 148).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the chip package assembly of Wang replace the chip package assembly of Aleksov / Molzer / Kim such that the EIC die over “the second layer” wherein the EIC die is electrically coupled to the first PIC (Kim: 120) and the second PIC (Kim: 125). One would be motivated couple a die to the patch for stacking architecture that can easily add more packages onto the existing package, also known as package-on-package.
Claim 25. Aleksov / Molzer / Kim in view of Wang teach claim 23. Aleksov further teaches high bandwidth (HBW) interconnect (110) includes a waveguide, which is any linear structure that conveys electromagnetic waves between its endpoints; this includes optical waveguide. Furthermore, the HBW interconnected may be filled with a dielectric material, which would include glass the same material as substrate 102. Aleksov further teaches waveguide (110) has a different microstructure than the first layer such as rectangular block (Para [0028]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov / Molzer / Kim in view of Wang as applied to claim 5 above, and further in view of Charles et al. (US 2020/0166720 A1, herein “Charles”).
Aleksov / Molzer / Kim in view of Wang teach the invention of claim 5. Aleksov / Molzer / Kim in view of Wang do not teach a first via coupled to the second die, wherein the first via coupled to the second die; and a second via coupled to the third die.
Charles teaches photonics optoelectrical system (Fig. 3) wherein via VXA is provided therein to extend through photonics dielectric stack (200), bond layer (4016), and interposer (220).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the stacked architecture of optoelectrical packages demand more electrical interconnections such that interlayers electrical vias of Charles would have been obvious to one having ordinary skill in the art to modify for providing electrical driving and powering signals to stacked EIC chips and PIC chips. One would be motivated to provide through multiple substrate vias to reduce manufacturing cost.
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Claims 7, 13-14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov / Molzer / Kim as applied to claim 1 above, and further in view Janta-Polczynski et al. (US 2020/0279840 A1, herein “Janta”).
Claim 7. Aleksov / Molzer / Kim teach the invention of claim 1, but Aleksov / Molzer / Kim do not teach the first PIC and second PIC extend into the first layer.
Janta teaches a photonics package wherein PIC die (130) is disposed within a cavity (503) (Fig. 5C). Janta further teaches the implementation of embodiment of Fig. 5C can be replicated to multiple PIC chips as shown in Fig. 6. It would have been obvious to one having ordinary skill in the art to recognize the teaching of Janta for setting the PIC chip into the first layer is for alignment with the optical components and interconnection with the electrical components (Para [0004]). One motivation for providing a cavity for the photonic chip is to design alignments and interconnections onto the substrate or redistribution layer which would simplify the placement of the photonic chips (Para [0004], [0032]).
Claim 13. Aleksov discloses an electronic package (Fig. 1), comprising:
a first layer (package substrate 102, Para [0036]), wherein the first layer comprises glass;
a second layer (molded material 127) over the first layer (102), wherein the second layer comprises a mold material (Para [0026]);
chip packages (114-1…114-6) are formed on the first layer (102)
a waveguide (waveguide 110) in the first layer, wherein the waveguide optically couples the first chip package (left package) to the second chip package (right package).
In a separate embodiment, Example 21, Aleksov discloses the interposer includes a through-silicon via, and the circuitry of the first interposer is coupled to the waveguide by the through-silicon via (Para [0117]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize the through-silicon via can be duplicated to such that each via can be coupled to each side of the waveguide. The motivation would be to access the optical signal at each end of the waveguide effectively functioning as input and output coupling node of the waveguide.
Aleksov is silent to the through-silicon via (TSV) is formed through the first layer (glass) and the second layer (mold material).
Molzer teaches in Fig. 12 package vias wherein through-mold via (TMV 128) and through-silicon via (TSV 29) are formed through the mold material (Fig. 3A and 3B show in more details, see also Col. 3, line 55 to Col. 4, line 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify conventional vias with TSVs and TMVs to provide interconnect through different materials. One would be motivated to design multi-chip packages with plurality of TSVs and TMVs to reduce cross-talk and external perturbation. TMVs and TSVs can shorten the signal path between circuitry thus reducing the overall package size that includes the benefit of reduce cross-talk (Col. 2, line 62 – Col. 3, line 3).
However, Aleksov and Molzer do not disclose the chip packages (114-1…114-6) are photonics integrated circuit (PIC).
Kim teaches co-packaging with silicon photonics hybrid planar lightwave circuit wherein substrate (105) supports the first PIC (120) and the second PIC (125) and a waveguide in the first layer, wherein the waveguide optically couples with the first PIC to the second PIC (Fig. 1a and 1b).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the chips (114-1…114-6) can be interchanged with the photonics integrated circuit chips (120, 125) as disclosed by Kim. Aleksov suggests an embodiment of larger integrated module shown in Fig. 16 wherein one of the integrated chip is a communication chip (1812) such that there are optical components (Para [0087]). Therefore, it would have been within the skills of an ordinary practitioner of the art to recognize replacing the electronic chips in Aleksov with photonics integrated chips of Kim, wherein both platforms are provided with electrical and optical interconnections. The motivation for co-packaging of electronic integrated circuits and photonic integrated circuits is reducing or minimization of power consumption (Kim: Col. 2, lines 38-58).
Aleksov / Molzer / Kim is silent to the first and second PIC embedded in the first layer, the second layer, or the first layer and the second layer.
Janta teaches a photonics package wherein PIC die (130) is disposed within a cavity (503) (Fig. 5C). Janta further teaches the implementation of embodiment of Fig. 5C can be replicated to multiple PIC chips as shown in Fig. 6. It would have been obvious to one having ordinary skill in the art to recognize the teaching of Janta for setting the PIC chip into the first layer is for alignment with the optical components and interconnection with the electrical components (Para [0004]) would be modifiable to the invention of Aleksov / Molzer / Kim. One would etch a cavity into the substrate with predetermined interconnections for receiving the PIC chip as shown in Janta’s disclosure. One motivation for providing a cavity for the photonic chip is to design alignments and interconnections onto the substrate or redistribution layer which would simplify the placement of the photonic chips (Para [0004], [0032]).
Claims 14. Aleksov / Molzer / Kim in view of Janta teach the invention of claim 13 and further teach the active layer is at a bottom surface of the first and second PIC and the waveguide. Aleksov / Molzer / Kim in view of Janta do not explicitly teach the first PIC and the second PIC are in the first layer wherein an active layer of the first PIC is at a top surface of the first PIC, and wherein an active layer of the second PIC is at a top surface of the second PIC. However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because choosing the surface for the active layer to make electrical connections do not change the function and operation of the first and second PIC. The benefits of this modification include selecting the shortest interconnection path(s) to reduce resistance.
Claim 15. Aleksov / Molzer / Kim in view of Janta teach the invention of claim 14 and further teach the waveguide is at a top surface of the first layer (Aleksov: Fig. 1).
Claim 16 The combined teaching of Aleksov / Molzer / Kim in view of Janta teach the first PIC (120) and the second PIC (125) are in the first layer (Janta: embedded in a cavity), wherein an active layer of the first PIC (120) is at a bottom surface of the first PIC and wherein an active layer of the second PIC is at a bottom surface of the second PIC (Kim: Fig. 1A and 1B).
Claim 17. The combined teaching of Aleksov / Molzer / Kim in view of Janta teach the waveguide is embedded in the first layer (Aleksov: Fig. 1).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Molzer/Kim in view of Wang as applied to claim 19 above, and further in view of Patel et al. (US 2020/0049890 A1, herein “Patel”).
Aleksov / Molzer / Kim in view of Wang teach the invention of claim 19, but Aleksov / Molzer / Kim in view of Wang do not teach forming the optical waveguides comprises exposing the first layer to a laser to account for misplacement of the plurality of PICs.
Patel teaches imparting a waveguide pattern by exposing the laser to the glass substrate by modifying the refractive index of the patterned glass. (Para [0037]).
It would have been obvious to one having ordinary skill in the art at the time of filing to recognize the method step of patterning waveguides using laser as taught by Patel would be implemented to form the waveguide in the invention of Aleksov / Molzer / Kim in view of Wang. One would be motivated to use laser for patterning the waveguide since laser is precise and adjustments to the placement of the patterns can be adapted to alignment changes of the optical elements.
As for the limitation—a process to account for misplacement of the plurality of PICs—the examiner considers Patel teaches the same process of patterning using laser as recited in claim 20, the intended limitation—to account for misplacement—would necessarily be met since the process of Patel is the same as the broadly recited method step.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Molzer/Kim in view of Wang as applied to claim 23 above, and in further view of Lu.
Aleksov / Molzer / Kim in view of Wang teach the invention of claim 23. However, Aleksov / Molzer / Kim in view of Wang do not teach the first PIC and the second PIC extend into the first layer.
Lu teaches electronic device package wherein the PIC is disposed in the cavity of the substrate and the encapsulant (molding material) is disposed in the cavity to encapsulate the PIC (Para [0038]). It would have been obvious to one having ordinary skill at the time of filing to recognize the teaching Lu embedding the PIC chip in the first and second layers would be modifiable to the first and second PIC in the invention as taught by Aleksov / Molzer / Kim in view of Wang. One would be motivated to encase the PIC within the substrate and encapsulant to reduce the overall thickness of the device package (Lu: Para [0038]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14, 16-17, and 19-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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/ERIN D CHIEM/Examiner, Art Unit 2874