DETAILED ACTION
This action is in response to the filing on 10/20/2025. Claims 1-5, 7-16, and 18-21, are pending and have been considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, 7, 16, and 18-21 are rejected under 35 U.S.C 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1 and 16
Step 1:
Claims 1 and 16 recite a method, system, and manufacture; therefore, they are directed to one of the four categories of statutory subject matter (process/method, machine/product/apparatus, manufacture, or composition of matter).
Step 2A Prong 1:
Claim 1 recites a method comprising:
delivering a quantum of charge to a circuit representing a stored state of a neural network node of a neural network as a stored voltage, the delivered quantum of charge to affect the stored voltage, the quantum of charge to be determined according to a value of one or more error signals generated based, at least in part, on one or more errors generated by a local operational circuit— Under its broadest reasonable interpretation, this limitation encompasses a mathematical concept of a mathematical relationship (see MPEP § 2106.04(a)(2)(I)), specifically organizing information and manipulating information through mathematical correlations. The at least one stored voltage is a variable, which is affected according to a value of charge, e.g., a number.
determining a fitness of a solution of the neural network based, at least in part, on the affected stored voltage— Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mental process, or a concept that can be performed in the human mind with the use of a physical aid (e.g. pen and paper), including observation, evaluation, judgement or opinion (see MPEP § 2106.04(a)(2)(III)). Or a mathematical concept achievable through mathematical computation (see MPEP § 2106.04(a)(2)(I)), specifically organizing information and manipulating information through mathematical correlations.
Claim 16 recites a manufacture comprising:
represent a circuit, to be formed in a circuit device, to deliver a first quantum of charge to a circuit representing a stored state of a first neural network node as a first stored voltage, the delivered first quantum of charge to affect the first stored voltage, the first quantum of charge to be determined according to a value of one or more error signals generated by a first local operational circuit— Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mental process, or a concept that can be performed in the human mind with the use of a physical aid (e.g. pen and paper), including observation, evaluation, judgement or opinion (see MPEP § 2106.04(a)(2)(III)).
Step 2A Prong 2:
This judicial exception is not integrated into a practical application.
Claim 16 recites the additional element of:
an article comprising: a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to generic computer-readable instructions.
Step 2B:
The claims do not contain significantly more than the judicial exception.
Claim 16 recites the additional element of:
an article comprising: a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to generic computer-readable instructions.
As such claims 1 and 16 are not patent eligible.
Dependent Claims 2-5, 7, and 18-21
Step 1:
Claims 2-5 and 7 recite a method, 18-21 recite a manufacture; therefore, they are directed to one of the four categories of statutory subject matter (process/method, machine/product/apparatus, manufacture, or composition of matter).
Step 2A Prong 1:
Claims 2-5, 7, and 18-21 merely narrow the previously cited abstract idea limitations. For the reasons described above with respect to independent claims 1 and 16 this judicial exception is not meaningfully integrated into a practical application, or significantly more than the abstract idea. The claims disclose similar limitations described for the independent claims above and do not provide anything more than the abstract idea.
Claim 3 recites a method comprising:
varying the one or more error signals responsive, at least in part, to adjustments in a supply voltage, current driver, load capacitance, operating clock frequency or operating temperature, or a combination thereof — Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mathematical concept of a mathematical relationship (see MPEP § 2106.04(a)(2)(I)), specifically organizing information and manipulating information through mathematical correlations. Error signals are number values and adjustments to various parameters are variables.
Claim 5 recites a method comprising:
varying a current and/or voltage applied to the local operational circuit to vary a distribution of the one or more error signals — Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mathematical concept of a mathematical relationship (see MPEP § 2106.04(a)(2)(I)), specifically organizing information and manipulating information through mathematical correlations. Error signals are number values and adjustments to various parameters are variables.
Claim 7 recites a method comprising:
ranking the neural network relative to other neural networks based, at least in part, on the determined fitness — Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mental process, or a concept that can be performed in the human mind with the use of a physical aid (e.g. pen and paper), including observation, evaluation, judgement or opinion (see MPEP § 2106.04(a)(2)(III)). Or a mathematical concept of a mathematical relationship (see MPEP § 2106.04(a)(2)(I)), specifically organizing information and manipulating information through mathematical correlations.
selectively spawning a child of the neural network based, at least in part, on the ranking — Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mental process, or a concept that can be performed in the human mind with the use of a physical aid (e.g. pen and paper), including observation, evaluation, judgement or opinion (see MPEP § 2106.04(a)(2)(III)).
Claim 19 recites a manufacture comprising:
represent a circuit to be formed in the circuit device to deliver a second quantum of charge to a circuit to represent a stored state of a second neural network node to affect the second stored voltage, the second quantum of charge to be determined according to a value of one or more error signals generated by a second local operational circuit, wherein the first and second neural network node are disposed in a same layer of the neural network— Under its broadest reasonable interpretation, this limitation encompasses the abstract idea of a mental process, or a concept that can be performed in the human mind with the use of a physical aid (e.g. pen and paper), including observation, evaluation, judgement or opinion (see MPEP § 2106.04(a)(2)(III)).
Step 2A Prong 2:
This judicial exception is not integrated into a practical application.
Claim 2 recites the additional element of:
wherein the local operational circuit comprises a reduced-voltage and/or reduced-current circuit — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to reduced voltage/current circuits.
Claim 4 recites the additional element of:
wherein the neural network node comprises a neural network node of a spiking neural network — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a spiking neural network.
Claim 18 recites the additional element of:
wherein the computer-readable instructions are formatted according to a register description language — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a register description language.
Claim 20 recites the additional element of:
wherein the first neural network node comprises a neural network node of a spiking neural network — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a spiking neural network.
Claim 21 recites the additional element of:
wherein the first local operational circuit comprises a reduced-voltage and/or reduced-current circuit — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to reduced voltage/current circuits.
Step 2B:
The claims do not contain significantly more than the judicial exception.
Claim 2 recites the additional element of:
wherein the local operational circuit comprises a reduced-voltage and/or reduced-current circuit — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to reduced voltage/current circuits.
Claim 4 recites the additional element of:
wherein the neural network node comprises a neural network node of a spiking neural network — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a spiking neural network.
Claim 18 recites the additional element of:
wherein the computer-readable instructions are formatted according to a register description language — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a register description language.
Claim 20 recites the additional element of:
wherein the first neural network node comprises a neural network node of a spiking neural network — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to a spiking neural network.
Claim 21 recites the additional element of:
wherein the first local operational circuit comprises a reduced-voltage and/or reduced-current circuit — This element amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)). This element merely limits the use of the abstract idea to reduced voltage/current circuits.
As such claims 2-5, 7, and 18-21 are not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8–15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Y. Kim et al. (An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems), hereinafter Kim.
Regarding claim 8, Kim teaches a circuit to alter one or more parameters of a neural network, comprising (Fig. 5 depicts the block diagram of a general digital neuromorphic hardware architecture for spiking neural networks. It consists of three arrays of synapse, learning, and neuron circuits as well as a control and an interface circuits for them. ... The learning circuits cooperate with the respective neurons and update the synaptic weights according to a learning-rule, such as spike timing dependent plasticity (STDP). [Section 3.1, para. 1; Fig. 5]):
a circuit to represent a stored state of a first neural network node as a first stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]);
a first local operational circuit (Kim discloses an adder circuit shown in Fig. 1 which is used in the circuitry of Fig. 5);
a circuit to deliver a first quantum of charge to the circuit to represent the stored state of the first neural network node (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]), the first quantum of charge to be determined according to a value of one or more error signals generated by the first local operational circuit (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Fig. 5] will affect the stored voltage [see Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Section 2.2, para. 1; Fig. 1]).
Regarding claim 9, Kim teaches all the limitations of claim 8 and further teaches:
a circuit to represent a stored state of a second neural network node as a stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]);
a second local operational circuit (Kim discloses an adder circuit in Fig. 1 which is used in the circuitry of Fig. 5);
a circuit to deliver a second quantum of charge to the circuit to represent the stored state of the second neural network node to affect the second stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]), the second quantum of charge to be determined according to a value of one or more error signals generated by the second local operational circuit (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Fig. 5] will affect the stored voltage [see Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Section 2.2, para. 1; Fig. 1]), wherein the first and second neural network nodes are disposed in a same layer of the neural network (We specifically consider the case where the neuromorphic hardware is configured to be a two-layer network for character recognition as illustrated in Fig. 6 [4]. The input and output layers have 196 and 36 excitatory neurons, respectively. [Section 3.3, para. 2]; Choose any 2 nodes such that they are either both in the input layer, or both in the output layer).
Regarding claim 10, Kim teaches all the limitations of claim 8 and further teaches:
a circuit to represent a stored state of a second neural network node as a stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]);
a second local operational circuit (Kim discloses an adder circuit in Fig. 1 which is used in the circuitry of Fig. 5);
a circuit to deliver a second quantum of charge to the circuit to represent the stored state of the second neural network node to affect the second stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]), the second quantum of charge to be determined according to a value of one or more error signals generated by the second local operational circuit (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Fig. 5] will affect the stored voltage [see Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Section 2.2, para. 1; Fig. 1]);
wherein: the first neural network node is disposed in a first layer of the neural network and the second neural network node is disposed in a second layer of the neural network that is downstream of the first layer of the neural network (We specifically consider the case where the neuromorphic hardware is configured to be a two-layer network for character recognition as illustrated in Fig. 6 [4]. The input and output layers have 196 and 36 excitatory neurons, respectively. [Section 3.3, para. 2]; Choose any 2 nodes such that a first node is in the input layer and connected to a second node in the output layer).
Regarding claim 11, Kim teaches all the limitations of claim 10 and further teaches:
a network to route a spike signal generated based, at least in part, on the affected first stored voltage to affect the second stored voltage (Fig. 5 depicts the block diagram of a general digital neuromorphic hardware architecture for spiking neural networks. It consists of three arrays of synapse, learning, and neuron circuits as well as a control and an interface circuits for them. The N×N crossbar array can represent a fully recurrent network topology and store N2 possible synaptic weights among N neurons. [Section 3.1, par. 1; Fig. 5]).
Regarding claim 12, Kim teaches all the limitations of claim 8 and further teaches:
wherein the local operational circuit comprises a reduced-voltage and/or reduced-current circuit (Kim discloses scaling down the supply voltage of the adder from the regular supply voltage of 1.2V to 0.95V [see Kim, Section 4.4, para. 3; Fig. 10]).
Regarding claim 13, Kim teaches all the limitations of claim 8 and further teaches:
a circuit to vary the one or more error signals responsive, at least in part, to adjustments in a supply voltage, current driver, load capacitance, operating clock frequency or operating temperature, or a combination thereof (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]. Thus, when computing the voltage the errors will be varied based on previous voltage that is supplied).
Regarding claim 14, Kim teaches all the limitations of claim 8 and further teaches:
wherein the first neural network node comprises a neural network node of a spiking neural network (Fig. 5 depicts the block diagram of a general digital neuromorphic hardware architecture for spiking neural networks. [Section 3.1, para. 1; Fig. 5]).
Regarding claim 15, Kim teaches all the limitations of claim 8 and further teaches:
a circuit to vary a current and/or voltage applied to the first local operational circuit to vary a distribution of the one or more error signals (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]. Thus, when computing the voltage the errors will be varied based on previous voltage that is supplied).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim et al. (An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems), hereinafter Kim, in view of McDonnell et al. (US 10/685,286 B1), hereinafter McDonnell.
Regarding claim 1, Kim teaches a method comprising:
delivering a quantum of charge to a circuit representing a stored state of a neural network node of a neural network as a stored voltage, the delivered quantum of charge to affect the stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]), the quantum of charge to be determined according to a value of one or more error signals generated based, at least in part, on one or more errors generated by a local operational circuit (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Fig. 5] will affect the stored voltage [see Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Section 2.2, para. 1; Fig. 1]).
However, Kim fails to teach determining a fitness of a solution of the neural network based, at least in part, on the affected stored voltage.
In the same field of endeavor, McDonnell teaches:
determining a fitness of a solution of the neural network based, at least in part, on the affected stored voltage (McDonnel discloses determining a fitness value of a neural network with a relative fitness estimator [see McDonnell, Col. 14, lines 44–48], and a fitness value is based on an error between the output of a neural network and the expected output of the dataset [see McDonnell, Col. 14, lines 9–28]).
It would have been obvious to one of ordinary skill, in the art at the time before the effective filing date of the invention to incorporate determining a fitness of a solution of the neural network based, at least in part, on the affected stored voltage as suggested in McDonnell into Kim because both systems perform machine learning (see Kim, Abstract; see McDonnell, Abstract). Incorporating the techniques of McDonnell into Kim would significantly reduce the amount of computing resources used to generate a neural network (see Col. 3, lines 43–45).
Regarding claim 2, the combination of Kim and McDonnell as applied in claim 1 above teaches all the limitations of claim 1 and further teaches:
wherein the local operational circuit comprises a reduced-voltage and/or reduced-current circuit (Kim discloses scaling down the supply voltage of the adder from the regular supply voltage of 1.2V to 0.95V [see Kim, Section 4.4, para. 3; Fig. 10]).
Regarding claim 3, the combination of Kim and McDonnell as applied in claim 1 above teaches all the limitations of claim 1 and further teaches:
varying the one or more error signals responsive, at least in part, to adjustments in a supply voltage, current driver, load capacitance, operating clock frequency or operating temperature, or a combination thereof (Kim discloses that the adder [see Kim, Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Kim, Section 2.2, para. 1; Fig. 1]. Kim discloses that the membrane potential of a neuron is a voltage [see Kim, Section 3.2, para. 1], and the equation for calculating the voltage [see Kim, Equation 13]. Kim further discloses the neuron circuit [see Kim, Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Kim, Section 3.2, para. 1; Fig. 5]. Thus, when computing the voltage the errors will be varied based on previous voltage that is supplied).
Regarding claim 4, the combination of Kim and McDonnell as applied in claim 1 above teaches all the limitations of claim 1 and further teaches:
wherein the neural network node comprises a neural network node of a spiking neural network (Fig. 5 depicts the block diagram of a general digital neuromorphic hardware architecture for spiking neural networks. [see Kim, Section 3.1, para. 1; Fig. 5]).
Regarding claim 5, the combination of Kim and McDonnell as applied in claim 1 above teaches all the limitations of claim 1 and further teaches:
varying a current and/or voltage applied to the local operational circuit to vary a distribution of the one or more error signals (Kim discloses that the adder [see Kim, Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Kim, Section 2.2, para. 1; Fig. 1]. Kim discloses that the membrane potential of a neuron is a voltage [see Kim, Section 3.2, para. 1], and the equation for calculating the voltage [see Kim, Equation 13]. Kim further discloses the neuron circuit [see Kim, Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Kim, Section 3.2, para. 1; Fig. 5]. Thus, when computing the voltage the errors will be varied based on previous voltage that is supplied).
Regarding claim 7, the combination of Kim and McDonnell as applied in claim 1 above teaches all the limitations of claim 1 and further teaches:
ranking the neural network relative to other neural networks based, at least in part, on the determined fitness (the relative fitness estimator 134 is configured to receive two or more matrix representations 304 as input, to estimate the relative fitness of the two or more neural networks corresponding to the matrix representations 304, and provide as output the ranking values 314 indicating the relative ranking of the two or more neural networks. [see McDonnell, Col. 17, lines 55–61]);
selectively spawning a child of the neural network based, at least in part, on the ranking (For example, the evolutionary processor 316 can use a weighted randomization process to select particular neural networks for mutation and crossover operations. In this example, the likelihood of each neural network of the population 302 being randomly selected is weighted according to the estimated fitness data 310. In another example, some neural networks may be removed from the population 302 or prevented from participating in mutation or cross-over operations a result of having a relative low ranking value. Generally, neural networks with higher ranking values 314 or higher relative fitness values 312 contribute more to the formation of the next population (e.g., the population 320 in FIG. 3). As a result of the evolutionary operations, the population 302 is modified to form the population 320. For example, the population 320 includes new neural networks (e.g., child neural networks) that were not present in the population 302. [see McDonnell, Col. 18, lines 32–48; Fig. 3]).
Claims 16 and 19–21 are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim et al. (An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems), hereinafter Kim, in view of Wirthlin (US 2014/0372817 A1), hereinafter Wirthlin.
Regarding claim 16, Kim teaches an article comprising:
a circuit to deliver a first quantum of charge to a circuit representing a stored state of a first neural network node as a first stored voltage, the delivered first quantum of charge to affect the first stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Section 3.2, para. 1], and the equation for calculating the voltage [see Equation 13]. Kim further discloses the neuron circuit [see Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Section 3.2, para. 1; Fig. 5]), the first quantum of charge to be determined according to a value of one or more error signals generated by a first local operational circuit (Kim discloses that the adder [see Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Fig. 5] will affect the stored voltage [see Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Section 2.2, para. 1; Fig. 1]).
However, Kim fails to teach a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to: represent a circuit, to be formed in a circuit device.
In the same field of endeavor, Wirthlin teaches:
a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to (a non-transitory computer-readable storage medium can be configured to store instructions that when executed cause a processor to perform a process [see Wirthlin, Abstract]);
represent a circuit, to be formed in a circuit device (the representation processor 410 can include, or can use, a Computer Aided Design (CAD) tool that handles the circuit representation 43 (e.g., a netlist) as an input and then converts the circuit representation 43 into a low-level representation used to make the integrated circuit. [see Wirthlin, para. 44]).
It would have been obvious to one of ordinary skill, in the art at the time before the effective filing date of the invention to incorporate a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to: represent a circuit, to be formed in a circuit device as suggested in Wirthlin into Kim because both methods represent circuits (see Kim, Fig. 1 and 5; see Wirthlin Abstract). Wirthlin identifies that the format of the circuit can be implemented in a hardware description language (HDL) (see Wirthlin, para. 44), and Kim designed the circuits in Verilog HDL (see Kim, Section 4, para. 1). Incorporating the techniques of Wirthlin would provide a process for performing automated partial triple module redundancy (see Wirthlin, para. 7, Fig. 2) which would improve the reliability of portions of a circuit (see Wirthlin, para. 3).
Regarding claim 19, the combination of Kim and Wirthlin as applied in claim 16 teaches all the limitations of claim 16 and further teaches:
represent a circuit to be formed in the circuit device (the representation processor 410 can include, or can use, a Computer Aided Design (CAD) tool that handles the circuit representation 43 (e.g., a netlist) as an input and then converts the circuit representation 43 into a low-level representation used to make the integrated circuit. [see Wirthlin, para. 44]) to deliver a second quantum of charge to a circuit to represent a stored state of a second neural network node to affect the second stored voltage (Kim discloses that the membrane potential of a neuron is a voltage [see Kim, Section 3.2, para. 1], and the equation for calculating the voltage [see Kim, Equation 13]. Kim further discloses the neuron circuit [see Kim, Section 3.2, para. 1; Fig. 5] which computes the given voltage equation with an adder circuit adder and stores the resulting voltage in a register [see Kim, Section 3.2, para. 1; Fig. 5]), the second quantum of charge to be determined according to a value of one or more error signals generated by a second local operational circuit (Kim discloses that the adder [see Kim, Fig. 1] produces an error if any error event occurs for any of the sub-adders except the three least significant sub-adders [see Kim, Section 2.2, para. 1; Fig. 1]. Thus, the neuron circuit [see Kim, Fig. 5] will affect the stored voltage [see Kim, Section 3.2, para. 1; Fig. 5] according to a value of an error signal when the adder produces an error based on one or more errors generated by the sub-adders [see Kim, Section 2.2, para. 1; Fig. 1]), wherein the first and second neural network nodes are disposed in a same layer of a neural network (We specifically consider the case where the neuromorphic hardware is configured to be a two-layer network for character recognition as illustrated in Fig. 6 [4]. The input and output layers have 196 and 36 excitatory neurons, respectively. [see Kim, Section 3.3, para. 2]; Choose any 2 nodes such that they are either both in the input layer, or both in the output layer).
Regarding claim 20, the combination of Kim and Wirthlin as applied in claim 16 teaches all the limitations of claim 16 and further teaches:
wherein the first neural network node comprises a neural network node of a spiking neural network (Fig. 5 depicts the block diagram of a general digital neuromorphic hardware architecture for spiking neural networks. [see Kim, Section 3.1, para. 1; Fig. 5]).
Regarding claim 21, the combination of Kim and Wirthlin as applied in claim 16 teaches all the limitations of claim 16 and further teaches:
wherein the first local operational circuit comprises a reduced-voltage and/or reduced-current circuit (Kim discloses scaling down the supply voltage of the adder from the regular supply voltage of 1.2V to 0.95V [see Kim, Section 4.4, para. 3; Fig. 10]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim et al. (An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems), hereinafter Kim, in view of Wirthlin (US 2014/0372817 A1), hereinafter Wirthlin, as applied in claim 16 above, and further in view of Dharmagadda (US 20090007058 A1), hereinafter Dharmagadda.
Regarding claim 18, the combination of Kim and Wirthlin as applied in claim 16 teaches all the limitations of claim 16 and further teaches:
wherein the computer-readable instructions are formatted according to a hardware description language (The proposed approximate adder was designed in Verilog HDL and synthesized with a commercial 90 nm CMOS technology and standard cell library. [see Kim, Section 4, para. 1]).
However, the combination of Kim and Wirthlin fails to teach wherein the computer-readable instructions are formatted according to a register description language.
In the same field of endeavor, Dharmagadda teaches:
wherein the computer-readable instructions are formatted according to a register description language (FIG. 1 illustrates a flowchart of conventional SoC design. Typically, the design process begins by writing a specification for the chip design ( e.g., register specification 120). [see Dharmagadda, para. 4]; In other embodiments, the user interface 210 is a register description language (RDL) that can be used to define a register specification. [see Dharmagadda, para. 32]).
It would have been obvious to one of ordinary skill, in the art at the time before the effective filing date of the invention to incorporate wherein the computer-readable instructions are formatted according to a register description language as suggested in Dharmagadda into the combination of Kim and Wirthlin because both methods represent circuits with description languages (see Kim, Section 4, para. 1; see Dharmagadda, para. 4). Dharmagadda discloses that the conventional chip design involves a register specification which can be done using a hardware description language like VHDL (see Dharmagadda, para. 3), and VHDL is used by Kim to design the circuits and corresponding registers (see Section 4, para. 1, Fig. 5). Dharmagadda further discloses that a register description language can be used to define the register specification (see Dharmagadda, para. 32). It would have been obvious to one of ordinary skill in the art to swap the register specification written in VHDL to being written in an RDL to achieve the predictable result of formatting the chip design.
Response to Arguments
Examiner acknowledges Applicant’s amendments to claims 9 and 13. The correction to the claims are accepted and the objections are respectfully withdrawn.
Applicant’s arguments, filed 10/20/2025, traversing the rejection of claims 1-5, 7-16, and 18-21 under 35 U.S.C. 112(a) have been fully considered and are persuasive, the rejections are respectfully withdrawn.
Applicant’s arguments, filed 10/20/2025, traversing the rejection of claims 1-5, 7-16, and 18-21 under 35 U.S.C. 112(b) have been fully considered and are persuasive, the rejections are respectfully withdrawn.
Applicant’s arguments, filed 10/20/2025, traversing the rejection of claims 1-5, 7-16, and 18-21 under 35 U.S.C. 101 have been fully considered and are not persuasive. With respect to claim 1, Applicant argues that delivery of a quantum of charge to a circuit cannot be performed in the human mind, and that determination of a fitness of a solution of a neural network based on the affected stored voltage cannot be performed in the human mind; with respect to claim 16, Applicant argues that delivery of a quantum of charge to a circuit cannot be performed in the human mind. Applicant’s arguments will be addressed as follows;
With respect to claim 1 that delivery of a quantum of charge to a circuit cannot be performed in the human mind, Examiner agrees. However, in line with pg. 15 of the previous office action, as cited by the Applicant, and identified above in the 35 U.S.C. 101 section, the claim limitation was not identified to recite a mental process, but instead recites a mathematical concept of mathematical relationships, specifically, organizing information and manipulating information through mathematical correlations. In other words, the claim limitation analyzed as a whole is not only delivering the quantum of charge to a circuit, but delivering the quantum of charge to a circuit representing a stored state of a neural network node as a stored voltage, to affect the stored voltage. Such that the stored voltage is a variable which is to be affected by the value of the quantum of charge. Thus, the claim incorporates the mathematical concept of manipulating information in the form of stored voltages through a mathematical operation involving delivering a quantum of charge, which is a value of charge (e.g., a value being a number), such that the stored voltage is affected, in other words, the stored voltage is manipulated through the delivery of the value. For at least the aforementioned reason, the claim limitation when analyzed as a whole was identified to recite a judicial exception.
With respect to claim 1 that determination of a fitness of a solution of a neural network based on a stored voltage cannot be performed in the human mind, Examiner disagrees. In line with pg. 16 of the previous office action, as cited by the Applicant, determining a fitness of a solution of neural network can be reasonably performed in the human mind. The claim limitation being amended to recite the solution being based at least in part on the affected stored voltage does not significantly alter the determination step such that it can no longer be performed in the human mind, instead the amended limitation recites information for which the solution is based on. As such, the determination step was identified to still recite a judicial exception. For example, for an image recognition task as discussed in para. 15 of the specification, the neural network may recognize an input image as a particular class. If the neural networks solution, in the form of the recognized class, is incorrect, a human would reasonably be able to determine that the solution is not fit. Similarly, if the solution, in the form of the recognized class, is correct, a human would reasonably be able to determine that the solution is fit. For at least the aforementioned reason, the claim limitation when analyzed as a whole was identified to recite a judicial exception.
With respect to claim 1 that delivery of a quantum of charge to a circuit cannot be performed in the human mind, Examiner agrees. However, in line with pg. 17 of the previous office action, as cited by the Applicant, the claim limitation does not just recite delivering a quantum of charge, and recites representing a circuit to deliver a quantum of charge. Representing a circuit can be reasonably performed in the human mind with the aid of a pen and paper, and the specific information recited in the claim limitation about the circuit does not significantly alter the representation step such that it can no longer be reasonably performed, and instead offers the specifics of the circuit to be represented. As such, the circuit as claimed can be reasonably performed in the human mind with a pen and paper, for example, by drawing a schematic of the circuit which is to perform the delivery of a quantum of charge. For at least the aforementioned reason, the claim limitation when analyzed as a whole was identified to recite a judicial exception.
For at least the aforementioned reasons with respect to claims 1 and 16, and dependent claims 2-5, 7, and 18-21 which depend from independent claims 1 and 16, the claims recite judicial exceptions which are not practically integrated, and the rejection under 35 U.S.C. 101 is respectfully maintained.
Applicant’s arguments, filed 10/20/2025, traversing the rejection of claims 8-15 under 35 U.S.C. 102(a)(1) have been fully considered and are not persuasive. Applicant argues that Kim as cited does not make any mention of how a carry prediction error may affect as state of a neuron circuit and thus fails to suggest delivering a quantum of charge to affect a stored voltage according to a value of one or more error signals. Examiner disagrees.
As cited in the 35 U.S.C 102 section above, Kim discloses a neuron unit which stores a membrane potential as a voltage in a register, contains an adder circuit to calculate the voltage, and the particular adder circuit disclosed can produce errors as a result produced by errors in the sub-adders. Thus, when calculating the membrane potential of the neuron circuit, the adder may contain an error which affects the membrane potential stored as a voltage in the register. In other words, the membrane potential which is considered the state of the neuron circuit, is affected by the errors produced in the adder circuit. As such, it is clear that Kim does disclose how a carry prediction error may affect a state of the neuron circuit, and relates to one of the key concepts of the paper which is how the error of the adder may affect the neuromorphic system. Further, for at least aforementioned reasons, Kim does disclose delivering a quantum of charge to affect a stored voltage according to a value of one or more error signals.
For at least the aforementioned reasons, the rejections under 35 U.S.C. 102(a)(1) are respectfully maintained.
Applicant’s arguments, filed 10/20/2025, traversing the rejection of claims 1-5, 7, 16, and 18-21 under 35 U.S.C. 103 have been fully considered and are not persuasive. Applicant argues that the claims are not obvious for similar reasons as to the above arguments addressed for claims 8-15 not being disclosed by Kim, and further, that none of Salamai et al., ‘547 patent, ‘286 patent, ‘817 patent, or ‘058 publication, alone or in combination make up for the deficiency of Kim. For the same reasons as stated above with respect to claims 8-15, the rejections of claims 1-5, 7, 16, and 18-21 under 35 U.S.C. 103 are respectfully maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Denker et al. (US 5,224,179 A) teaches neural network circuitry which delivers quantum of charges corresponding to changes in voltages and interconnection weights.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.B./Examiner, Art Unit 2143
./JENNIFER N WELCH/ Supervisory Patent Examiner, Art Unit 2143
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