DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant amended claims 1, 21, and 25-29 in the Request for Continued Examination filed on 09/16/2025. Claims 12-20 are canceled.
Claims 1-11 and 21-29 remain pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/16/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-11 and 21-29 filed on 09/16/2025 have been considered but they are deemed to be moot in view of new grounds of rejection.
Claim Objections
Claims 1, 8, 9, and 21 are objected to because of the following informalities:
Claim 1, line 3, “a requester ID” should read “a requester identifier (ID)”;
Claim 8, lines 2-3, “the first key an ephemeral key generated by the CPU” should read “the first key is an ephemeral key generated by the CPU”;
Claim 9, lines 3-4, “the at least one key ID” should read “the at least one authorized key ID”;
Claim 21, line 2, “a CPU” should read “a central processing unit (CPU)”;
Claim 21, line 10, “a requester ID” should read “a requester identifier (ID)”;
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 and 21-29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The examiner is unable to find support for “the access control circuit to determine whether to perform cryptography for the memory transaction based at least in part on determining that the requester ID and the key ID of the memory transaction correspond with an entry in the access control data structure” for claim 1. The examiner is unable to find support for “the access control circuit to determine whether to perform cryptography for the storage transaction based at least in part on determining that the requester ID and the key ID of the storage transaction correspond with an entry in the access control table” for claim 21, and “determine by the access control circuit whether to perform cryptography for the storage transaction based at least in part on determining that the requester ID and the key ID of the storage transaction correspond with an entry in the access control data structure” for claim 25.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 21-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim limitation recites “the key ID” in line 4, which renders the claim vague and indefinite. It is unclear whether “the key ID” is referring to “at least one authorized key ID” in claim 1, lines 3-4, or to a different/distinct key ID.
Claim 1 recites the limitation "the requester" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 1, claim limitation recites “the requester ID” in line 11, which renders the claim vague and indefinite. It is unclear whether “the requester ID” is referring to “requester ID” in claim 1, line 3, or to “a requester identifier (ID)” in claim 1, line 7, or to a different/distinct requester ID.
Claim 1 recites the limitation "the fields of the key ID associated with the memory transaction" in line 19. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 4, claim limitation recites “the memory transaction” in line 2, which renders the claim vague and indefinite. It is unclear whether “the memory transaction” is referring to “a memory transaction” in claim 1, line 6, or to “a memory transaction” in claim 1, line 24, or to a different/distinct memory transaction.
Regarding claim 4, claim limitation recites “the key ID” in line 2, which renders the claim vague and indefinite. It is unclear whether “the key ID” is referring to “at least one authorized key ID” or to “a key ID” in claim 1, line 8, or to a different/distinct key ID.
Regarding claim 9, claim limitation recites “the memory transaction” in lines 1-2, which renders the claim vague and indefinite. It is unclear whether “the memory transaction” is referring to “a memory transaction” in claim 1, line 6, or to “a memory transaction” in claim 1, line 24, or to a different/distinct memory transaction.
Regarding claim 9, claim limitation recites “the data” in line 2, which renders the claim vague and indefinite. It is unclear whether “the data” is referring to “data” in claim 1, line 17, or to “decrypted data” in claim 1, line 23, or to “encrypted data” in claim 1, line 25, or to different/distinct data.
Regarding claim 10, claim limitation recites “the key ID” in lines 3-4, which renders the claim vague and indefinite. It is unclear whether “the key ID” is referring to “at least one authorized key ID” or to “a key ID” in claim 1, line 8, or to a different/distinct key ID.
Regarding claim 21, claim limitation recites “the key ID” in line 11, which renders the claim vague and indefinite. It is unclear whether “the key ID” is referring to “at least one authorized key ID” in claim 21, lines 10-11, or to a different/distinct key ID.
Claim 21 recites the limitation "the requester" in line 15. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 21, claim limitation recites “the requester ID” in line 18, which renders the claim vague and indefinite. It is unclear whether “the requester ID” is referring to “requester ID” in claim 21, line 10, or to “a requester identifier (ID)” in claim 21, line 14, or to a different/distinct requester ID.
Claim 21 recites the limitation "the fields of the key ID associated with the storage transaction" in lines 26-27. There is insufficient antecedent basis for this limitation in the claim.
Claim 24 recites the limitation "the cryptographic circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 25, claim limitation recites “the requester ID” in lines 10-11, which renders the claim vague and indefinite. It is unclear whether “the requester ID” is referring to “a requester identifier (ID)” in claim 25, lines 4-5, or to “a requester ID” in claim 25, line 10, or to a different/distinct requester ID.
Regarding claim 25, claim limitation recites “the key ID” in line 11, which renders the claim vague and indefinite. It is unclear whether “the key ID” is referring to “at least one authorized key ID” in claim 25, line 10, or to a different/distinct key ID.
Regarding claim 25, claim limitation recites “the requester ID” in line 13, which renders the claim vague and indefinite. It is unclear whether “the requester ID” is referring to “a requester identifier (ID)” in claim 25, lines 4-5 , or to “requester ID” in claim 25, line 10, or to a different/distinct requester ID.
Claim 25 recites the limitation "the fields of the key ID associated with the storage transaction" in lines 17-18. There is insufficient antecedent basis for this limitation in the claim.
Claim 25 recites the limitation "the processed data" in line 19. There is insufficient antecedent basis for this limitation in the claim.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 9, 21, 25, 27, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case et al. (US 2016/0364343 A1), hereinafter Case, in view of Hou et al. (US 2017/0371564 A1), hereinafter Hou, and in view of Childe et al. (US 2023/0360040 A1), hereinafter Childe.
Regarding claim 1, Case discloses
An apparatus comprising:
an access control circuit (inline encryption engine 112, FIG. 1) to receive a memory transaction directed to a storage, the memory transaction having a requester identifier (ID) to indicate the requester associated with the memory transaction and a key ID associated with the memory transaction ([0083]: receiving a memory transaction request including context component, such as a domain identifier, an operating system identifier, an algorithm, an encryption mode, a crypto key, a physical or virtual address, a resource domain, a privilege and a security state), the access control circuit to determine whether to perform cryptography for the memory transaction based at least in part on the requester ID and the key ID ([0055]: key selection policy unit uses attributes of the bus transaction or request such as domain identifier, operating system identifier, privilege level, address, and cipher mode, to determine which key to select; the selected key is then used to decrypt/encrypt the data input to cipher engine);
a cryptographic circuit couped to the access control circuit, the cryptographic circuit to perform a cryptographic operation on data associated with the memory transaction based at least in part on the key ID ([0055]: key selection policy unit uses attributes of the bus transaction or request such as domain identifier, operating system identifier, privilege level, address, and cipher mode, to determine which key to select; the selected key is then used to decrypt/encrypt the data input to cipher engine; & [0086]: encrypt the data using the key);
wherein the apparatus comprises an inline engine coupled between the storage and an accelerator, the inline engine to provide encrypted data to the accelerator ([0089]: communicating the encrypted data component to a location in the encrypted memory region), the storage to store encrypted data ([0087]: stores the encrypted data in the selected encrypted region of memory).
Case does not explicitly disclose
the accelerator comprises at least one of a graphics processing unit (GPU), a graphics accelerator and a digital signal processing (DSP) unit, the inline engine to provide decrypted data to the accelerator in response to a memory transaction from the accelerator directed to the storage, the storage to store encrypted data.
However, Hou discloses
the accelerator comprises at least one of a graphics processing unit (GPU), a graphics accelerator and a digital signal processing (DSP) unit, the inline engine to provide data to the accelerator in response to a memory transaction from the accelerator directed to the storage ([0029]: the non-real-time processing engine 108 (e.g., a GPU) may send a read request (via a connection 112) to the memory controller 102 to access data (e.g., video, audio or multimedia data associated with the display frames) stored in the memory 104; in response, the memory controller 102 may issue a read command (via a connection 114) to the memory 104 to allow the non-real-time processing engine 108 to acquire the data from the memory 104 (via a data bus 116)).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate feature of Hou to Case, because Case discloses receive memory transaction request ([0083]) and Hou further suggests GPU sends a read request to memory controller to access data stored in the memory ([0029]).
One of ordinary skill in the art would be motivated to utilize the teachings of Hou in the Case system in order to allow the non-real-time processing engine to acquire data from memory efficiently.
Case and Hou do not explicitly disclose
a first memory to store an access control data structure, the access control data structure having a plurality of entries, each entry to store a requester ID and at least one authorized key ID associated with the requester ID, wherein the key ID comprise a plurality of fields;
perform a cryptographic operation on data associated with the memory transaction according to an algorithm indicated by at least one of the fields of the key ID associated with the memory transaction.
However, Childe discloses
a first memory to store an access control data structure, the access control data structure having a plurality of entries, each entry to store a requester ID and at least one authorized key ID associated with the requester ID, wherein the key ID comprise a plurality of fields ([0236]: the QS registry includes a plurality of QS registration records in which reach record may include, for example one or more data fields and values representative of: a user identity (e.g. Customer Number/CUSTNUM or USER_ID) of said each user; a user secret associated with each user, a QREF locator associated with a data item stored by the user if any, or a QREF locator associated with a data item the user is allowed to access in some manner; a data item reference identifier associated with the data item, a quantum key identifier (e.g. QSKD_KEY_ID) associated with the QD key (e.g. QSKD_KEY) available for use in encrypting the data item prior to storage/decrypting the encrypted data item during access; and an access control list (e.g. ACL) associated with the data item; & [0270]: the following quantum key schema may be used for storing the QD keys and one or more fields associated with the allocated QD key (e.g. QSKD_KEY1) may be provided);
perform a cryptographic operation on data associated with the memory transaction according to an algorithm indicated by at least one of the fields of the key ID associated with the memory transaction ([0236]: a quantum key identifier (e.g. QSKD_KEY_ID) associated with the QD key (e.g. QSKD_KEY) available for use in encrypting the data item prior to storage/decrypting the encrypted data item during access).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate feature of Childe to Case and Hou, because Case and Hou disclose receive memory transaction request (Case: [0083]) and Childe further suggests each record includes user identity and key identifier ([0236]).
One of ordinary skill in the art would be motivated to utilize the teachings of Childe in the Case and Hou system in order to provide a secure system .
Regarding claim 2, Case, Hou, and Childe disclose the apparatus as described in claim 1. Case further discloses
a fabric, the fabric comprising the inline engine, the fabric to couple a central processing unit (CPU), the storage and the accelerator (FIG. 1 & [0017]: inline encryption engine has an output coupled to an input of switch fabric and an output of switch fabric is coupled to an input of IEE; another output of switch fabric is coupled to an input to secure RAM; & [0089]: inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC)).
Regarding claim 9, Case, Hou, and Childe disclose the apparatus as described in claim 2. Case further discloses
the accelerator is to send the memory transaction to request the data from the storage, and in response to the memory transaction, the inline engine is to decrypt the data according to a decryption algorithm identified using the at least one key ID and direct the decrypted data to the accelerator, without involvement of the CPU ([0087]: if the transaction request is a read request, to retrieve the data and decrypts the data; transfers the decrypted data to the requesting resource; & [0055]: key selection policy unit uses attributes of the bus transaction or request such as domain identifier, operating system identifier, privilege level, address, and cipher mode, to determine which key to select; the selected key is then used to decrypt/encrypt the data input to cipher engine).
Regarding claims 21 and 25, the limitations of claims 21 and 25 are rejected in the analysis of claim 1 above and these claims are rejected on that basis.
Regarding claim 27, Case, Hou, and Childe disclose the at least one non-transitory computer-readable medium as described in claim 25. Case, Hou, and Childe further disclose
cause the system to configure the access control data structure and store, in the access control data structure, a first entry having a first requester ID and at least one first key ID (Childe: [0236]: the QS registry includes a plurality of QS registration records in which reach record may include, for example one or more data fields and values representative of: a user identity (e.g. Customer Number/CUSTNUM or USER_ID) of said each user; a user secret associated with each user, a QREF locator associated with a data item stored by the user if any, or a QREF locator associated with a data item the user is allowed to access in some manner; a data item reference identifier associated with the data item, a quantum key identifier (e.g. QSKD_KEY_ID) associated with the QD key (e.g. QSKD_KEY) available for use in encrypting the data item prior to storage/decrypting the encrypted data item during access; and an access control list (e.g. ACL) associated with the data item; & [0270]: the following quantum key schema may be used for storing the QD keys and one or more fields associated with the allocated QD key (e.g. QSKD_KEY1) may be provided). Therefore, the limitations of claim 27 are rejected in the analysis of claim 25 above, and the claim is rejected on that basis.
Regarding claim 28, Case, Hou, and Childe disclose the at least one non-transitory computer-readable medium as described in claim 27. Case further discloses
to configure the cryptographic circuit to perform a first cryptographic mode according to a first key associated with the first key ID, wherein the first key ID is associated with the accelerator ([0089]: receiving the memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC), encrypting the data component according to the context component; & [0090]: the context component can include at least one of a group consisting of: a resource domain identifier, an encryption algorithm, an encryption mode, a crypto key, an address, operating system, a privilege level, a counter value, a starting variable, an initialization vector, and a security state).
Claim(s) 3-7, 23, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Hou, in view of Childe, and further in view of Ye (US 2021/0336780 A1).
Regarding claim 3, Case, Hou, and Childe disclose the apparatus as described in claim 2. Case, Hou, and Childe do not explicitly disclose
the access control circuit, in response to a first command from the CPU, is to store in the access control data structure a first entry having a first request ID and at least one first key ID, wherein the first command from the CPU is in response to a first instruction to cause the access control circuit to configure the access control data structure.
However, Ye discloses
the access control circuit, in response to a first command from the CPU, is to store in the access control data structure a first entry having a first request ID and at least one first key ID, wherein the first command from the CPU is in response to a first instruction to cause the access control circuit to configure the access control data structure ([0039]: after receiving the first storage request sent by the terminal, the operation server parses the first storage request to obtain the device identifier, the new public key, and the first to-be-verified signature information carried in the first storage request; & [0040]: sends the device public key and device identifier of the terminal to a device public key management server, so that the device public key management server correspondingly stores the device identifier and the device public key).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate feature of Ye to Case, Hou, and Childe, because Case, Hou, and Childe disclose receive memory transaction request (Case: [0083]) and Ye further suggests receive storage request and stores device identifier and device public key ([0039-0040]).
One of ordinary skill in the art would be motivated to utilize the teachings of Ye in the Case, Hou, and Childe system in order to better organize data.
Regarding claim 4, Case, Hou, Childe, and Ye disclose the apparatus as described in claim 3. Case, Hou, Childe, and Ye further disclose
the inline engine comprises a processor to process a command of the memory transaction and send the requester ID and the key ID to the access control circuit (Ye: [0039]: after receiving the first storage request sent by the terminal, the operation server parses the first storage request to obtain the device identifier, the new public key, and the first to-be-verified signature information carried in the first storage request; & [0040]: sends the device public key and device identifier of the terminal to a device public key management server, so that the device public key management server correspondingly stores the device identifier and the device public key). Therefore, the limitations of claim 4 are rejected in the analysis of claim 3 above, and the claim is rejected on that basis.
Regarding claim 5, Case, Hou, Childe, and Ye disclose the apparatus as described in claim 3. Case further discloses
the access control circuit, in response to a second command from the CPU (processing core), is to configure the cryptographic circuit to perform a first cryptographic mode according to a first key associated with the first key ID, wherein the first key ID is associated with the accelerator ([0089]: receiving the memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC), encrypting the data component according to the context component; & [0090]: the context component can include at least one of a group consisting of: a resource domain identifier, an encryption algorithm, an encryption mode, a crypto key, an address, operating system, a privilege level, a counter value, a starting variable, an initialization vector, and a security state).
Regarding claim 6, Case, Hou, Childe, and Ye disclose the apparatus as described in claim 5. Case further discloses
according to the second command having a first command encoding, the inline engine is to receive and store the first key, the first key generated by an application executed on the CPU ([0054]: cipher key storage unit 404 is a register or buffer that stores cipher keys generated by key generation and long term key recovery unit; cipher key storage unit includes as many entries as are necessary to save keys for various domains and crypto codes being used in SOC).
Regarding claim 7, Case, Hou, Childe, and Ye disclose the apparatus as described in claim 6. Case further discloses
according to another instantiation of the second command having a second command encoding, the inline engine is to clear the first key and associate a default memory encryption behavior with the first key ID ([0074]: all keys can be cleared upon tamper or security violation detection; & [0073]: upon tamper detection, all buffered memory contents can be erased and access to registers blocked; encryption keys can be immediately erased with an asynchronous reset to the key registers).
Regarding claim 23, the limitations of claim 23 are rejected in the analysis of claim 3 above and this claim is rejected on that basis.
Regarding claim 24, the limitations of claim 24 are rejected in the analysis of claim 5 above and this claim is rejected on that basis.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Hou, in view of Childe, in view of Ye, and further in view of Anshel et al. (US 10,367,640 B2), hereinafter Anshel.
Regarding claim 8, Case, Hou, Childe, and Ye disclose the apparatus as described in claim 5. Case, Hou, Childe, and Ye do not explicitly disclose
according to the second command having a third command encoding, the inline engine is to receive and store the first key, the first key an ephemeral key generated by the CPU.
However, Anshel discloses
according to the second command having a third command encoding, the inline engine is to receive and store the first key (Col. 9, lines 19-21: device receives public key from trusted third party device and store public key in memory), the first key an ephemeral key generated by the CPU (Col. 10, lines 11-15: processor of device generates first ephemeral private key).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate feature of Anshel to Case, Hou, Childe, and Ye, because Case, Hou, Childe, and Ye disclose receive memory transaction request (Case: [0083]) and Anshel further suggests generate ephemeral private key (Col. 10, lines 11-15).
One of ordinary skill in the art would be motivated to utilize the teachings of Anshel in the Case, Hou, Childe, and Ye system in order to provide stronger security.
Claim(s) 10, 11, 22, 26, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Hou, in view of Childe, and further in view of Geissinger (US 2018/0137176 A1).
Regarding claim 10, Case, Hou, and Childe disclose the apparatus as described in claim 1. Case, Hou, and Childe do not explicitly disclose
a compression circuit coupled to the access control circuit, the compression circuit to perform compression/decompression operations on the data associated with the memory transaction based at least in part on the key ID.
However, Geissinger discloses
a compression circuit coupled to the access control circuit, the compression circuit to perform compression/decompression operations on the data associated with the memory transaction based at least in part on the key ID ([0111]: the scanned compressed objects are decompressed using the corresponding decompression keys).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate feature of Geissinger to Case, Hou, and Childe, because Case, Hou, and Childe disclose receive memory transaction request (Case: [0083]) and Geissinger further suggests decompress objects using key ([0111]).
One of ordinary skill in the art would be motivated to utilize the teachings of Geissinger in the Case, Hou, and Childe system in order to provide a secure system and save resource.
Regarding claim 11, Case, Hou, Childe, and Geissinger disclose the apparatus as described in claim 10. Case, Hou, Childe, and Geissinger further disclose
the access control circuit, in response to a second command from a central processing unit (CPU), to configure the compression circuit to perform a first compression mode in response to a first key ID, wherein the first key ID is associated with the accelerator (Geissinger: [0111]: a query is received by a document store from a client that specifies at least one database operation implicating documents within the document store; the scanned compressed objects are decompressed using the corresponding decompression keys). Therefore, the limitations of claim 11 are rejected in the analysis of claim 10 above, and the claim is rejected on that basis.
Regarding claims 22 and 26, the limitations of claims 22 and 26 are rejected in the analysis of claim 10 above and these claims are rejected on that basis.
Regarding claim 29, the limitations of claim 29 are rejected in the analysis of claim 11 above and this claim is rejected on that basis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jacobs et al. (US 11,914,737 B2). Receive a request to access data; decrypting, decompressing, and authenticating, using the set of cluster keys and the segments keys, data.
Matsubara et al. (US 9,462,078 B2). Store the identifier representing the information processing device in association with an encryption key used by the information processing device.
Cunningham (US 9,912,644 B2). Compress the data and sign the data using the private key.
Wong et al. (US 2013/0166922 A1). To decrypt the compressed data from application, access the session key established with the application.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYLEE J HUANG whose telephone number is (571)272-0080. The examiner can normally be reached Monday-Friday 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joon H Hwang can be reached on 571-272-4036. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaylee Huang
11/01/2025
/KAYLEE J HUANG/Primary Examiner, Art Unit 2447
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