DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/17/2025 has been entered.
Response to Arguments
Applicant's arguments filed 6/17/2025 have been fully considered but they are not persuasive.
The double patenting rejection is maintained.
The rejection of at least claim(s) 1 and 15 under 35 U.S.C. 102(a)(1) as unpatentable over Otsuka et al. is maintained.
A) Applicant argues that “As an initial matter, the Office Action admits that "Otsuka et al. discloses the claimed invention except for the capacitor parameter is an equivalent series resistance," and cites Horie to cure this deficiency. Specifically, the Office Action alleges that "Horie et al. disclose that it is well known in the art to reduce variation in the internal resistance of capacitors," and that "[i]t would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor device of Otsuka et al. so that the capacitor parameter is an equivalent series resistance, since such a modification would voltage can be applied to each capacitor evenly." Applicant respectfully disagrees.
Horie, for instance, is allegedly directed to "[a] plurality of unit capacitors are connected together in parallel into a capacitor block and the capacitor blocks are connected together in series." (Horie at 1 [0005]) (emphasis added). Specifically, Horie teaches that connecting the supercapacitors in series leads to "variation in the capacitance and the internal resistance of each electric double layer capacitor connected in series." (Horie at 1 [0010]). Therefore, Applicant first respectfully submits that as Horie teaches the benefits of connecting the supercapacitors in parallel, that one of ordinary skill in the art would not be motivated to look to Horie based on the disclosure of Otsuka, at least because Otsuka teaches to connect the plurality of capacitive elements (11) in series.
- It is submitted that Otsuka et al. explicitly states [0015], “Thereby, all the series capacitive element blocks (10) are constituted by the capacitive elements (11) having the same capacitance” (see also claim 3).
Because supercapacitors are manufactured with inherent tolerances, the only way this can be true is if each individual capacitor was tested and matched. Therefore, “a ratio of the second parameter value (capacitance) to the first parameter value (capacitance) is 1.0”.
- In response to applicant's argument that the references fail to show certain features of the invention (with regard to at least independent claims 1 and 15), it is noted that the features upon which applicant relies (i.e., wherein the first parameter is an equivalent series resistance) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s arguments with respect to claim(s) 7-8, 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has not traverse the examiner’s assertion of official notice in the response filed 6/17/2025 and the well-known in the art statement is taken to be admitted prior art (see MPEP 2144.03).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 6-12, 14-18, 20-24 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 and 13-22 of U.S. Patent No. 11,133,133 (‘133). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, ‘133 discloses a supercapacitor module comprising: a first supercapacitor having a first parameter value for a capacitor parameter in a first test condition (C:1, L: 1-3), wherein the capacitor parameter is a leakage current, an equivalent series resistance, or a capacitance (C:5, C: 9); and a second supercapacitor having a second parameter value for the capacitor parameter in about the first test condition, a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (C: 1, L: 4-8); wherein the first supercapacitor and the second supercapacitor are connected in series (C: 12).
Regarding claim 2, '133 discloses the ratio of the second parameter value to the first parameter value is from about 0.85 to about 1.15 (C: 2, L: 1-2).
Regarding claim 3, '133 discloses the ratio of the second parameter value to the first parameter value is from about 0.9 to about 1.1 (C:3, L: 1-2).
Regarding claim 5, '133 discloses the parameter is a leakage current (C:4, L:1- 2).
Regarding claim 6, '133 discloses the leakage current is greater than 23.75 microamps and less than about 26.25 microamps at an applied DC voltage of about 5 volts and a temperature of about 25 degrees C (C:5, L: 1-4).
Regarding claim 7, '133 discloses the capacitor parameter is an equivalent series resistance (C: 6, L: 1-2).
Regarding claim 8, '133 discloses the equivalent series resistance is greater than about 61.75 mohms and less than about 68.25 mohms at an applied AC voltage of about 10 mV at a frequency of about 1000 Hz and at a temperature of about 25°C (C: 7, L: 1-5).
Regarding claim 9, '133 discloses the capacitor parameter is capacitance (C: 8, L: 1-2).
Regarding claim 10, '133 discloses the capacitance is greater than about 4.75 F and less than about 5.25 F at a temperature of about 25 degrees C (C:9, L: 1-3).
Regarding claim 11, '133 discloses the first test condition includes a test voltage (C: 10, L:1-2).
Regarding claim 12, '133 discloses the first test condition includes a test temperature (C: 11, L: 1-2).
Regarding claim 14, '133 discloses a first supercapacitor has a third parameter value for a second capacitor parameter in a second test condition (C: 13, L:1-3); the second supercapacitor has a fourth parameter value for the second capacitor parameter in about the second test condition (C: 13, L: 4-5); and a second ratio of the fourth parameter value to the third parameter value is from about 0.8 to about 1.2 (C: 13, L: 6-10).
Regarding claim 15, '133 discloses a method for manufacturing a supercapacitor module from a first supercapacitor and a second supercapacitor, the first supercapacitor having a first parameter value for a capacitor parameter in a first test condition (C: 14,L: 1-5), wherein the capacitor parameter is a leakage current, and equivalent series resistance, or a capacitance (C:15, C: 16, C:17); the method comprising: selecting the second supercapacitor based on the second capacitor having a second parameter value for the capacitor parameter in about the first test condition, a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (C: 14, L: 6-10), further comprising connecting the first supercapacitor in series with the second supercapacitor (C: 19).
Regarding claim 16, '133 discloses the capacitor parameter is leakage current (C: 15, L: 1-2).
Regarding claim 17, '133 discloses the capacitor parameter is an equivalent series resistance (C: 16, L: 1-2).
Regarding claim 18, '133 disclose the capacitor parameter is capacitance (C: 17, lines 1-2).
Regarding claim 20, '133 discloses a voltage across the first capacitor is not adjusted using a balancing circuit (C: 18, L: 1-2).
Regarding claim 21, '133 discloses connecting the first supercapacitor in series with the second supercapacitor without a balancing circuit (C: 19, L: 1-3).
Regarding claim 22, '133 discloses the second ratio of the second parameter value to the first parameter value is from about 0.9 to about 1.1 (C: 20, L: 1-3).
Regarding claim 23, '133 discloses the second ratio of the second parameter value to the first parameter value is from about 0.95 to about 1.05 (C: 21, L: 1-3).
Regarding claim 24, '133 disclose the first supercapacitor has a third parameter value for a second capacitor parameter in a second test condition (C: 22, L: 1-3); the second supercapacitor has a fourth parameter value for the second capacitor parameter at about the second test condition; and selecting the second supercapacitor is further based on a second ratio of the fourth parameter value to the third parameter value being from about 0.8 to about 1.2 (C: 22, L: 4-9).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 9, 11-12, 14-16, 18, and 22-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otsuka et al. (JP 2010017053).
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Regarding claim 1, Otsuka et al. disclose a supercapacitor module comprising:
a first supercapacitor (11) having a first parameter value (capacitance or leakage current – claim 3, [0015], [0044]) for a capacitor parameter in a first test condition (voltage - fig. 1, 5, and 6); wherein the capacitor parameter is a leakage current, an equivalent series resistance, or a capacitance (capacitance or leakage current – claim 3, [0015], [0044]) and
a second supercapacitor (11) having a second parameter value (capacitance or leakage current & capacitance) for the capacitor parameter in about the first test condition, a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (1 – all capacitor elements 11 have the same capacitance or the leakage current is within 10 % of each other in group C – (claim 3, [0015], [0044]); wherein the first supercapacitor and the second supercapacitor are connected in series (fig. 1 – contained in 10).
Regarding claim 2, Otsuka et al. disclose the ratio of the second parameter value to the first parameter value is from about 0.85 to about 1.15 ( element 11 – capacitors have same capacitance- claim 3, [0015]).
Regarding claim 3, Otsuka et al. disclose the ratio of the second parameter value to the first parameter value is from about 0.9 to about 1.1 ( element 11 – capacitors have same capacitance – claim 3, [0015]).
Regarding claim 5, Otsuka et al. disclose the capacitor is a leakage current [0044])
Regarding claim 9, Otsuka et al. disclose the capacitor parameter is a capacitance ([0015], claim 3).
Regarding claim 11, Otsuka et al. disclose the first test condition includes a test voltage (inherent for testing for capacitance and/or leakage current).
Regarding claim 12, Otsuka et al. disclose the first test condition includes a test temperature (all test conditions occur at a temperature).
Regarding claim 14, Otsuka et al. disclose the first supercapacitor has a third parameter value for a second capacitor parameter (leakage current or capacitance) in a second test condition;
the second supercapacitor has a fourth parameter value (leakage current or capacitance) for the second capacitor parameter in about the second test condition; and
a second ratio of the fourth parameter value to the third parameter value is from about 0.8 to about 1.2. (1 – all capacitor elements 11 have the same capacitance or the leakage current is within 0.9 to 1.1 of each other in group C – (claim 3, [0015], [0044]).
Regarding claim 15, Otsuka et al. disclose a method for manufacturing a supercapacitor module from a first supercapacitor (11) and a second supercapacitor (11),
the first supercapacitor (11) having a first parameter value for a capacitor parameter (capacitance or leakage current) in a first test condition (at least voltage), the method comprising:
selecting the second supercapacitor (11) based on the second capacitor having a second parameter value for the capacitor parameter in about the first test condition (at least voltage), a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (1 – all capacitor elements 11 have the same capacitance or the leakage current is within 10 % of each other in group C – (claim 3, [0015], [0044]).
Regarding claim 16, Otsuka et al. disclose the capacitor parameter is a leakage current [0044].
Regarding claim 18, Otsuka et al. disclose the capacitor parameter is a capacitance ([0015], claim 3).
Regarding claim 22, Otsuka et al. disclose the second ratio of the second parameter value to the first parameter value is from about 0.9 to about 1.1 ([0015], [0044], claim 3).
Regarding claim 23, Otsuka et al. disclose the second ratio of the second parameter value to the first parameter value is from about 0.95 to about 1.05 ([0015], claim 3).
Regarding claim 24, Otsuka et al. disclose the first supercapacitor has a third parameter value for a second capacitor parameter in a second test condition (leakage current or capacitance);
the second supercapacitor has a fourth parameter value for the second capacitor parameter at about the second test condition (leakage current of capacitance); and
selecting the second supercapacitor is further based on a second ratio of the fourth parameter value to the third parameter value being from about 0.8 to about 1.2 ([0015], [0044], claim 3).
Claim(s) 1, 7, 15, 17, and 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (CN 105914823).
Regarding claim 1, Zhang et al. disclose a module comprising a first supercapacitor (C1 – Translation - P: 2, P:5) having a first parameter value for a capacitor parameter in a first test condition (ESR, leakage current, capacitance, etc.), wherein the capacitor parameter is leakage current, ESR, or capacitance (Translation P:2, P:5); and
a second supercapacitor (C2 – Translation P:2, P:5) having a second parameter value for the capacitor parameter in about the first test condition (ESR, leakage current, capacitance), a ratio of the second parameter value to the first parameter value being 1.0 (Translation – P: 2, P:5 - supercapacitors are identical – ESR, leakage current, capacitance, etc.);
wherein the first supercapacitor (C1) and the second supercapacitor (C2) are connected in series (Translation P:2, P:6).
Supercapacitors are manufactured with inherent tolerances. For Zhang et al. to use identical supercapacitors, the capacitors need to be individually tested and matched. Therefore, “a ratio of the second parameter value (ESR) to the first parameter value (ESR) is 1.0”.
Regarding claim 7, Zhang et al. disclose the capacitor parameter is ESR (all supercapacitors are identical – Translation - P: 2, P: 6).
Regarding claim 15, Zhang et al. disclose a method for manufacturing a supercapacitor module from a first supercapacitor (C1) and a second supercapacitor (C2), the first supercapacitor having a first parameter value for a capacitor parameter in a first test condition (Translation – P: 2, P: 5), wherein the capacitor parameter is a leakage current, and ESR, or a capacitance (Translation – P: 2, P: 5); the method comprising: selecting the second supercapacitor (C2) based on the second capacitor having a second parameter value for the capacitor parameter in about the first test condition, a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (1 – identical to C1), further comprising connecting the first supercapacitor in series with the second supercapacitor (Translation – P: 2, P: 6).
Supercapacitors are manufactured with inherent tolerances. For Zhang et al. to use identical supercapacitors, the capacitors need to be individually tested and matched. Therefore, “a ratio of the second parameter value (ESR) to the first parameter value (ESR) is 1.0”.
Regarding claim 17, Zhang et al. disclose the capacitor parameter is ESR (all supercapacitors are identical – Translation - P: 2, P: 6).
Regarding claim 20, Zhang et al. disclose a voltage across the first capacitor (C1) is not adjusted using a balancing circuit.
Regarding claim 21, Zhang et al. disclose connecting the first supercapacitor in series (C1) with the second supercapacitor (C2) without a balancing circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otsuka et al. (JP 2010017053) in view of Applicant’s Admitted Prior Art (AAPA).
Regarding claim 6, Otsuka et al. disclose the claimed invention except for the leakage current is greater than 23.75 microamps and less than about 26.25 microamps at an applied DC voltage of about 5 volts and a temperature of about 25 degrees C.
AAPA discloses it is known in the supercapacitor art to minimize leakage current.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the supercapacitor module of Otsuka et al. so that the leakage current is greater than 23.75 microamps and less than about 26.25 microamps at an applied DC voltage of about 5 volts and a temperature of about 25 degrees C, since such a modification would form a supercapacitor module with low leakage current.
Regarding claim 10, Otsuka et al. disclose the claimed invention except the capacitance is greater than about 4.75 F and less than about 5.25 F at a temperature of about 25°C.
AAPA discloses that it is known in the supercapacitor art to form a supercapacitor having a capacitance that is greater than about 4.75 F and less than about 5.25 F at a temperature of about 25°C.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the supercapacitor module of Otsuka et al. so that the capacitance is greater than about 4.75 F and less than about 5.25 F at a temperature of about 25°C, since such a modification would form a supercapacitor module having desired capacitance.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 105914823).
Regarding claim 8, Zhang et al. disclose the claimed invention except for the equivalent series resistance is greater than about 61.75 mohms and less than about 68.25 mohms at an applied AC voltage of about 10 mV at a frequency of about 1000 Hz and at a temperature of about 25°C.
It is known in the supercapacitor art to form a supercapacitor having equivalent series resistance is greater than about 61.75 mohms and less than about 68.25 mohms at an applied AC voltage of about 10 mV at a frequency of about 1000 Hz and at a temperature of about 25°C.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the supercapacitor module so that the equivalent series resistance is greater than about 61.75 mohms and less than about 68.25 mohms at an applied AC voltage of about 10 mV at a frequency of about 1000 Hz and at a temperature of about 25°C, since such a modification would form a supercapacitor module with low ESR.
Claim(s) 15, 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cowperthwaite et al. (US 2013/0266826) in view of Otsuka et al. (JP 2010017053).
Regarding claim 15, Cowperthwaite et al. disclose a method for manufacturing a supercapacitor module from a first supercapacitor (120A) and a second supercapacitor (120B),
the first supercapacitor (120A) having a first parameter value for a capacitor parameter (capacitance) in a first test condition (at least voltage), the method comprising:
selecting the second supercapacitor (120A) based on the second capacitor having a second parameter value for the capacitor parameter (capacitance) in about the first test condition (at least voltage).
Cowperthwaite et al. disclose the claimed invention except for a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2.
Otsuka et al. disclose a method for manufacturing a supercapacitor module from a first supercapacitor (11) and a second supercapacitor (11),
the first supercapacitor (11) having a first parameter value for a capacitor parameter (capacitance or leakage current) in a first test condition (at least voltage), the method comprising:
selecting the second supercapacitor (11) based on the second capacitor having a second parameter value for the capacitor parameter in about the first test condition (at least voltage), a ratio of the second parameter value to the first parameter value being from about 0.8 to about 1.2 (1 – all capacitor elements 11 have the same capacitance– (claim 3, [0005], [0044])).
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the supercapacitor module of Cowperthwaite et al. using supercapacitor elements having the same capacitance, since such a modification would form a supercapacitor module having desired capacitance.
Regarding claim 20, Cowperthwaite et al. disclose a voltage across the first capacitor is not adjusted using a balancing circuit (fig. 2B).
Regarding claim 21, Cowperthwaite et al. disclose comprising connecting the first supercapacitor in series [0053] with the second supercapacitor [0053] without a balancing circuit (fig. 2B).
Conclusion
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/ERIC W THOMAS/Primary Examiner, Art Unit 2848
ERIC THOMAS
Primary Examiner
Art Unit 2848
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