DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed August 11th, 2025. Claims 1-17 are pending, of which claims 1-17 are currently rejected. Claims 18-20 have been cancelled by Applicant.
Response to Arguments
The amendment filed August 11th, 2025 has been entered. Claims 1-17 remain pending in the application. Applicant’s amendments to the Claims and Specification have overcome each and every objection previously set forth in the Non-Final Office Action mailed April 9th, 2025.
Claim Rejections – 35 USC § 112
A new rejection under 35 USC § 112(d) has been made as necessitated by the amendments to claim 12.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. New grounds of rejection have been made by Examiner that are necessitated by the amendments. See Claim Rejections - 35 USC § 103.
Remarks
Examiner points out that parts of claim 12 as originally presented have been removed. Examiner wishes to indicate that in order for properly amend claims, any parts that are removed are to be indicated with a strikethrough, instead of entirely deleting limitations. Additionally, with the current amendment of claim 12, it does not further limit claim 11 in any way (which is further discussed in Claim Rejections - 35 USC § 112). Therefore, for prior art purposes, claim 12 is rejected for the same reasons as claim 11, as claim 12 recites the same invention as claim 11
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 12 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 12 does not further limit the recited limitations of claim 11, upon which claim 12 depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pribbernow (US 2007/0011642 A1), further in view of Jacob (Yaakov) et al. (US 2020/0097442 A1) (hereinafter “Jacob”), further in view of Cohen et al. (US 2019/0102671 A1) (hereinafter “Cohen”).
Regarding claim 1, Pribbernow teaches a way of implementing an application-specific integrated circuit in a field programmable gate array (FPGA) (see Pribbernow: ¶ 0031, 0032, 0040, 0042; Fig. 1, 8, 9).
Jacob teaches the ASIC implementing the system of Fig. 2 including a systolic array and a controller for controlling the systolic array (see Jacob: ¶ 0107; Fig. 2).
The system of Fig. 2 taught by Jacob corresponds to the main fixed function circuitry of claim 1 while the systolic array controller corresponds to the CL-IP module taught by Pribbernow which in turn corresponds to the support processor of claim 1.
Jacob’s controller (corresponding to Pribbernow’s CL-IP module, corresponding to the support processor of claim 1) is outside the systolic array and therefore teaches the main fixed function circuitry of the ASIC with an external support processor.
It would be obvious to implement Jacob’s ASIC as disclosed in Fig. 2 using Pribbernow’s ASIC fabrication method including bringing in the systolic array and systolic array controller as this would be using Pribbernow for its intended purpose. This would provide the advantage provided by Jacob in regards to the controller’s cycle-to-cycle operation, allowing for a more flexible or programmable approach and the system being able to react in real-time (Jacob: ¶ 0053).
This combination results in Jacob’s teaching being implemented in Pribbernow’s programmable logic within the CL-IP module which comprises of embedded programmable fabric (Pribbernow: Fig. 1 element 118), allowing for programmable flexibility because the control can be reprogrammed.
Pribbernow in view of Jacob does not explicitly teach the following:
wherein the support processor comprises an embedded programmable fabric configured to at least manipulate data between stages of a neural network used to perform deep learning operations (Cohen: ¶ 0034 programmable IP or ASIP programmable core i.e., programmable fabric that is used to manage execution of operations of neural network layers as discussed in ¶ 0070; ¶ 0112 managing of execution of operations of neural network layers includes data manipulation between the neural network layers i.e., neural network stages).
It would be obvious to combine the data manipulation between neural network stages as taught by Cohen with the system as taught by Pribbernow in view of Jacob as all teachings are directed towards digital design for configurable systems. This would provide the advantage provided by Cohen in regards to the optimization for accuracy and efficiency (Cohen: ¶ 0112).
Pribbernow in view of Jacob in view of Cohen therefore teaches an apparatus comprising:
main fixed function circuitry operable to perform a main fixed function for the application-specific integrated circuit device; and
a support processor that performs operations outside of the main fixed function of the application-specific integrated circuit device, wherein the support processor comprises an embedded programmable fabric configured to at least manipulate data between stages of a neural network used to perform deep learning operations.
Regarding claim 2, Pribbernow in view of Jacob in view of Cohen further teaches the main fixed function comprising matrix multiplication (see Jacob: ¶ 0051, 0060).
Regarding claim 3, Pribbernow in view of Jacob in view of Cohen further teaches the main fixed function comprising general matrix multiply circuitry (see Jacob: ¶ 0051, 0060).
Regarding claim 4, Pribbernow in view of Jacob in view of Cohen further teaches the main fixed function comprising general matrix vector multiply circuitry (see Jacob: ¶ 0051, 0060). As is known in the art, if the circuitry can carry out matrix multiplication it will also be able to carry out matrix vector multiplication as matrix vector multiplication is simply a special case of general matrix multiplication.
Regarding claim 5, Pribbernow in view of Jacob in view of Cohen teaches the apparatus comprising memory (Pribbernow: Fig. 1 Element 110 corresponding to Jacob: Fig. 2 Element 270).
Regarding claim 6, Pribbernow in view of Jacob in view of Cohen further teaches the apparatus comprising a memory controller that controls the memory (Jacob: Fig. 2 Elements 250 and 280).
Regarding claim 7, Pribbernow implements the memory controller (Fig.2 Elements 250 Data Load and 280 Data Store units) in the programmable fabric of the FPGA (Pribbenow: Fig. 1 Element 118), and therefore Pribbernow in view of Jacob in view of Cohen teaches the memory controller comprising a memory controller-embedded programmable fabric.
Regarding claim 8, in the system of Pribbernow in view of Jacob in view of Cohen, there would be unused programmable circuitry outside of the memory controller. If this available external programmable fabric were redirected to improving the load and store units (memory controller), it would have access to internal functions while also being outside of the memory controller itself. Therefore, Pribbernow in view of Jacob in view of Cohen teaches the memory controller-embedded programmable fabric being physically outside of the memory controller while still having access to internal functions.
Regarding claim 9, Pribbernow in view of Jacob in view of Cohen further teaches a tensor core (Fig. 2 Element 100). Pribbernow implements the systolic array of Jacob (Fig. 2 Element 100) in the FPGA. Therefore, Pribbernow in view of Jacob teaches the support processor comprising a tensor core.
Claims 10 recites the apparatus of claim 6 and is therefore rejected for the same reasons therein.
Claims 11-12 both recite the apparatus of claim 7 and are therefore rejected for at least the same reasons therein.
Regarding claim 13, Pribbernow in view of Jacob in view of Cohen further teaches memory zeroing operations (see Jacob: ¶ 0083). This memory zeroing taught by Jacob would occur in the programmable fabric as Pribbernow implements the memory controller in the programmable fabric of the FPGA. As such, operations of the memory controller would also occur within the same programmable fabric. Therefore, Pribbernow in view of Jacob in view of Cohen teaches memory zeroing operations performed by the programmable fabric of the memory controller.
Regarding claim 14, Pribbernow in view of Jacob in view of Cohen further teaches at least performing memory setting or other arithmetic operations (see Pribbernow: ¶ 0041 “memory sizing”). This memory setting as disclosed by Pribbernow would be performed by the memory controller within the programmable fabric as Pribbernow implements the memory controller in the programmable fabric of the FPGA. Therefore, Pribbernow in view of Jacob in view of Cohen teaches memory setting operations performed by the programmable fabric of the memory controller.
Regarding claim 15, Pribbernow in view of Jacob in view of Cohen teaches a plurality of support processors including the aforementioned support processor (Pribbernow: ¶ 0042 CL-IP modules).
Regarding claim 16, Pribbernow in view of Jacob in view of Cohen teaches at least one of the other support processors aside from the aforementioned support processor comprising an embedded programmable fabric (see Pribbernow: ¶ 0032, 0042; Fig. 1 Element 118). All CL-IP modules would follow the same ASIC implementation method and therefore would have identical structures, including comprising an embedded programmable fabric. Therefore, Pribbernow in view of Jacob in view of Cohen teaches at least one of the other support processors aside from the aforementioned support processor comprising an embedded programmable fabric.
Claim 17 is directed to a method that is practiced by the apparatus of claim 1 and is therefore rejected for at least the same reasons therein.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barik et al. (US 2018/0307980 A1) teaches a compute apparatus for performing machine learning operations using a decode unit in order to schedule operations to one of an array of programmable compute units and a fixed function compute unit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182