DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed August 13th, 2026. Claims 1-17 are pending, of which claims 1-17 are currently rejected.
Response to Arguments
The amendment filed August 13th, 2026 has been entered. Claims 1-17 remain pending in the application.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. New grounds of rejection have been made as necessitated by amendments.
See Claim Rejections Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pribbernow (US 2007/0011642 A1) (hereinafter “Pribbernow”), further in view of Jacob (Yaakov) et al. (US 2020/0097442 A1) (hereinafter “Jacob”), further in view of Cohen et al. (US 2019/0102671 A1) (hereinafter “Cohen”), further in view of Stabrawa et al. (US 2023/0008874 A1) (hereinafter "Strabrawa").
Regarding claim 1, Pribbernow teaches a way of implementing an application-specific integrated circuit in a field programmable gate array (FPGA) (see Pribbernow: ¶ 0031, 0032, 0040, 0042; Fig. 1, 8, 9).
Jacob teaches the ASIC implementing the system of Fig. 2 including a systolic array and a controller for controlling the systolic array (see Jacob: ¶ 0107; Fig. 2).
The system of Fig. 2 taught by Jacob corresponds to the main fixed function circuitry of claim 1 while the Data Load Unit corresponds to the CL-IP module taught by Pribbernow which in turn corresponds to the support processor of claim 1.
Jacob’s Data Load Unit (corresponding to Pribbernow’s CL-IP module, corresponding to the support processor of claim 1) is outside the systolic array and therefore teaches the main fixed function circuitry of the ASIC with an external support processor.
It would be obvious before the effective filing date of the claimed invention to implement Jacob’s ASIC as disclosed in Fig. 2 using Pribbernow’s ASIC fabrication method including bringing in the systolic array and systolic array controller as this would be using Pribbernow for its intended purpose. This would provide the advantage provided by Jacob in regards to the Data Load Unit’s ability to handle a wide array of input types, thereby increasing flexibility of computations (Jacob: ¶ 0051).
This combination results in Jacob’s teaching being implemented in Pribbernow’s programmable logic within the CL-IP module which comprises of embedded programmable fabric (Pribbernow: Fig. 1 element 118), allowing for programmable flexibility because the control can be reprogrammed.
Pribbernow in view of Jacob does not explicitly teach the following:
wherein the support processor comprises an embedded programmable fabric configured to at least manipulate data between the main fixed function circuitry and a memory,
wherein data manipulation includes at least one of memory zeroing and using prefetcher hints.
However, Cohen teaches:
wherein the support processor comprises an embedded programmable fabric configured to at least manipulate data between the main fixed function circuitry and a memory (Cohen: ¶ 0034 programmable IP or ASIP programmable core i.e., programmable fabric that is used to manage execution of operations of neural network layers as discussed in ¶ 0070; ¶ 0112 managing of execution of operations of neural network layers includes data manipulation between the neural network layers i.e., neural network stages; Fig. 3a support processor as ASIP 308 contained within CNNA 300, CNNA 300 corresponding to Data Load Unit 250 of Jacob Fig. 2, and memory being Fig. 2 270 of Jacob).
It would be obvious before the effective filing date of the claimed invention to combine the data manipulation between neural network stages as taught by Cohen with the system as taught by Pribbernow in view of Jacob as all teachings are directed towards digital design for configurable systems. This would provide the advantage provided by Cohen in regards to the optimization for accuracy and efficiency (Cohen: ¶ 0112).
Pribbernow in view of Jacob in view of Cohen does not explicitly teach:
wherein data manipulation includes at least one of memory zeroing and using prefetcher hints.
However, Stabrawa teaches:
wherein data manipulation includes at least one of memory zeroing (Stabrawa: ¶ 0169; ¶ 0205) and using prefetcher hints (Stabrawa: ¶ 0201).
It would be obvious before the effective filing date of the claimed invention to combine the specific techniques of data manipulation as taught by Stabrawa with the apparatus as taught by Pribbernow in view of Jacob in view of Cohen because all teachings are directed towards programmable devices. One with ordinary skill in the art would be motivated to combine the teachings because employing these techniques may make memory processes and allocation more quickly and handling of memory request are more efficient (Stabrawa: ¶ 0207).
Pribbernow in view of Jacob in view of Cohen therefore teaches an apparatus comprising:
main fixed function circuitry operable to perform a main fixed function for the application-specific integrated circuit device; and
a support processor that performs operations outside of the main fixed function of the application-specific integrated circuit device, wherein the support processor comprises an embedded programmable fabric configured to at least manipulate data between the main fixed function circuitry and a memory,
wherein data manipulation includes at least one of memory zeroing and using prefetcher hints.
Regarding claim 2, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches the main fixed function comprising matrix multiplication (see Jacob: ¶ 0051, 0060).
Regarding claim 3, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches the main fixed function comprising general matrix multiply circuitry (see Jacob: ¶ 0051, 0060).
Regarding claim 4, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches the main fixed function comprising general matrix vector multiply circuitry (see Jacob: ¶ 0051, 0060). As is known in the art, if the circuitry can carry out matrix multiplication it will also be able to carry out matrix vector multiplication as matrix vector multiplication is simply a special case of general matrix multiplication.
Regarding claim 5, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches the apparatus comprising the memory (Cohen: Fig. 3A local memory 316).
Regarding claim 6, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches the apparatus comprising a memory controller that controls the memory (Cohen: Fig. 3a 300 CNNA as memory controller, operations of CNNA further discussed in ¶ 0069; in combining Pribbernow, Jacob and Cohen, the CNNA as Data load Unit 250 of Jacob would control the data memory 270).
Regarding claim 7, the memory controller CNNA 300 shown in Fig. 3a of Cohen comprises the ASIP 308, the ASIP 308 containing the embedded programmable fabric as discussed in ¶ 0070.
Regarding claim 8, the memory controller CNNA 300 as shown in Fig. 3a is outside of the programmable core ASIP i.e., the support processor containing the embedded programmable fabric (Cohen: Fig. 3a) but has access to internal functions of the memory controller as the ASIP plays a role in the data being input and output to the CNNA 300 from memory as shown by the communication occurring between the ASIP, DMA, the local memory, and the CNN (Cohen: also discussed in ¶ 0069 - ¶ 0072 and Fig. 3b as well).
Regarding claim 9, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches a tensor core (Fig. 2 Element 100). Pribbernow implements the systolic array of Jacob (Fig. 2 Element 100) in the FPGA. Therefore, Pribbernow in view of Jacob teaches the support processor comprising a tensor core.
Regarding claim 10, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches the support processor being implemented in field programmable logic as discussed with respect to claim 1.
Regarding claim 11, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches:
The apparatus of claim 10, wherein the main fixed function circuitry is implemented in application specific integrated circuitry (Jacob teaches the ASIC implementing the system of Fig. 2 including a systolic array and a controller for controlling the systolic array, see Jacob: ¶ 0107; Fig. 2).
Regarding claim 12, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches:
The apparatus of claim 1, wherein the embedded programmable fabric is configured to manipulate the data between stages of a neural network used to perform deep learning operations (Cohen: ¶ 0034 programmable IP or ASIP programmable core i.e., programmable fabric that is used to manage execution of operations of neural network layers as discussed in ¶ 0070; ¶ 0112 managing of execution of operations of neural network layers includes data manipulation between the neural network layers i.e., neural network stages).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Regarding claim 13, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches memory zeroing operations (see Jacob: ¶ 0083). This memory zeroing taught by Jacob would occur in the programmable fabric as Pribbernow implements the memory controller in the programmable fabric of the FPGA. As such, operations of the memory controller would also occur within the same programmable fabric. Therefore, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches memory zeroing operations performed by the programmable fabric of the memory controller.
Regarding claim 14, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa further teaches at least performing memory setting or other arithmetic operations (see Pribbernow: ¶ 0041 “memory sizing”). This memory setting as disclosed by Pribbernow would be performed by the memory controller within the programmable fabric as Pribbernow implements the memory controller in the programmable fabric of the FPGA. Therefore, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches memory setting operations performed by the programmable fabric of the memory controller.
Regarding claim 15, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches a plurality of support processors including the aforementioned support processor (Pribbernow: ¶ 0042 CL-IP modules).
Regarding claim 16, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches at least one of the other support processors aside from the aforementioned support processor comprising an embedded programmable fabric (see Pribbernow: ¶ 0032, 0042; Fig. 1 Element 118). All CL-IP modules would follow the same ASIC implementation method and therefore would have identical structures, including comprising an embedded programmable fabric. Therefore, Pribbernow in view of Jacob in view of Cohen in view of Stabrawa teaches at least one of the other support processors aside from the aforementioned support processor comprising an embedded programmable fabric.
Claim 17 is directed to a method that is practiced by the apparatus of claim 1 and is therefore rejected for at least the same reasons therein.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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