DETAILED ACTION
1. This office action is in response to the Application No. 17484918 filed on 12/03/2025. Claims 1-22 are presented for examination and are currently pending.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on
12/03/2025 has been entered.
Response to Arguments
4. The claim amendments of 12/03/2025 has overcome the 112(f) claim interpretation of 08/05/2025. As a result, the 112(f) has been withdrawn.
On page 8 of the remarks, the Applicant argued that “As evident from the claim language, the presently claimed apparatus includes interference circuitry, machine-readable instructions, and at least one processor configured to implement a multi-resolution, dual-encoder segmentation pipeline. The processor: (i) encodes a full- resolution input image via a first network to generate a first feature map at a first downscaled resolution; (ii) downscales the input image and encodes the resulting lower-resolution version via a second network to generate a second feature map having a greater number of channels at a second downscaled resolution; (iii) upscales the second feature map to the first downscaled resolution; (iv) concatenates the first and second feature maps; (v) applies a convolution to the concatenated output; and (vi) generates, via segmentation-head circuitry, a pixel-level segmentation class map. This dual-network, dual-resolution feature-fusion architecture is central to the claimed invention and is neither taught nor suggested by any cited reference”.
The argument that “This dual-network, dual-resolution feature-fusion architecture is central to the claimed invention and is neither taught nor suggested by any cited reference” is not persuasive.
The Examiner notes that the claimed limitation require “processor circuit to … encode an input image via a first network … encode the second image via a second network”. However, even though a “dual-network, dual-resolution feature-fusion architecture” is not the recited claim language in the independent claims, Cheng teaches encoder block 210-1 [0102] as the first network and encoder blocks 210-2 and 212-2 [0103] as second network. This reads on the claimed first network and second network, or the argued dual-network. The Examiner notes that the broadest reasonable interpretation of “a first network” and “a second network” is taught by Cheng since the Applicant has not provided a definition of “a first network” and “a second network”. In addition, Cheng’s teaching encoder block 210-1 [0102] as the first network and encoder blocks 210-2 and 212-2 [0103] as second network has been broadly interpreted as encoding components of the apparatus, since the Applicant has not claimed for instance, a first neural network and second neural network to distinguish over Cheng.
Furthermore, the argument above is not persuasive because even though a “dual-network, dual-resolution feature-fusion architecture” has not been claimed has argued above, Cheng teaches a feature map 440 with a scale (otherwise referred to as “resolution”) corresponding to feature map 422 [0091]; The emphasized feature maps are upsampled to achieve a common scale (i.e. resolution), respectively, and are fed into spatial feature transformer 440 [0095].
On page 9 of the remarks, the Applicant argued that “In the Final Office Action, specifically on pages 5-16, the Examiner asserts that Cheng, in view of Asama (and further in view of Yuan, Li, and Shigenobu for certain claims), would have rendered the claimed architecture obvious. Respectfully, the cited references do not disclose, suggest, or motivate the claimed arrangement. The rejection is premised on an improper reconstruction of Applicant's invention using hindsight.”
It is noted that in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
On page 9 of the remarks, the Applicant argued that “A careful reading of Cheng shows that its semantic segmentation architecture employs a single encoder that internally branches into multiple pathways. Importantly, these are not independent networks, but simply internal hierarchical branches within one unified encoder. Cheng does not process differently scaled versions of the same input via separate encoder circuits, nor does it teach or suggest such an arrangement. The Examiner's assertion that Cheng teaches or suggests "two encoders" is unsupported because Cheng's branches are tightly integrated components of a single co-trained model, driven by internal feature abstractions rather than distinct external inputs. A person of ordinary skill in the art would not interpret Cheng as disclosing dual, stand-alone encoder networks”.
The argument above is not persuasive because even though Cheng teaches a multi-branch cascaded subnetwork that includes an encoder (abstract), Cheng’s encoder block 210-1 in Fig. 2 reads on the claimed limitation of “encode an input image via a first network” and Cheng’s encoder blocks 210-2 and 212-2 [0103] reads on the claimed limitation of “encode the second image via a second network”. The Examiner notes Cheng’s encoder block 210-1 is an encoder because it encodes an input image and Cheng’s encoder block 210-2 and 212-2 is also an encoder because it encodes an input image.
On page 9 of the remarks, the Applicant argued that “Asama, by contrast, occupies a different technical domain entirely. Asama is directed to hardware-efficient hybrid IIR-FIR convolution blocks, skip-line compression schemes, and low- level filter optimizations. Asama provides no teachings regarding encoder network topology, multi-resolution processing pipelines, or the fusion of independently generated feature maps. Nothing in Asama suggests architectural changes to the structure or function of an image encoder.
The argument above is not persuasive because while Asama does not disclose all the features of the present claimed invention, Asama is used as a teaching reference, and therefore, it is not necessary for this secondary reference to contain all the features of the presently claimed invention. Rather Asama in combination with Cheng as the primary reference discloses the presently claimed invention.
Further on page 9 of the remarks, the Applicant argued that “The Examiner's conclusion that Asama may be combined with Cheng "to improve efficiency" is conclusory, lacks evidentiary support, and does not establish a teaching, suggestion, or motivation to modify Cheng's architecture into the dual-encoder, dual-resolution structure required by the claims. A valid rationale under MPEP §2143 must arise from the references themselves, not from the invention disclosed in Applicant's specification”.
The argument above is not persuasive because the combination of references did not arise from instant specification of Applicant, but rather a person of ordinary skill in the art would have modified Cheng’s teachings with the secondary reference Asama based on beneficial teachings of Asama.
Cheng as primary reference teaches feature maps are upsampled to achieve a common scale (i.e. resolution) [0095] and feature map is downsampled [0104], while Asama as secondary reference similarly teaches the upscaler 220A upsamples the feature map [0035], downscaled image information may include … feature maps (The Examiner notes that downscaling is downsampling) [0044], as a result, it would have been obvious to a person having ordinary skill in the art to have modified Cheng with Asama for the benefit of downscaling the image in response to detecting that a resolution of the received image exceeds a predetermined threshold (Asama [0067])
On pages 9-10 of the remarks, the Applicant argued that “Even assuming, purely for the sake of argument, that Cheng and Asama could be combined, the combined system would still fall far short of the claimed invention. Cheng's encoder, even when viewed in combination with Asama's convolution filters, does not produce two independently constructed feature maps, one from a full-resolution encoder and one from a separately operating downscaled encoder with a greater number of channels. Nor does either reference suggest upscaling one independently generated feature map to match the resolution of another before concatenation and processing. The cited art fails to teach or suggest generating multi-resolution features from independent encoder networks, or subsequently fusing such features after resolution alignment. Asama, focused purely on convolutional kernel optimization, adds no missing architectural features”.
The argument above is not persuasive because the Applicant is arguing about a claim language that is not claimed. The instant claims does not appear to provide specific claims directed to “convolution filters” or “full-resolution encoder”.
Furthermore, in response to applicant's argument against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir.1986).
In addition, even though Asama as secondary reference teaches convolutional kernels optimization as argued above, Cheng as primary reference similarly teaches convolutional kernels [0081], as a result, both references are analogous art in the same field of endeavor. So it would have been obvious to a person of ordinary skill in the art to modify Cheng with the teachings of Asama.
On page 10 of the remarks, the Applicant argued that “A person of ordinary skill in the art would not have reasonably expected to decompose Cheng's single encoder into two stand-alone encoders that accept different-resolution inputs and then recombine their outputs, particularly given the tight integration and co-training that Cheng's branches require and the fact that Cheng's design is specifically optimized for point-cloud processing, not multi-resolution image fusion. Implementing such a fundamental architectural redesign would require knowledge of Applicant's invention to know where and how to divide the network, what channel relationships to impose, and how to align the respective feature outputs for subsequent fusion. The proposed combination therefore depends on knowing the Applicant's solution in advance, which is precisely the hindsight reconstruction that KSR and In re Rouffet forbid”.
The Applicant’s arguments above about hindsight reasoning is not persuasive because the reason to combine was based on what would have been obvious to a person having ordinary skill in the art before the effective filing data of the claimed invention. Cheng as primary reference discloses feature maps are upsampled to achieve a common scale (i.e. resolution) [0095] and feature map is downsampled [0104], while Asama as secondary reference similarly teaches the upscaler 220A upsamples the feature map [0035], downscaled image information may include … feature maps (The Examiner notes that downscaling is downsampling) [0044], as a result, it would have been obvious to a person having ordinary skill in the art to have modified Cheng with Asama for the benefit of downscaling the image in response to detecting that a resolution of the received image exceeds a predetermined threshold (Asama [0067]).
Furthermore, the Applicant is arguing about claim language that is not claimed, for example, “decompose”.
On page 10 of the remarks, the Applicant argued that “Because neither Cheng nor Asama, alone or in combination, teaches or suggests the dual- encoder, dual-resolution, dual-feature-map architecture now explicitly recited in amended claim 1, and because the Examiner's rationale for combining the references lacks the necessary evidentiary foundation and relies on hindsight, the §103 rejection is improper and should be withdrawn”.
On page 10 of the remarks, the Applicant argued that “In view of the above, Applicant respectfully submits that independent claim 1 is novel and non-obvious over the cited art. Independent claims 8, 15, and 22 recite corresponding limitations, mutatis mutandis, and are likewise patentable. Dependent claims 2-14 and 16-21, by virtue of their dependency, are also patentable over the references of record”.
The argument above is not persuasive because it is prima facie obvious to modify Cheng’s teaching of a convolutional neural network with Asama’s similar teaching of a convolutional neural network because the idea of combining them flows logically from the similar teachings taught in the prior art.
It is noted that in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Furthermore, the Applicant’s arguments about patentability is unpersuasive because rather than providing arguments about how the language of the claims patentably distinguishes from Cheng modified by Asama, the Applicant is arguing about dual-network, dual-resolution, feature-fusion architecture which are not the specific language recited in the claims. As a result, independent claims 1, 8, 15, 22 and the claims that depend on them are not patentable because they are obvious over Cheng in view of Asama.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claims 1-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “interference circuitry”.
The limitations “interference circuitry” does not have basis in the original disclosure. The Applicant’s specification at [0005], [0008] and [0010] describes “bottleneck extender circuitry”, “imaging network circuitry”, “convolution circuitry”, “processor circuitry”. The claimed limitations “interference circuitry” is different from circuitry that is stated in the specification. Therefore, the specification does not provide written description support for “interference circuitry”.
Claims 2-6 that are not specifically mentioned are rejected due to dependency.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites “interference circuitry”. It is not clear what is meant by interference circuitry.
For the purpose of examination, the “interference circuitry” has been interpreted as interface circuitry.
Claims 2-6 that are not specifically mentioned are rejected due to dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-6, 8-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20230035475 filed 07/16/2021) in view of Asama et al. (US20200074691 filed 11/05/2019)
Regarding claim 1, Cheng teaches an apparatus (Referring now to FIG. 1, there is shown a simplified block diagram of a computer system 100 [0056])
comprising: interference circuitry (one or more input/output devices 120 [0057], Fig. 1);
machine readable instructions and at least one processor circuit to be programmed by the machine-readable instructions to (a CPU 105, … a processor such as CPU 105 … configured to execute the executable program instructions to carry out the functions described further herein including, but not limited to, implementing a branched encoder network [0057], Fig. 1):
encode an input image (Neural network 200 accepts input data 202 at input block 204 [0068]; … a deep neural network which performs sematic segmentation on images [0053]) via a first network (where the first branch of neural network 200 has one sparse convolutional layer represented by encoder block 210-1 [0102]. The Examiner notes encoder block 210-1 is the first network),
the first network to generate a first feature map (First input feature map 422 may be a branch feature map output by, e.g., an encoder block such as encoder block 210-1 of FIG. 2 [0090]. The Examiner notes feature map 422 is the first feature map) with a first number of channels (… where the plurality of channels correspond to each emphasized feature map [0109]) at a first downscaled resolution (Similarly, feature map 422 is downsampled [0090]; As input feature maps 422 and 424 are produced from processing by two or more branches, their scale and abstraction levels will differ [0090]; a scale (otherwise referred to as “resolution”) [0091].The Examiner notes that downscaling is downsampling);
encode the second image via a second network (where the second branch of neural network 200 has two sparse convolutional layers represented by encoder blocks 210-2 and 212-2 [0103]. The Examiner notes 210-2 and 212-2 as the second network),
the second network to generate a second feature map (Input feature map 424 also is branch feature map output from a subsequent branch, as shown in FIGS. 2 ... As input feature maps 422 and 424 are produced from processing by two or more branches [0090]. The Examiner notes feature map 424 second feature map) with a second number of channels (… where the plurality of channels correspond to each emphasized feature map [0109])
upscale the second feature map (Feature map 424 is upsampled [0090]; The emphasized feature maps are upsampled to achieve a common scale (i.e. resolution). The Examiner notes an example of upscaling is upsampling)
concatenate the first and second feature maps (Feature map 424 is upsampled, linearly fused with feature map 422 by fusion block 430 [0090], Fig. 4A)
to generate a concatenated output (As previously noted, linear fusion involves the element-wise concatenation of the feature vectors of corresponding points in the sparse tensors of the input feature maps [0090]. The Examiner notes that the output arrow coming out from fusion block 430 in Fig. 4A is the concatenated output);
apply a convolution operation to the concatenated output (the method further comprises fusing the fused feature map, … wherein the fusing comprises concatenation followed by a convolution operation [0014]); and
generate, by segmentation head circuitry (Attention blocks 432 and 434 [0090], Fig. 4A; In particular, the described systems and methods employ a unified deep neural network for performing sematic segmentation of sparse 3D point clouds [0055]),
a pixel level segmentation class map from the concatenated output (first attention block 432, which produces a first attention feature map, … second attention block 434, which produces a second attention feature map [0090]; The first and second attention feature maps are fused by adding the respective feature maps at the downsampled scale to produce an emphasized feature map 440 with a scale [0091]. The Examiner notes emphasized feature map 440 in Fig. 4A in class map).
Cheng does not explicitly teach the input image having a first image resolution, downscale the input image to generate a second image at a second resolution; generate a second feature map with a second number of channels at a second downscaled resolution, the second number of channels greater than the first number of channels; upscale the second feature map to the first downscaled resolution;
Asama teaches the input image having a first image resolution (the input may be two color images each having a resolution of H pixels by W pixels (H×W) and three channels [0026]),
a first feature map (first feature map is 232, Fig. 2) a first number of channels at a first downscaled resolution (H/4xW/4 x 18, Fig. 2. The Examiner notes the first number of channels is 18 and first downscaled resolution is H/4xW/4)
downscale the input image (The hybrid IIR-FIR convolution block 410 can receive downscaled input 412 from the TVS 408 and generate downscaled image [0044]) to generate a second image at a second resolution (The TVS 408 may be a block that outputs H/2×W/2×3 images [0042]. The Examiner notes the second resolution is H/2xW/2);
generate a second feature map with a second number of channels (H/16×W/16 x36, Fig. 2. The Examiner notes the second feature map has 36 channels) at a second downscaled resolution (Similarly, the max pooling layer 208B downscales the input feature map 234 further to generate a downscaled feature map 242 of resolution H/16×H/16 [0028]. The Examiner notes the second feature map is 242, Fig. 2),
the second number of channels (H/16×W/16 x36, Fig. 2. The Examiner notes the second feature map has 36 channels) greater than the first number of channels (H/4xW/4 x 18, Fig. 2; The max pooling layer 208A downscales the feature map 224 to generate a downscaled feature map of resolution of H/4×W/4 [0028]. The Examiner notes the first number of channels is 18 channels);
upscale (Still referring to FIG. 2, the upscaler 220B may generate a feature map 248 of resolution H/4×W/4 [0033]) the second feature map (feature map 246 with resolution of H/16×W/16 … to be sent to the upscaler 220B [0032]) to the first downscaled resolution (232 in Fig. 2 has a first downscaled resolution of H/4×W/4);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to incorporate the teachings Asama for the benefit of downscale the image in response to detecting that a resolution of the received image exceeds a predetermined threshold (Asama [0067])
Regarding claim 2, Modified Cheng teaches the apparatus of claim 1, Asama teaches wherein the first feature map of the input image is a downscaled feature map describing features of the input image (generate a downscaled feature map 242 of resolution H/16×W/16 [0028]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 3, Modified Cheng teaches the apparatus of claim 1, Asama teaches wherein the at least one processor circuit is to quantize the input image based on differential pulse code modulation (the image processor 628 can include a differential pulse-code modulation (DPCM) encoder to compress skip lines in a neural network [0065]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to incorporate the teachings Asama for the benefit of using a DPCM (differential pulse-code modulation) encoder which can encode the compressed channels to reduce the number of bits needed to store each pixel on the skip line buffer, the skip lines further compressed may reduce the memory requirement of the model (Asama [0030])
Regarding claim 4, Modified Cheng teaches the apparatus of claim 1, Cheng teaches wherein the at least one processor circuit is to transmit the concatenated output to a decoder of the imaging network circuitry (The Examiner notes output from fusion block 430 is the concatenated output which is transmitted to ATT 432, Fig. 4A [0090]; the fused feature map is input to a first attention block 432 [0090]; The fused feature map can be further fused with the output feature map of a decoder [0093])
Regarding claim 5, Modified Cheng teaches the apparatus of claim 1, Cheng teaches wherein in response to receiving an imaging task, the at least one processor circuit is to selectively transmit the input image to an encoder of the imaging network circuitry (Neural network 200 accepts input data 202 at input block 204 [0068]; … a deep neural network which performs sematic segmentation on images [0053]; where the first branch of neural network 200 has one sparse convolutional layer represented by encoder block 210-1 [0102]).
Regarding claim 6, Modified Cheng teaches the apparatus of claim 1, Asama teaches wherein the at least one processor circuit is to perform a spatially separable depthwise convolution and a pointwise convolution (For example, depthwise-separable convolutions may replace a K×K× Cin×Cout convolution with K×K convolutions for each input channel Cin, followed by a point-wise 1×1×Cin×Cout convolution [0019]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to incorporate the teachings Asama for the benefit of a separable convolutions may be used to design efficient neural network architectures, particularly in the form of depthwise-separable convolutions, such depthwise separation may lead to significant savings in the number of parameters (Asama [0019])
Regarding claim 8, claim 8 is similar to claim 1. It is rejected in the same manner and reasoning applying. Further Cheng teaches a non-transitory computer readable medium comprising instructions, which, when executed, cause processor circuitry to at least (According to another aspect of the present disclosure, there is provided a non-transitory computer readable medium storing executable instructions which, when executed by a computer, cause a processor of the computer to perform a method as described herein [0033]):
Regarding claim 9, claim 9 is similar to claim 2. It is rejected in the same manner and reasoning applying.
Regarding claim 10, claim 10 is similar to claim 3. It is rejected in the same manner and reasoning applying.
Regarding claim 11, claim 11 is similar to claim 4. It is rejected in the same manner and reasoning applying.
Regarding claim 12, claim 12 is similar to claim 5. It is rejected in the same manner and reasoning applying.
Regarding claim 13, claim 13 is similar to claim 6. It is rejected in the same manner and reasoning applying.
Regarding claim 15, claim 15 is similar to claim 1. It is rejected in the same manner and reasoning applying.
Regarding claim 16, claim 16 is similar to claim 2. It is rejected in the same manner and reasoning applying.
Regarding claim 17, claim 17 is similar to claim 3. It is rejected in the same manner and reasoning applying.
Regarding claim 18, claim 18 is similar to claim 4. It is rejected in the same manner and reasoning applying.
Regarding claim 19, claim 19 is similar to claim 5. It is rejected in the same manner and reasoning applying.
Regarding claim 20, claim 20 is similar to claim 6. It is rejected in the same manner and reasoning applying.
8. Claims 7, 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20230035475 filed 07/16/2021) in view of Asama et al. (US20200074691 published 3/5/2020 in view of Yuan et al. (US20210272299 filed 07/16/2020) and further in view of Li et al. (US20190164045)
Regarding claim 7, Modified Cheng teaches the apparatus of claim 1, Modified Cheng does not explicitly teach wherein the first output is an encoded feature map of at least 256 channels, and the second output is a less than 128 channel encoded feature map corresponding to an at least 1280x720 resolution input.
Yuan teaches wherein the first output is an encoded feature map of at least 256 channels (the number of channels of the image output by the residual sub-module in the third encoding module 408 may be preset to 256 [0111]), and
the second output is a less than 128 channel encoded feature map (For example, the number of channels of the image output by the residual sub-module in the first encoding module 404 may be preset to 64 [0111])
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Modified Cheng to incorporate the teachings of Yuan for the benefit of acquisition and transmission of digital images by imaging equipment (Yaun [0003])
Modified Cheng does not explicitly teach the second output is a less than 128 channel encoded feature map corresponding to an at least 1280x720 resolution input.
Li teaches the second output is a less than 128 channel encoded feature map corresponding to an at least 1280x720 resolution input (For example, in a case where a processing unit (for example, a multiplier array for convolution operation) is capable of processing data with 32channels at a time, and where a convolution operation is to be performed on an RGB image (the number of channels being 3) of 720×1280 by using a 5×5 convolution kernel (with each stride in width and height being 1) [0081]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Modified Cheng to incorporate the teachings of Li for the benefit of operations in the convolutional neural network that can be efficiently performed by hardware such as a universal Central Processor (CPU) and Graphics Processor (GPU) or a dedicated accelerator, and the like (Li [0002])
Regarding claim 14, claim 14 is similar to claim 7. It is rejected in the same manner and reasoning applying.
Regarding claim 21, claim 21 is similar to claim 7. It is rejected in the same manner and reasoning applying.
9. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20230035475 filed 07/16/2021) in view of Asama et al. (US20200074691 published 3/5/2020 in view of Shigenobu et al. (US20210235070)
Regarding claim 22, claim 22 is similar to claim 1. It is rejected in the same manner and reasoning applying. Modified Cheng does not explicitly teach an apparatus to perform semantic image segmentation comprising: mode selecting circuitry to transmit an input image to at least one of vision network circuitry and imaging network circuitry,
Shigenobu teaches an apparatus to perform semantic image segmentation comprising: mode selecting circuitry (first mode determination engine 11, second mode determination engine 12, cost calculator 13, mode selector 14 [0027])
to transmit an input image to vision network circuitry and imaging network circuitry (An image encoding method includes, using an image as input, determining a first mode suited to encode the image in accordance with a first processing procedure; using the image as input, determining a second mode suited to encode the image in accordance with a second processing procedure; selecting one of first mode and the second mode as a final mode; encoding the image, using the final mode (abstract),
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Modified Cheng to incorporate the teachings of Shigenobu for the benefit of a device for selecting a mode suited to encoding and then encoding an image (Shigenobu [0002])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MORIAM MOSUNMOLA GODO whose telephone number is (571)272-8670. The examiner can normally be reached Monday-Friday 8:00am-5:00pm EST.
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/M.G./Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148