Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/19/2025 has been entered.
Response to Amendments
Acknowledgment is made of the amendment filed 08/19/2025 (“Amend.”), in which: claim 1 amended; no claims are cancelled; no new claims are added, and the rejection of the claims are traversed. Claims 1 – 9 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments filed 08/19/2025 have been fully considered but are not persuasive.
Applicant argues on pages 5 – 6 of the instant Remarks:
In the art disclosed by Delic, the shallow trench isolation region 512 is in contact with the separator. However, examiner notes that Delic discloses a plurality of shallow trench isolation regions 512 (Figs. 5B and 5D); such that a shallow trench isolation region from a plurality of trench isolation regions is not in contact with the separator of discussion. Therefore, Examiner is not persuaded that the amended feature is not disclosed by the prior art of record. See rejection below.
Rejections
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 9 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Applicant amends claim 1 to include a shallow trench isolation and states in their arguments received 08/19/2025 that support for such an amendment may be found in Fig. 4 and the discussion thereof in the instant specification. However, examiner does not see a shallow trench isolation that could be considered distinct from the already claimed first separator 16; nor do any of the denoted structures in Fig. 4 refer to a shallow trench isolation; nor does the specification (pages 11 – 13 of the instant specification) provide support for a shallow trench isolation that could be considered distinct from the already claimed first separator 16. Claims 2 – 9 depend on claim 1 and thus are rejected by virtue. Appropriate response/correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 5 and 7 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kokubun et al. (US 20190296074 A1) and further in view of Delic (US 20180195900 A1).
Regarding independent Claim 1, Kokubun teaches a photodetector, comprising:
a pixel array (Fig. 1; plurality of silicon photomultipliers, SiPM, arranged in a matric form. See [0025]) in which a plurality of pixels are arranged in an array (Fig. 1), wherein each of the plurality of pixels includes:
a first semiconductor layer (Fig. 8; p+ type layer 22) of a first conductivity type (Kokubun teaches in [0028] the p+ type layer 22);
a second semiconductor layer (Fig. 8; epitaxial layer 21 that lies between the isolation features 30 and positioned above p+ type layer 22) of the first conductivity type (Kokubun teaches in [0028] – [0031] the conductivity type of epitaxial layer 21) located above the first semiconductor layer (Fig. 8) and having an impurity concentration lower than an impurity concentration of the first semiconductor layer ([0028] and [0030]); and
a first semiconductor region (Fig. 8; n+ type layer 23) of a second conductivity type (Fig. 8 and [0029]) disposed in the second semiconductor layer (Fig. 8) and joined to the first semiconductor layer (Fig. 8; diode 25. See [0029]), the second conductivity type being different from the first conductivity type (Fig. 8) the first semiconductor layer and the first semiconductor region constitute a multiplication region (Fig. 5 and [0040] – [0041]) in which a charge is multiplied by avalanche multiplication ([0041]),
the pixel array includes a first separator (Fig. 8; local oxidation of silicon, LOCOS, film 30) of the first conductivity type (Kokubun teaches in [0027] an oxidized film, LOCOS film 30, where oxidized is recognized by one of ordinary skill in the art to be a process that results in the loss of electrons, i.e., a p type material. P type conductivity has been interpreted thus far by the examiner to be the first conductivity type. See rejection of the limitations above) disposed in the second semiconductor layer (Fig. 8) and a second separator (Fig. 8; peripheral p type layer 261) of the first conductivity type ([0030]) disposed in the first semiconductor layer (Fig. 8), [[and]]
the first separator and the second separator are arranged to be separated from each other (See Fig. 8),
a lowermost surface of the second semiconductor layer is located above an uppermost surface of the first semiconductor layer (Fig. 8), [[and]] …
However, Kokubun remains silent regarding:
… the first separator does not include an insulator, and
the first separator is not in contact with a shallow trench isolation.
Kokubun discusses in [0043] – [0047] the role of the peripheral p+ type layer 26 (261) and LOCOS film 30 in providing a high photon detection efficiency, which is the function of the first and second separators as disclosed by the applicant in the instant specification (page 5; lines 15 – 27 of instant specification).
However, in the same field of endeavor, Delic teaches a single-photon avalanche diode (SPAD) array sensor (Fig. 4); wherein each pixel (Fig. 5D) is surrounded by p+ ring 502 (see lines 4 – 6 of [0088], also see Fig. 5B and [0088] – [0093]). Delic discloses in [0091] that lightly doped guard rings maximize the probability that the avalanche is initiated in the center of the multiplication region (or depletion region). Further, Delic teaches the p+ ring 502 as a doped conductive structure, such that p+ ring 502 is not an insulator. As both Kokubun’s LOCOS film 30 and Delic’s p+ ring 502 separate adjacent pixels from each other and serve to increases the detection efficiency of the device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to substitute Kokubun’s LOCOS film 30 with Delic’s p+ ring 502.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector to include Delic’s p+ ring as a first separator because such a modification is the result of a simple substitution of one known element for another producing a predictable result. More specifically, Kokubun’s LOCOS film 30 and Delic’s p+ ring perform the same general and predictable function, the predictable function being to separate pixels and increase detection efficiency of the photodetector. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself - that is in the substitution of Kokubun’s LOCOS film 30 by replacing it with Delic’s p+ ring. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious before the effective filing date of the instant invention.
Further, Examiner notes that Delic teaches a plurality of shallow trench isolation regions using silicon dioxide layers 512 (Figs. 5B and 5D and [0088]); wherein a shallow trench isolation region 512 is not in contact with by p+ ring 502 (Figs. 5B and 5D. Also see excerpt of Fig. 5B below). Delic’s shallow trench isolation region may be added to the device disclosed by Kokubun in a similar way shown/disclosed by Delic; such that Kokubun’s epitaxial layer 21 may fill space between the added shallow trench isolation region 512 and the added separator from Delic’s disclosure. Delic shows, e.g., Fig. 5B, that the well region 508 (similar to Kokubun’s epitaxial layer 21) fills gaps (see “filled gap” marked in excerpt below) in portions of the semiconductor device between the outer p+ ring 502 and the shallow trench isolation region 512. Thus, examiner asserts that Delic’s shallow trench isolation structure may be added to Kokubun’s photodetector and further added in a similar way as disclosed by Delic to yield a photodetector wherein the first separator does not include an insulator, and the first separator is not in contact with a shallow trench isolation.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector to include Delic’s shallow trench isolation regions, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Kokubun’s photodetector as modified by Delic’s shallow trench isolation regions can yield a predictable result of separating conducting/semiconducting photodetector elements since Delic’s shallow trench isolation regions are formed of insulating silicon dioxide. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector, further in view of Delic, to include Delic’s teaching of forming the shallow trench isolation spaced from the first separator wherein a well region at least partially filling the space therebetween, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, well region 508 is comparable to Kokubun’s epitaxial layer 21 because they are both well regions in a photodetector device. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kokubun’s photodetector, further in view of Delic, to include Delic’s teaching of forming the shallow trench isolation spaced from the first separator wherein a well region at least partially filling the space therebetween with the predictable result of allowing space for the well region to make contact with other structures of the photodetector device.
The examiner also asserts that an embodiment shown in Fig. 3 of Kokubun, further in view of Delic, also teaches the photodetector of claim 1 in the present disclosure. See below.
Regarding independent Claim 1, Kokubun teaches a photodetector, comprising:
a pixel array (Fig. 1; plurality of silicon photomultipliers, SiPM, arranged in a matric form. See [0025]) in which a plurality of pixels are arranged in an array (Fig. 1), wherein each of the plurality of pixels includes:
a first semiconductor layer (Fig. 3; p+ type layer 22) of a first conductivity type (Kokubun teaches in [0028] the p+ type layer 22);
a second semiconductor layer (Fig. 3; epitaxial layer 21 that lies between the isolation features 30 and positioned above p+ type layer 22) of the first conductivity type (Kokubun teaches in [0028] – [0031] the conductivity type of epitaxial layer 21) located above the first semiconductor layer (Fig. 3) and having an impurity concentration lower than an impurity concentration of the first semiconductor layer ([0028] and [0030]); and
a first semiconductor region (Fig. 3; n+ type layer 23) of a second conductivity type (Fig. 3 and [0029]) disposed in the second semiconductor layer (Fig. 3) and joined to the first semiconductor layer (Fig. 3; diode 25. See [0029]), the second conductivity type being different from the first conductivity type (Fig. 3) the first semiconductor layer and the first semiconductor region constitute a multiplication region (Fig. 5 and [0040] – [0041]) in which a charge is multiplied by avalanche multiplication ([0041]),
the pixel array includes a first separator (Fig. 3; local oxidation of silicon, LOCOS, film 30) of the first conductivity type (Kokubun teaches in [0027] an oxidized film, LOCOS film 30, where oxidized is recognized by one of ordinary skill in the art to be a process that results in the loss of electrons, i.e., a p type material. P type conductivity has been interpreted thus far by the examiner to be the first conductivity type. See rejection of the limitations above) disposed in the second semiconductor layer (Fig. 3) and a second separator (Fig. 3; peripheral p type layer 26) of the first conductivity type ([0030]) disposed in the first semiconductor layer (Fig. 3), [[and]]
the first separator and the second separator are arranged to be separated from each other, [[and]]
a lowermost surface of the second semiconductor layer is located above an uppermost surface of the first semiconductor layer (Fig. 8), [[and]] …
However, Kokubun remains silent regarding:
the first separator does not include an insulator, and
the first separator is not in contact with a shallow trench isolation.
Kokubun discusses in [0043] – [0047] the role of the peripheral p+ type layer 26 (261) and LOCOS film 30 in providing a high photon detection efficiency, which is the function of the first and second separators as disclosed by the applicant in the instant specification (page 5; lines 15 – 27 of instant specification).
However, in the same field of endeavor, Delic teaches a single-photon avalanche diode (SPAD) array sensor (Fig. 4); wherein each pixel (Fig. 5D) is surrounded by p+ ring 502, understood to be distinct from the p+ region 502 (see lines 4 – 6 of [0088], also see Fig. 5B and [0088] – [0093]). Delic discloses in [0091] that lightly doped guard rings maximize the probability that the avalanche is initiated in the center of the multiplication region (or depletion region). Further, Delic teaches the p+ ring 502 as a doped conductive structure, such that p+ ring 502 is not an insulator. As both Kokubun’s LOCOS film 30 and Delic’s p+ ring 502 separate adjacent pixels from each other and serve to increases the detection efficiency of the device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to substitute Kokubun’s LOCOS film 30 with Delic’s p+ ring 502.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector to include Delic’s p+ ring as a first separator because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Kokubun’s LOCOS film 30 and Delic’s p+ ring perform the same general and predictable function, the predictable function being to separate pixels and increase detection efficiency of the photodetector. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself - that is in the substitution of Kokubun’s LOCOS film 30 by replacing it with Delic’s p+ ring. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious before the effective filing date of the instant invention.
Further, Examiner notes that Delic teaches a plurality of shallow trench isolation regions using silicon dioxide layers 512 (Figs. 5B and 5D and [0088]); wherein a shallow trench isolation region 512 is not in contact with by p+ ring 502 (Figs. 5B and 5D. Also see excerpt of Fig. 5B below). Delic’s shallow trench isolation region may be added to the device disclosed by Kokubun in a similar way shown/disclosed by Delic; such that Kokubun’s epitaxial layer 21 may fill space between the added shallow trench isolation region 512 and the added separator from Delic’s disclosure. Delic shows, e.g., Fig. 5B, that the well region 508 (similar to Kokubun’s epitaxial layer 21) fills gaps (see “filled gap” marked in excerpt below) in portions of the semiconductor device between the outer p+ ring 502 and the shallow trench isolation region 512. Thus, examiner asserts that Delic’s shallow trench isolation structure may be added to Kokubun’s photodetector and further added in a similar way as disclosed by Delic to yield a photodetector wherein the first separator does not include an insulator, and the first separator is not in contact with a shallow trench isolation.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector to include Delic’s shallow trench isolation regions, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Kokubun’s photodetector as modified by Delic’s shallow trench isolation regions can yield a predictable result of separating conducting/semiconducting photodetector elements since Delic’s shallow trench isolation regions are formed of insulating silicon dioxide. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kokubun’s photodetector, further in view of Delic, to include Delic’s teaching of forming the shallow trench isolation spaced from the first separator wherein a well region at least partially filling the space therebetween, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, well region 508 is comparable to Kokubun’s epitaxial layer 21 because they are both well regions in a photodetector device. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kokubun’s photodetector, further in view of Delic, to include Delic’s teaching of forming the shallow trench isolation spaced from the first separator wherein a well region at least partially filling the space therebetween with the predictable result of allowing space for the well region to make contact with other structures of the photodetector device.
Regarding dependent Claim 2, Kokubun, further in view of Delic, teach the photodetector according to claim 1, wherein;
the second separator has an impurity concentration higher than an impurity concentration of a region of the first semiconductor layer (Kokubun: Fig. 8; the examiner is interpreting the portion of p+ type layer 22 on the same plane of 261 to be a region of the first semiconductor layer) which is of a same depth as the second separator and where the second separator is not disposed (Kokubun: Fig. 8).
Kokubun teaches in [0030] that the impurity concentration of epitaxial layer 21 may be 1x1016 cm-3 and that the impurity concentration of p+ type layer 22 may be 4.5x1016 cm-3. Additionally, Kokubun teaches in [0055] that peripheral p+ type layer 261 may have an impurity concentration of at least 10 times the epitaxial layer 21, such that the impurity concentration of the peripheral p+ type layer 261 may be 1x1017 cm-3. This teaches the impurity concentration of the second separator being higher than a region of the first semiconductor layer.
Regarding dependent Claim 3, Kokubun, further in view of Delic, teach the photodetector according to claim 1 -(Kokubun teaches the device according to claim 1 in Figs. 1 – 6), wherein;
in a plan view of the pixel array, the second separator overlaps at least part of the first semiconductor region in each of the plurality of pixels (Kokubun: Figs. 1 – 3 and [0031]).
Regarding dependent Claim 4, Kokubun, further in view of Delic, teach the photodetector according to claim 3, wherein;
in a plan view of the pixel array, the second separator does not overlap at least part of a uniform electric field region (Kokubun: Fig. 6; effective region 45. See [0040] and [0043]) included in the first semiconductor region in each of the plurality of pixels (Kokubun: Fig. 5), the uniform electric field region being a region in which an electric field is uniform (Kokubun: See [0040] and [0043]).
Regarding dependent Claim 5, Kokubun, further in view of Delic, teach the photodetector according to claim 1, wherein;
an impurity concentration of the first semiconductor layer is high (Kokubun: [0028]) on an upper side where the multiplication region is included, and an impurity concentration on a lower side of the first semiconductor layer is lower than or equal to the impurity concentration on the upper side (From the disclosure of Kokubun, the examiner is interpreting the impurity concentration to be the same on the lower side as it is on the upper side of p+ type semiconductor layer 22, e.g., the first semiconductor layer).
Regarding dependent Claim 7, Kokubun, further in view of Delic, teach the photodetector according to claim 1, wherein;
the pixel includes a circuit region (Kokubun: Fig. 4) disposed in the second semiconductor layer (Kokubun: Fig. 3), the circuit region including one or more transistors (Kokubun: electrode film 31 acts as a transistor as a voltage is applied. See [0039]), and
the second separator overlaps at least part of the circuit region in a plan view of the pixel array (Kokubun: Figs. 3 and 4).
Regarding dependent Claim 8, Kokubun, further in view of Delic, teach the photodetector according to claim 1, wherein;
the second separator has a cross section parallel to the pixel array extending from an upper side to a lower side of the first semiconductor layer (Kokubun: Fig. 8).
Regarding dependent Claim 9, Kokubun, further in view of Delic, teach the photodetector according to claim 1, wherein;
the second separator has a cross section parallel to the pixel array extending from a lower side to an upper side of the first semiconductor layer (Kokubun: Fig. 8).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kokubun et al. (US 20190296074 A1) and further in view of Delic (US 20180195900 A1) and Mandai et al. (US 20180090536 A1).
Regarding dependent Claim 6, Kokubun, further in view of Delic, teach the photodetector according to claim 1. However, Kokubun remains silent on the photodetector according to claim 1 wherein;
the impurity concentration of the first semiconductor layer increases from an upper side to a lower side of the first semiconductor layer.
However, in the same field of endeavor, Mandai teaches a photodetector wherein;
the impurity concentration of the first semiconductor layer (Fig. 4A; element 402 excluding the region bounded by the depletion layer 418, taught in [0069]) increases from an upper side (the examiner is interpreting a front surface as disclosed in [0067] of Mandai to be an upper side) to a lower side (the examiner is interpreting a back surface as disclosed in [0067] of Mandai to be a lower side) of the first semiconductor layer.
Mandai teaches in [0067] that the first semiconductor layer increases from a front surface to a back surface
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the photodetector, as disclosed by Kokubun and Delic, to include a first semiconductor layer with an impurity concentration gradient that increases from an upper side to a lower side, as disclosed by Mandai, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify Kokubun’s first semiconductor layer to include an impurity concentration gradient that increases from an upper side to a lower side, as disclosed by Mandai, is expressly provided by Mandai, stating in [0069] that “The dopant concentration gradient in the anode gradient layer 402 may reduce the SPAD breakdown voltage and/or shorten the collection time of the minority charge carriers, which can improve the response time of the SPAD region 400.” Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Kokubun’s first semiconductor layer to include an impurity concentration gradient that increases from an upper side to a lower side, as disclosed by Mandai, with the motivation of improving the photodetector’s response time, a benefit that one of ordinary skill in the art would have recognized.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20110095388 A1 teaches a similar photodetector (See Fig. 7).
US 20190157323 A1 teaches a pixel separation unit with similar features to the instant photodetector.
US 20090121306 A1 and US 20220020789 A1 combined teach a similar photodetector.
US 20150054111 A1 teaches similar semiconductor layers and separators.
US 7262402 B2 teaches similar semiconductor layers and separators.
US 20170031010 A1 teaches similar semiconductor layers and separators.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897