DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Prior Art Rejections
Applicant’s arguments filed 3/12/2026, with respect to the rejection(s) of claim(s) 1, 10, 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Ovsiannikov, Brothers, and Woo do not teach control signals specify a multiplexer control pattern to use to route a subset of activation values during sparsity mode. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new prior art rejections.
Claim Objections
Claims 1, 10, 17 are objected to because of the following informalities: change “the plurality of control signals are to… route the subset of activation values of the plurality of activation values from the second plurality of registers” to “the plurality of control signals values from the second plurality of registers are to… route the subset of activation values of the plurality of activation values”. Such that it is clear that the plurality of activation values are not from the second plurality of registers.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-17, 19, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ovsiannikov et al. (US 2090392287 A1, hereinafter “Ovsiannikov”) in view of Sen et al. (US 20230030287 A1, hereinafter “Sen”, cited in 892 mailed 12/12/2025).
As per claim 1, Ovsiannikov teaches A digital signal processing (DSP) block (Ovsiannikov: Fig. 1A element 102; [0259]) comprising:
a first plurality of registers (Ovsiannikov: Fig. 1B element 127; [0262]),
a plurality of multipliers (Ovsiannikov: Fig. 1B element 126; [0259]), wherein each respective multiplier of the plurality of multipliers is configurable to receive a respective value of the plurality of (Ovsiannikov: [0262]);
one or more inputs configurable to receive a plurality of activation values (Ovsiannikov: Fig. 1B element 139; [0263]);
a multiplexer network (Ovsiannikov: Fig. 1L element 166; [0314])
during a sparsity mode (Ovsiannikov: [0264] “The sparse activation computation feature can be optionally disabled, resulting in “dense” tensor computation mode” shows Ovsiannikov teaches having a mode for sparsity computation), and wherein the plurality of multipliers is configurable to simultaneously multiply each value of the plurality of (Ovsiannikov: [0271]);
and adder circuitry (Ovsiannikov: Fig. 1B element 128A, 128B, 130A, 130B; [0261]) configurable to generate a first sum and a second sum based on the plurality of products (Ovsiannikov: [0271]).
However, while Ovsiannikov discloses a weight decompression unit (Fig. 1N element 138) that writes weights to the weight registers ([0320]), Ovsiannikov does not explicitly disclose the decompressed weights sent to weight registers are non-zero. Thus, Ovsiannikov does not teach weight registers configurable to receive and store a plurality of non-zero weight values; a second plurality of registers configurable to receive and store a plurality of control signals; and route, based on the plurality of control signals, a subset of activation values of the plurality of activation values to a multiplier of the plurality of multipliers, wherein the plurality of control signals are to specify a multiplexer control pattern to use to route the subset of activation values of the plurality of activation values from the second plurality of registers to the multiplier of the plurality of multipliers.
Sen teaches configurable to receive and store a plurality of non-zero weight values (Sen: Fig. 6 element 620; [0072]);
a second plurality of registers configurable to receive and store a plurality of control signals (Sen: Fig. 6 element 610; [0072]);
and route, based on the plurality of control signals, a subset of activation values of the plurality of activation values to a multiplier of the plurality of multipliers (Sen: Fig. 6; [0072]; wherein the new index register file controls the input value to be multiplied), wherein the plurality of control signals are to specify a multiplexer control pattern to use to route the subset of activation values of the plurality of activation values from the second plurality of registers to the multiplier of the plurality of multipliers (Sen: Fig. 6; [0072]; “subset” is understood as merely consisting of only elements of a superset and does not require being a proper, or strict, subset).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the weight decompression unit and IFM lane control logic of Ovsiannikov with the processor element of Sen. One would have been motivated to combine these references because both references disclose computing for neural networks with sparse data, and Sen improves execution time and energy savings by exploiting the sparsity of weights (Sen: [0017]).
As per claim 6, Ovsiannikov/Sen further teaches the DSP block of claim 1, wherein: in a first mode of operation of the DSP block: the plurality of multipliers is a first column of multipliers (Ovsiannikov: [0261] “Each tile 102 may include a multiply-and-reduce (MR) array 122 of multiply-and-reduce (MR) columns 133 … Each MR column 133 contains sixteen multiplier units MU 103 and two adder trees 128A and 128B” The Examiner interprets Ovsiannikov to allow a single column);
the adder circuitry is configurable to generate the first sum by adding a first portion of the plurality of products generated by a first portion of the first column of multipliers (Ovsiannikov: [0262] “Subsequently, adder trees 128A and 128B in each MR column 133 sum up (reduce) resulting products from the sixteen MUs in the column to form a dot product.”);
and the adder circuitry is configurable to generate the second sum by adding a second portion of the plurality of products generated by a second portion of the first column of multipliers (Ovsiannikov: [0271] “each of the adders 128 may form a sum of some of those sixteen products at its inputs (as illustrated in FIG. 1B for four lanes), and the adder of each accumulator 130 may form the sum of (i) the current value of the register of the accumulator 130, and (ii) the output of a corresponding adder 128.”);
and in a second mode of operation of the DSP block: the plurality of multipliers comprises the first column of multipliers and a second column of multipliers (Ovsiannikov: [0261] “Each tile 102 may include a multiply-and-reduce (MR) array 122 of multiply-and-reduce (MR) columns 133 … Each MR column 133 contains sixteen multiplier units MU 103 and two adder trees 128A and 128B”);
the adder circuitry is configurable to generate the first sum by adding the first portion of the plurality of products generated by the first column of multipliers (Ovsiannikov: [0262] “Subsequently, adder trees 128A and 128B in each MR column 133 sum up (reduce) resulting products from the sixteen MUs in the column to form a dot product.”);
and the adder circuitry is configurable to generate the second sum by adding the second portion of the plurality of products generated by the second column of multipliers (Ovsiannikov: [0271] “each of the adders 128 may form a sum of some of those sixteen products at its inputs (as illustrated in FIG. 1B for four lanes), and the adder of each accumulator 130 may form the sum of (i) the current value of the register of the accumulator 130, and (ii) the output of a corresponding adder 128.”).
As per claim 7, Ovsiannikov/Sen further teaches The DSP block of claim 1, wherein: the multiplexer network comprises a first portion configurable to receive a first portion of the plurality of values, wherein the first portion of the multiplexer network comprises a first plurality of multiplexers having a first number of multiplexers (Ovsiannikov: Fig. 1MA, Fig. 1MB; [0317]);
the multiplexer network comprises a second portion configurable to receive a second portion of the plurality of values, wherein the second portion of the multiplexer network comprises a second plurality of multiplexers having the first number of multiplexers (Ovsiannikov: [0319]; The Examiner interprets the plurality of multiplexers taught in Ovsiannikov to be separable into portions);
the plurality of multipliers comprises a first portion having a first number of multipliers, wherein the first portion of the plurality of multipliers is communicatively coupled to the first portion of the crossbar wiring structure (Ovsiannikov: [0317]);
and the plurality of multipliers comprises a second portion having the first number of multipliers, wherein the second portion of the plurality of multipliers is communicatively coupled to the second portion of the multiplexer network (Ovsiannikov: [0265]; The Examiner interprets the plurality of multipliers taught in Ovsiannikov to be separable into portions), wherein the first number of multiplexers is equal to the first number of multipliers (Ovsiannikov: [0263], [0336]).
As per claim 8, Ovsiannikov/Brothers/Woo further teaches The DSP block of claim 7, wherein the multiplexer network comprises: a third portion, wherein the third portion of the multiplexer network is communicatively coupled to the first portion of the multiplexer network, wherein the third portion of the multiplexer network is configurable to receive each value of the plurality of activation values (Ovsiannikov: Fig. 1MA, [0317]);
and a fourth portion, wherein the fourth portion of the multiplexer network is communicatively coupled to the second portion of the multiplexer network, wherein the fourth portion of the multiplexer network is configurable to receive each value of the plurality of activation values (Ovsiannikov: Fig. 1MA, [0317]).
As per claim 9, Ovsiannikov/Brothers/Woo further teaches The DSP block of claim 1, wherein the multiplexer network comprises a plurality of multiplexers configurable for one or more sparsity ratios (Ovsiannikov: [0343]).
As per claim 10, the claim is directed to and integrated circuit device that implements the same features as the DSP block of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Ovsiannikov/Sen teaches and input circuitry configurable to receive a first value and a second value from a second DSP block (Ovsiannikov: [0505]);
second adder circuitry configurable to: receive the first sum and the first value and generate a third sum by adding the first sum and the first value (Ovsiannikov: [0505]); receive the second sum and the second value and generate a fourth sum by adding the second sum and the second value (Ovsiannikov: [0505]); and output circuitry configurable to output the third sum and the fourth sum from the DSP block to a third DSP block (Ovsiannikov: [0505]).
As per claim 11, Ovsiannikov/Sen further teaches The integrated circuit device of claim 10, wherein: the multiplexer network comprises: a first plurality of multiplexers each configurable to receive a first portion of the plurality of activation values and selectively output a value from the first portion of the plurality of activation values (Ovsiannikov: Fig. 1MA, Fig. 1MB, [0317]);
and a second plurality of multiplexers each configurable to receive a second portion of the plurality of activation values and selectively output a value from the second portion of the plurality of activation values (Ovsiannikov: [0319]);
the plurality of multipliers comprise: a first plurality of multipliers configurable to generate the first portion of the plurality of products based on the first portion of the plurality of activation values received from the first plurality of multiplexers (Ovsiannikov: [0317], [0271]);
a second plurality of multipliers configurable to generate the second portion of the plurality of products based on the second portion of the plurality of activation values received from the second plurality of multiplexers (Ovsiannikov: [0317], [0271]);
and the first adder circuitry is configurable to: generate the first sum by adding the first portion of the plurality of products; and generate the second sum by adding the second portion of the plurality of products (Ovsiannikov: Fig. 1B, element 128A, 128B, [0271]).
As per claim 12, Ovsiannikov/Sen further teaches The integrated circuit device of claim 11, wherein: the first portion of the plurality of activation values comprises each input of the second portion of the plurality of activation values; and the second portion of the plurality of activation values comprises fewer than each input of the first portion of the plurality of activation values (Ovsiannikov: [0271]).
As per claim 13, Ovsiannikov/Sen further teaches The integrated circuit device of claim 11, wherein the first portion of the plurality of activation values is identical to the second portion of the plurality of activation values (Ovsiannikov: [0271]).
As per claim 14, Ovsiannikov/Sen further teaches The integrated circuit device of claim 11, wherein the first plurality of multipliers comprises more multipliers than the second plurality of multipliers (Ovsiannikov: [0267] “As mentioned previously, multiplier units in MR array 122 may be arranged as a plurality of rows, e.g., 16 rows, with FIG. 1B showing only four rows out of 16 for clarity”).
As per claim 15, Ovsiannikov/Sen further teaches The integrated circuit device of claim 10, wherein the fracturable column is a first fracturable column of a plurality of fracturable columns of the DSP block (Ovsiannikov: [0261] “FIG. 1B shows an MR array 122, in some embodiments. Each MR array contains eight MR columns 133.”).
As per claim 16, Ovsiannikov/Sen further teaches The integrated circuit device of claim 10, wherein the integrated circuit device comprises a programmable logic device, wherein the programmable logic device comprises the DSP block and at least an additional DSP block, and wherein the programmable logic device is configurable to cause data output from the DSP block to be provided to the additional DSP block (Ovsiannikov: Fig. 4AH, [0496]; The Examiner interprets the adders with its nearest tile to correspond to an additional DSP block).
As per Claim 17, the claim is directed to a DSP block that implements the same features as the integrated circuit of claim 10, and is therefore rejected for at least the same reasons therein. Furthermore, Ovsiannikov/Sen teaches a multiplexer network is configurable to: receive the plurality of activation values (Ovsiannikov: [0343] “For example, lane 1 (outputting c1) has 6 choices to output: c0, c1, c2 (which is zero) and b0, b1 (which is also zero) and b2. The multiplexer 163 outputs one of these 6 choices. Which choice to output is determined by the tile control FSM 144.”);
As per Claim 19, Ovsiannikov/Sen further teaches The DSP block of claim 17, comprising: a second fracturable column comprising third adder circuitry configurable to generate a fifth sum, a sixth sum, and a seventh sum (Ovsiannikov [0261], [0293], [0327]);
and a third fracturable column comprising fourth adder circuitry configurable to generate an eighth sum and a ninth sum (Ovsiannikov [0261).
As per claim 22, Ovsiannikov/Sen further teaches The DSP block of claim 1, wherein the first plurality of registers are loaded using a first port (Ovsiannikov: Fig. 1V element 146; Brothers: Fig. 7; [0099]) and the second plurality of registers are loaded using a second port (Ovsiannikov: Fig. 1K element 127; The Examiner notes the weight data comes from a different port than the selection data).
Claims 4, 5, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ovsiannikov/Sen in further view of Langhammer (US 20170322769 A1, hereinafter “Langhammer”).
As per Claim 4, Ovsiannikov/Sen further teaches The DSP block of claim 1, comprising: second adder circuitry configurable to receive a first product and a second product of the plurality of products and generate a third sum by adding the first product and the second product; third adder circuitry configurable to receive a third product and a fourth product of the plurality of products and generate a fourth sum by adding the third product and the fourth product; fourth adder circuitry configurable to receive a fifth product and a sixth product of the plurality of products and generate a fifth sum by adding the fifth product and the sixth product; fifth adder circuitry configurable to receive a seventh product and eighth product of the plurality of products and generate a sixth sum by adding the seventh product and the eighth product (Ovsiannikov [0262] “Subsequently, adder trees 128A and 128B in each MR column 133 sum up (reduce) resulting products from the sixteen MUs in the column to form a dot product.”);
However, while Ovsiannikov discloses adders comprising of a combination of physical adders and multiplexers (Ovsiannikov [0296] “As used herein, an “adder” is either a physical circuit for adding at least two numbers to form a sum, or one of a plurality of logical adders formed with a combination of physical adders and multiplexers as in the example of FIG. 1J.”), Ovsiannikov does not explicitly teach a first multiplexer configurable to receive the fourth sum and the sixth sum and provide a first output to a first adder of the adder circuitry, wherein the first output comprises either the fourth sum or the sixth sum, wherein the first adder is configurable to generate a seventh sum by adding the third sum and the first output; a second multiplexer configurable to receive the fourth sum and the sixth sum and provide a second output to a second adder of the adder circuitry, wherein the second output comprises either the fourth sum or the sixth sum, wherein the second adder is configurable to generate the first sum by adding the fifth sum and the second output; a third adder of the adder circuitry configurable to receive the first sum and the seventh sum and generate am eighth sum by adding the first sum and the seventh sum; and a third multiplexer configurable to receive the seventh sum and the eighth sum and selectively output the seventh sum of the eighth sum as the second sum.
Langhammer teaches a first multiplexer configurable to receive the fourth sum and the sixth sum and provide a first output to a first adder of the adder circuitry, wherein the first output comprises either the fourth sum or the sixth sum, wherein the first adder is configurable to generate a seventh sum by adding the third sum and the first output (Langhammer Fig 2, Fig. 6, [0144] “Multiplexer 675 of specialized processing block 600A may receive signal ADD_CHAIN_IN and the floating-point sum signal and select to propagate signal ADD_CHAIN_IN over a chain-out port and a cascade connection to the corresponding chain-in port of specialized processing block 600B.”);
a second multiplexer configurable to receive the fourth sum and the sixth sum and provide a second output to a second adder of the adder circuitry, wherein the second output comprises either the fourth sum or the sixth sum, wherein the second adder is configurable to generate the first sum by adding the fifth sum and the second output (Langhammer [0143] “Floating-point adder circuit 605 of specialized processing block 600A may generate a floating-point sum signal based on the first and second summand signals, and configurable interconnect circuitry may convey the floating-point sum signal as signal E to an output port of specialized processing block 600A.”);
a third adder of the adder circuitry configurable to receive the first sum and the seventh sum and generate am eighth sum by adding the first sum and the seventh sum; and a third multiplexer configurable to receive the seventh sum and the eighth sum and selectively output the seventh sum of the eighth sum as the second sum (Langhammer [0144] “Multiplexer 675 of specialized processing block 600A may receive signal ADD_CHAIN_IN and the floating-point sum signal and select to propagate signal ADD_CHAIN_IN over a chain-out port and a cascade connection to the corresponding chain-in port of specialized processing block 600B.” It would be obvious for one of ordinary skill to continue for as many combinations of sums as the user desires by extending the cascade chain as taught by Langhammer.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the adder trees of Ovsiannikov (Fig. 1B element 128A-B, [0262]) with the specialized processing blocks of Langhammer (Fig. 2, Fig. 6, [0132]). One would have been motivated to combine these references because both references disclose summation of multiple inputs, and Langhammer increases the efficiency of Ovsiannikov to perform fixed-point and/or floating-point operations (Langhammer [0041]).
As per Claim 5, Ovsiannikov/Sen/Langhammer further teaches The DSP block of claim 4, comprising: input circuitry configurable to receive a first value and a second value from a second DSP block (Ovsiannikov [0505] “Reduction fabric 111 performs “inter-tile” reduction (as opposed to intra-tile reduction accomplished by adder trees 128A and 128B) for all reduction configurations” The Examiner interprets the combination of an MR tile and part of the reduction fabric taught in Ovsiannikov as equivalent to the claimed DSP block);
a fourth adder configurable to receive the first sum and the first value and generate a ninth sum by adding the first sum and the first value (Ovsiannikov [0505] “Reduction fabric 111 is comprised of a reconfigurable adder tree made up of reduce-and-accumulate (RAA) nodes 520 illustrated in FIG. 5A… RAA receives inputs either from same tile column ARUs 167 where that RAA node is located or inputs from other RAA nodes.”);
a fifth adder configurable to receive the second sum and the second value and generate a tenth sum by adding the second sum and the second value (Ovsiannikov [0505] “Reduction fabric 111 is comprised of a reconfigurable adder tree made up of reduce-and-accumulate (RAA) nodes 520 illustrated in FIG. 5A… RAA receives inputs either from same tile column ARUs 167 where that RAA node is located or inputs from other RAA nodes.”);
and output circuitry configurable to output the ninth sum and the tenth sum from the DSP block to a third DSP block (Ovsiannikov [0505] “RAA sends outputs either to RAA nodes further up in the adder tree or back to ARU.”).
As per Claim 20, Ovsiannikov/Sen teaches The DSP block of claim 19, wherein: the input circuitry configurable to receive a third value and a fourth value from the second DSP block (Ovsiannikov [0505] “Reduction fabric 111 performs “inter-tile” reduction (as opposed to intra-tile reduction accomplished by adder trees 128A and 128B) for all reduction configurations”);
and the second adder circuitry is configurable to: receive the second sum and the sixth sum and generate a tenth sum by adding the second sum and the sixth sum; receive the tenth sum and the fourth value and generate an eleventh sum by adding the tenth sum and the fourth value; receive the ninth sum and the seventh sum and generate a twelfth sum by adding the ninth sum and the seventh sum; and receive the twelfth sum and the third value and generate a thirteenth sum by adding the twelfth sum and the third value (Ovsiannikov[0505] “Reduction fabric 111 is comprised of a reconfigurable adder tree made up of reduce-and-accumulate (RAA) nodes 520 illustrated in FIG. 5A…. RAA receives inputs either from same tile column ARUs 167 where that RAA node is located or inputs from other RAA nodes.”), wherein:
However, while Ovsiannikov teaches mixing data types with a Type Converter (Ovsiannikov [0358]), and adders comprising of a combination of physical adders and multiplexers (Ovsiannikov [0296]), Ovsiannikov does not explicitly teach the twelfth sum and the thirteenth sum each have a first number of mantissa bits; the third sum and the fourth sum each have a second number of mantissa bits; and the first number of mantissa bits and the second number of mantissa bits are different.
Langhammer teaches the twelfth sum and the thirteenth sum each have a first number of mantissa bits (Langhammer Fig 2, Fig. 6, [0139] “Consider further that A, B, C, and D are mantissas of single-precision floating-point numbers (i.e., include 23 bits).”;
the third sum and the fourth sum each have a second number of mantissa bits; and the first number of mantissa bits and the second number of mantissa bits are different (Langhammer [0139] “If desired, at least one of A, B, C, and D may be an extended mantissa of a single-precision floating-point number (i.e., include more than 23 bits).”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the adder trees and reduction fabric of Ovsiannikov (Ovsiannikov Fig. 1A element 111, Fig. 1B element 128A-B, 1) with the specialized processing blocks of Langhammer (Fig. 2, Fig. 6, [0132]). One would have been motivated to combine these references because the references disclose summation of multiple inputs, and Langhammer increases the efficiency of Ovsiannikov to perform fixed-point and/or floating-point operations (Langhammer [0041]).
Allowable Subject Matter
Claims 21, 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The statement of reasons for the indication of allowable subject matter was addressed in the non-final action mailed 12/12/2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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