DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) and in further view of Bartley et al, hereinafter Bartley (US 2012/0098140 A1).
Regarding claim 1: Gandhi teaches (fig.1) a die module, comprising: a base die (104), wherein the base die (104) comprises a functional block (first functional die closest to 104, hereinafter 106-1) block, the base die having a lateral width; and a chiplet (die above 106-1 hereinafter 106-2) coupled (106-2 is electrically coupled to 104, col.4 lines 60-67 and col.5 lines 1-21) to the base die (104) proximate to the functional block (106-1), wherein the chiplet (106-2) comprises similar functionality (106-1 and 106-2 can be the same type of die having the same functionality) as the functional block (106-1).
Gandhi is silent to teach the chiplet having a lateral width less than the lateral width of the base die.
Bartley teaches (fig.17) a chiplet (610-604) having a lateral width less than the lateral width of the base die (612).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the widths of the chiplets and base die of Bartley in the device of Gandhi to have the predictable result of enabling the capabilities of chip-chip and chip-wafer bonding to be simultaneously leveraged to achieve high density interconnects while mixing and matching die sizes, aspect ratios and functions, and while controlling yield to acceptable levels depending on specs required during manufacturing. (par.119-120 of Bartley)
Regarding claim 1(alternative interpretation): Gandhi teaches (fig.1) a die module, comprising: a base die (104), wherein the base die (104) comprises a functional block (106); and a chiplet (112) coupled (112 is electrically coupled to 104, col.4 lines 60-67 and col.5 lines 1-21) to the base die (104) proximate to the functional block (106), wherein the chiplet (112 can include memory, processor and IO functional features similar to 104, col.5 lines 22-34 and col.4 lines 39-51) comprises similar functionality as the functional block (106).
Gandhi is silent to teach the chiplet having a lateral width less than the lateral width of the base die.
Bartley teaches (fig.17) a chiplet (610-604) having a lateral width less than the lateral width of the base die (612).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the widths of the chiplets and base die of Bartley in the device of Gandhi to have the predictable result of enabling the capabilities of chip-chip and chip-wafer bonding to be simultaneously leveraged to achieve high density interconnects while mixing and matching die sizes, aspect ratios and functions, and while controlling yield to acceptable levels depending on specs required during manufacturing. (par.119-120 of Bartley)
Regarding claim 3: Gandhi teaches the die module of claim 1, wherein the functional block (106) is a processor core (col.4, lines 34-39).
Regarding claim 4: Gandhi teaches the die module of claim 1, wherein the functional block (106) is an IO block (col.4, lines 34-39).
Regarding claim 5: Gandhi teaches the die module of claim 1, wherein the functional block (106) is a memory block (col.4, lines 34-39).
Regarding claim 6: Gandhi teaches the die module of claim 1, wherein the chiplet (112) is coupled (112 is electrically coupled to 104 by hybrid bonding) to the base die (104) with a hybrid bonding architecture (col.5, lines 3-12).
Regarding claim 8: Gandhi teaches the die module of claim 1, wherein the base die (104) has a backside surface (BS as shown in fig. below) and a front side surface (FS as shown in fig. below), wherein first level interconnects (FLIs) (154) are on the front side surface (FS) of the base die (104).
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Regarding claim 9: Gandhi teaches die module of claim 8, wherein the chiplet (112) is coupled (112 is electrically coupled to 104 col.4 lines 60-67 and col.5 lines 1-21) to the backside surface (BS) of the base die (104).
Claim 2 and 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) as applied in claim 1 and in further view of Salmon (US 11,393,807 B2).
Regarding claim 2: Ghandi teaches the die module (102) of claim 1, wherein the functional block (106) is isolated from the circuitry of the base die (104),
Ghandi is silent to explicitly teach the chiplet (112) replaces the functional block (106).
Salmon teaches clusters of coupled chips with similar functionality that are isolated from one another (such as in fig.29) can include redundancy features where a failed chip cluster can be switched off and replaced by another cluster. (c.41 lines 42-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date for the device of Ghandi to include the redundancy features mentioned in Salmon since the functional block 106 and chiplet 112 of Ghandi have similar functionality to each other and have independent functionality to allow for swapping one for the other in the case of failure as mentioned in Salmon and doing so would give the predictable result of a more robust electronic device with higher reliability and availability of use. (c.41 lines 50-54 of Salmon).
Regarding claim 7: Ghandi teaches the die module of claim 6,
Gandhi is silent to explicitly teach wherein interconnects (130 of Ghandi) in the hybrid bonding architecture have a pitch that is approximately 10 µm or smaller.
Salmon teaches hybrid bumps can be used in microbump pitches for flip chips of 40 microns or less, col.51 lines 1-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the microbump pitch size as taught by Salmon in the device of Ghandhi since hybrid bumps are commonly known to be employed in semiconductor devices with line and space dimensions finer than 2 micron and would have the predictable result of saving space, reducing cost of manufacture, and improving performance of the semiconductor device. (col.37 lines 13-28 of Salmon)
Claims 15-18, 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) and Bartley (US 2012/0098140 A1) and in further view of Salmon (US 11,393,807 B2).
Regarding claim 15: Ghandi teaches (fig.1) an electronic package (100), comprising: a package substrate (134); and a die module (102) coupled to the package substrate (134), wherein the die module (102) comprises: a base die (104) with a first surface (bottom side of 104 , hereinafter BS) and a second surface (top side of 104, hereinafter TS), wherein the first surface (BS) faces the package substrate (134), and wherein the base die (104) comprises a plurality of functional blocks (106) the base die having a lateral width; and a chiplet (112) coupled (112 is electrically coupled to 104, col.4 lines 60-67 and col.5 lines 1-21) to the base die (104),
Ghandi is silent to teach wherein the chiplet replaces a functionality of one of the plurality of functional blocks.
Salmon teaches clusters of coupled chips with similar functionality that are isolated from one another (such as in fig.29) can include redundancy features where a failed chip cluster can be switched off and replaced by another chip cluster. (c.41 lines 42-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date for the device of Ghandi to include the commonly known redundancy features mentioned in Salmon since the functional block 106 and chiplet 112 have similar functionality and have independent functionality to allow for swapping one to the other as mentioned in Salmon and doing so would give the predictable result of a more robust electronic device with higher reliability and availability. (c.41 lines 50-54 of Salmon).
Gandhi is silent to teach the chiplet having a lateral width less than the lateral width of the base die.
Bartley teaches (fig.17) a chiplet (610-604) having a lateral width less than the lateral width of the base die (612).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the widths of the chiplets and base die of Bartley in the device of Gandhi to have the predictable result of enabling the capabilities of chip-chip and chip-wafer bonding to be simultaneously leveraged to achieve high density interconnects while mixing and matching die sizes, aspect ratios and functions, and while controlling yield to acceptable levels depending on specs required during manufacturing. (par.119-120 of Bartley)
Regarding claim 16: Ghandi in view of Salmon teaches the electronic package of claim 15, wherein the functional block (106) that is replaced is a processor core (col.4, lines 34-39).
Regarding claim 17: Ghandi in view of Salmon teaches the electronic package of claim 15, wherein the functional block (106) that is replaced is an IO block (col.4, lines 34-39).
Regarding claim 18: Ghandi in view of Salmon teaches the electronic package of claim 15, wherein the chiplet (112) is over the first surface (BS) of the base die (104).
Regarding claim 21: Ghandi in view of Salmon teaches the electronic package of claim 15, wherein the chiplet (112) is coupled (112 is electrically coupled to 104 by hybrid bonding) to the base die (104) by hybrid bonding (col.5, lines 3-12)
Regarding claim 22: Ghandi in view of Salmon teaches the electronic package of claim 21, wherein interconnects of the hybrid bonding have a pitch that is approximately 10 µm or smaller. (Salmon teaches hybrid bumps can be used in microbump pitches for flipchips of 40 microns or less, col.51 lines 1-5).
Regarding claim 23: Ghandi teaches an electronic system, comprising: a board (PCB not shown. C.5 lines 62-63); a package substrate (134) coupled to the board (PCB); and a die module (102) coupled to the package substrate (134), wherein the die module (102) comprises: a base die (104) with a plurality of functional blocks (106); and a chiplet (112) coupled to the base die (104) over one of the plurality of functional blocks (106),
Ghandi is silent to teach wherein individual ones of the plurality of functional blocks (106) comprise selector circuitry; the chiplet (112) is selected by the selector circuitry and the respective functional block (106) is turned off.
Salmon teaches clusters of coupled chips with similar functionality that are isolated from one another (such as in fig.29) can include redundancy features where a failed chip cluster can be switched off by selector circuitry and replaced by another chip cluster. (c.41 lines 42-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date for the device of Ghandi to include the commonly known redundancy features mentioned in Salmon since the functional block 106 and chiplet 112 have similar functionality and have independent functionality to allow for swapping one to the other as mentioned in Salmon and doing so would give the predictable result of a more robust electronic device with higher reliability and availability. (c.41 lines 50-54 of Salmon).
Gandhi is silent to teach the chiplet having a lateral width less than the lateral width of the base die.
Bartley teaches (fig.17) a chiplet (610-604) having a lateral width less than the lateral width of the base die (612).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the widths of the chiplets and base die of Bartley in the device of Gandhi to have the predictable result of enabling the capabilities of chip-chip and chip-wafer bonding to be simultaneously leveraged to achieve high density interconnects while mixing and matching die sizes, aspect ratios and functions, and while controlling yield to acceptable levels depending on specs required during manufacturing. (par.119-120 of Bartley)
Regarding claim 24: Ghandi in view of Salmon teaches the electronic system of claim 23, wherein the chiplet (112) is a processor core (col.5, lines 22-34).
Regarding claim 25: Ghandi in view of Salmon teaches the electronic system of claim 23, wherein the chiplet (112) is an IO block (col.5, lines 22-34).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) and Bartley (US 2012/0098140 A1) as applied in claim 1 and in further view of Jo (US 2017/0154868 A1).
Regarding claim 13: Gandhi teaches the die module of claim 1
Gandhi is silent to teach a dummy die adjacent to the chiplet, wherein the dummy die has a surface that is substantially coplanar with a surface of the chiplet facing away from the base die.
Gandhi in view of JO teaches (fig.4 of Jo) teach a dummy die (360 of JO) adjacent to the chiplet (360 of JO would be in the device of Gandhi adjacent to chiplet 112 of Gandhi), wherein the dummy die (360 of JO) has a surface that is substantially coplanar (as shown in fig. 4 of Jo) with a surface of the chiplet (112 of Gandhi) facing away from the base die (104 of Gandhi).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to include the dummy dies of Jo in the device of Gandhi in order to have the predictable result of supporting lower and upper dies and provide electrical isolation to parts of the dies for improved reliability of the device. (par.46 of JO)
Regarding claim 14: Gandhi in view of JO teaches the die module of claim 13, wherein the dummy die (360 of Jo) is coupled to the base die (104 of Gandhi) by hybrid bonding or an adhesive (360 of Jo would be bonded by adhesive tape 370 of Jo to 104 of Ghandi).
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) and Bartley (US 2012/0098140 A1) as applied in claim 15 and in further view of Jo (US 2017/0154868 A1).
Regarding claim 20: Ghandi teaches the electronic package of claim 15
Ghandi is silent to explicitly teach a dummy die adjacent to the chiplet wherein the dummy die is a silicon substrate without active circuitry.
Gandhi in view of JO teaches (fig.4 of Jo) teach a dummy die (360 of JO) adjacent to the chiplet (360 of JO would be in the device of Gandhi adjacent to chiplet 112 of Gandhi), wherein the dummy die (360 of JO) does not have active circuitry.
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to include the dummy dies of Jo in the device of Gandhi in order to have the predictable result of supporting lower and upper dies and provide electrical isolation to parts of the dies for improved reliability of the device. (par.46 of JO)
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention for the dummy die of Jo to be a silicon substrate in order to have similar coefficient of expansion as the substrate (substrate of the dies are formed of Si mentioned in p.60).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al, hereinafter Gandhi (US 11,302,674 B2) and Bartley (US 2012/0098140 A1).
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Regarding claim 10: Gandhi teaches the die module of claim 9,
Gandhi is silent to explicitly teach wherein the base die (104) comprises through silicon vias to connect to the chiplet (112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include through silicon vias (TSV) to the base die 104 since 104 is vertically stacked with 106 and having TSVs in stacked chips is commonly known in various electronic devices to allow for better efficiency and performance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10,13-18 and 20-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY VERDES whose telephone number is (703)756-1401. The examiner can normally be reached Monday - Friday 07:30 - 03:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICKY VERDES/
Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898