How Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Response filed on 8 April 2025, responding to the Office action on 16 January 2025 has been entered. Applicant has canceled claim 10 and amended claims 1, 8, 15, and 21.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, 15, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has canceled claim 10. Rejection of claim 10 is withdrawn.
Applicant asserts that amended claim limitations of amended claims 1, 8 , 15, and 21 overcome cited prior art due to Kitazaki not disclosing the gate electrode of the access transistor as laterally adjacent to the node. New grounds for rejection provided in view of the amended claim limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 8-9, 11, 13-16 rejected under 35 U.S.C. 103 as being unpatentable over Kitazaki US PGPUB No. 20100039850 (hereinafter Kitazaki) in view of Ramaswamy et al. US PGPUB No. 20200234751 (hereinafter Ramaswamy).
Regarding claim 1, Kitazaki discloses (fig. 9-10, 13-14) a memory device, comprising:
a plateline (PL, ¶32, 34, 109, 111);
a capacitor (FC111, ¶33, 44, 112) coupled to the plateline (PL),
wherein the capacitor (FC111) is a vertical trench capacitor and includes a ferroelectric material (51, fig. 10, ¶124) between the plateline (PL) and a node (61, ¶112, 114); and
an access transistor (TC, ¶112-115) coupled to the capacitor (FC111) via the node (61).
Kitazaki does not disclose wherein a gate electrode of the access transistor is laterally adjacent to the node. In the same field of endeavor, Ramaswamy discloses (fig. 1) ferroelectric transistors, wherein a gate electrode (18 or 22, Ramaswamy ¶19) of the access transistor (12 or 14, Ramaswamy ¶19) is laterally adjacent (Ramaswamy fig. 1) to the node (39, Ramaswamy ¶32). It would have been obvious to one of ordinary skill in the art at the time of filing to use the arrangement of transistors disclosed by Ramaswamy in the device of Kitazaki, improving energy efficiency by increasing transistor density within the device.
Regarding claim 8, Kitazaki discloses (fig. 9-10, 13-14) a memory device, comprising:
a plateline (PL, ¶32, 34, 109, 111);
a capacitor (FC111, ¶33, 44, 112) coupled to the plateline (PL), wherein the capacitor (FC111) is a vertical trench capacitor and includes a ferroelectric material (51, fig. 10, ¶124) between the plateline (PL) and a node (61, ¶112, 114);
an access transistor (TC, ¶112-115) coupled to the capacitor (FC111) via the node (61),
a bitline (BL11, ¶46) perpendicular to the plateline (PL); and
a wordline (WL, ¶32, 34, 109, 113-114) parallel to the plateline (PL). Kitazaki discloses a bitline (BL1j, j=integer of individual bitlines) in column direction and wordline (WL) and plateline (PL) in the row direction (¶32).
Kitazaki does not disclose wherein a gate electrode of the access transistor is laterally adjacent to the node. In the same field of endeavor, Ramaswamy discloses (fig. 1) ferroelectric transistors, wherein a gate electrode (18 or 22, Ramaswamy ¶19) of the access transistor (12 or 14, Ramaswamy ¶19) is laterally adjacent (Ramaswamy fig. 1) to the node (39, Ramaswamy ¶32). It would have been obvious to one of ordinary skill in the art at the time of filing to use the arrangement of transistors disclosed by Ramaswamy in the device of Kitazaki, improving energy efficiency by increasing transistor density within the device.
Regarding claim 9, Kitazaki in view of Ramaswamy discloses the memory device of claim 8,
wherein the access transistor (TC, Kitazaki ¶112-115) is coupled to the bitline (BL11, Kitazaki ¶46).
Regarding claim 11, Kitazaki in view of Ramaswamy discloses the memory device of claim 8,
wherein a gate of the access transistor is coupled to the wordline (The wordline is coupled to the gate as the “Word line WL functions as a gate electrode of cell transistor TC,” Kitazaki ¶113).
Regarding claim 13, Kitazaki in view of Ramaswamy discloses the memory device of claim 8,
wherein the wordline (WL, Kitazaki ¶32, 34, 109, 113-114) is coupled to a gate of a semiconductor-based transistor (from another TC such as that near FC121 within the memory cell, Kitazaki fig. 9-10, ¶44-47, based on the definition of “coupled” provided in the Specification ¶14 of the instant application).
Regarding claim 14, Kitazaki in view of Ramaswamy discloses the memory device of claim 13,
wherein the semiconductor-based transistor (TC) comprises silicon (Kitazaki ¶113), gallium nitride, an oxide semiconductor, or a transition metal dichalcogenide (TMD) material.
Regarding claim 15, Kitazaki discloses (fig. 9-10, 13-14) a memory device, comprising:
a plate (PL, ¶32, 34, 109, 111);
a capacitor (FC111, ¶33, 112) coupled to the plate, wherein the capacitor is a vertical trench capacitor and includes a ferroelectric material (51, fig. 10, ¶124) between the plate and a node (61, ¶112, 114); and
an access transistor (TC, ¶112-115) coupled to the FC111 via the node (61).
Kitazaki does not disclose wherein a gate electrode of the access transistor is laterally adjacent to the node. In the same field of endeavor, Ramaswamy discloses (fig. 1) ferroelectric transistors, wherein a gate electrode (18 or 22, Ramaswamy ¶19) of the access transistor (12 or 14, Ramaswamy ¶19) is laterally adjacent (Ramaswamy fig. 1) to the node (39, Ramaswamy ¶32). It would have been obvious to one of ordinary skill in the art at the time of filing to use the arrangement of transistors disclosed by Ramaswamy in the device of Kitazaki, improving energy efficiency by increasing transistor density within the device.
Regarding claim 16, Kitazaki in view of Ramaswamy in discloses the memory device of claim 15,
wherein the access transistor (TC, Kitazaki ¶112-115) is coupled to a bitline (BL11, Kitazaki ¶46).
Claims 2-7, 12, 17-20 rejected under 35 U.S.C. 103 as being unpatentable over Kitazaki and Ramaswamy in view of Manipatruni et al. US PGPUB No 20200273865 (hereinafter Manipatruni).
Regarding claim 2, Kitazaki in view of Ramaswamy discloses the memory device of claim 1.
Kitazaki in view of Ramaswamy does not disclose a bitline parallel to the plateline. In the same field of endeavor, Manipatruni discloses (fig. 2A-2D) the plateline (PL) and bitline (BL, Manipatruni ¶45) as parallel (Manipatruni ¶63). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to place the plateline and bitline parallel disclosed by Manipatruni in the device by Kitazaki modified by Ramaswamy to improve the density of memory by reducing the memory bit-cell footprint.
Regarding claim 3, Kitazaki in view of Ramaswamy and Manipatruni discloses the memory device of claim 2,
wherein the access transistor TC (Kitazaki ¶112-115) is coupled to the bitline (BL11, Kitazaki ¶46).
Regarding claim 4, Kitazaki in view of Ramaswamy discloses the memory device of claim 1.
Kitazaki does not disclose the wordline perpendicular to the plateline as both are in the row direction (¶32). In the same field of endeavor, Manipatruni discloses (fig. 2A) the wordline (WL) perpendicular to the plateline (PL) (Manipatruni ¶63). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to place the wordline perpendicular to the plateline as disclosed by Manipatruni in the device by Kitazaki to allow for different signal propagation paths, potentially reducing delay and allowing for more efficient selection and access of memory cells.
Regarding claim 5, Kitazaki in view of Ramaswamy and Manipatruni discloses the memory device of claim 4,
wherein the wordline (WL/217, Manipatruni ¶63) coupled to a semiconductor-based transistor MN2 (Manipatruni fig 2A, ¶49).
In the alternative, the wordline (WL) (Kitazaki ¶32, 34, 109, 113-114) is coupled indirectly to a gate of a semiconductor-based transistor from another TC such as that near FC121 within the memory cell (Kitazaki fig. 9-10, ¶44-47) based on the instant applications definition of “coupled” provided in the Specification ¶14.
Regarding claim 6, Kitazaki in view of Ramaswamy and Manipatruni discloses the memory device of claim 5,
wherein the semiconductor-based transistor (TC) comprises silicon (Kitazaki ¶113), gallium nitride, an oxide semiconductor, or a transition metal dichalcogenide (TMD) material.
Regarding claim 7, Kitazaki in view of Ramaswamy discloses the memory device of claim 1,
wherein the access transistor (TC, Kitazaki ¶112-115) includes a dielectric material (GD, Kitazaki ¶126) and a spacer (31, Kitazaki ¶127). Kitazaki does not disclose the spacer region is between the dielectric material and the node.
In the same field of endeavor, Manipatruni discloses (fig. 2A), wherein the access transistor MN (Manipatruni ¶49) includes a dielectric material 205 (Manipatruni ¶49), and a spacer region 206a (Manipatruni ¶49) between the dielectric material and the node 209b (Manipatruni ¶60). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the spacer disclosed by Manipatruni in the device by Kitazaki modified by Ramaswamy to lower leakage current and prevent short-channel effects.
Regarding claim 12, Kitazaki in view of Ramaswamy discloses the memory device of claim 11,
wherein the access transistor (TC, Kitazaki ¶112-115) includes a dielectric material (GD, Kitazaki ¶126) and a spacer region (31, Kitazaki ¶127). Kitazaki does not disclose the spacer region between the dielectric material GD and the node (61, Kitazaki ¶112, 114).
In the same field of endeavor, Manipatruni discloses (fig. 2A), wherein the access transistor MN (Manipatruni ¶49) includes a dielectric material 205 (Manipatruni ¶49), and a spacer region 206a (Manipatruni ¶49) between the dielectric material and the node 209b (Manipatruni ¶60). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the spacer disclosed by Manipatruni in the device by Kitazaki to lower leakage current and prevent short-channel effects.
Regarding claim 17, Kitazaki in view of Ramaswamy discloses the memory device of claim 15.
Kitazaki does not disclose the wordline perpendicular to the plateline as both are in the row direction (¶32). In the same field of endeavor, Manipatruni discloses (fig. 2A) the WL perpendicular to the plateline (PL) (Manipatruni ¶63). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to place the wordline perpendicular to the plateline as disclosed by Manipatruni in the device by Kitazaki to allow for different signal propagation paths, potentially reducing delay and allowing for more efficient selection and access of memory cells.
Regarding claim 18, Kitazaki in view of Ramaswamy and Manipatruni discloses the memory device of claim 17.
Kitazaki discloses wherein the wordline (WL, Kitazaki ¶32, 34, 109, 113-114) is coupled to a gate of a semiconductor-based transistor (from another TC such as that near FC121 within the memory cell, Kitazaki fig. 9-10, ¶44-47, based on the definition of “coupled” provided in the Specification ¶14 of the instant application).
Regarding claim 19, Kitazaki in view of Manipatruni discloses the memory device of claim 18,
wherein the semiconductor-based transistor (TC) comprises silicon (Kitazaki ¶ 0113), gallium nitride, an oxide semiconductor, or a transition metal dichalcogenide (TMD) material.
Regarding claim 20, Kitazaki in view of Ramaswamy discloses the memory device of claim 15,
wherein the access transistor (TC, Kitazaki ¶112-115) includes a dielectric material (GD, Kitazaki ¶126) and a spacer region (31, Kitazaki ¶127).
Kitazaki does not disclose the spacer layer between the dielectric material (GD) and the node (61, Kitazaki ¶112, 114).
In the same field of endeavor, Manipatruni discloses (fig. 2A), wherein the access transistor MN (Manipatruni ¶49) includes a dielectric material 205 (Manipatruni ¶49), and a spacer region 206a (Manipatruni ¶49) between the dielectric material and the node 209b (Manipatruni ¶60). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the spacer disclosed by Manipatruni in the device by Kitazaki to lower leakage current and prevent short-channel effects.
Claims 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Kitazaki and Ramaswamy in view of Sharma US PGPUB No 20200373312 (hereinafter Sharma).
Regarding claim 21, Kitazaki (fig. 9-10, 13-14) discloses a memory device comprising:
a plateline (PL, ¶32, 34, 109, 111);
a capacitor (FC111, ¶33, 44, 112) coupled to the plateline (PL),
wherein the capacitor (FC111) is a vertical trench capacitor and includes a ferroelectric material (51, fig. 10, ¶124) between the plateline (PL) and a node (61, ¶112, 114); and
an access transistor (TC, ¶112-115) coupled to the capacitor (FC111) via the node (61).
Kitazaki does not disclose wherein a gate electrode of the access transistor is laterally adjacent to the node. In the same field of endeavor, Ramaswamy discloses (fig. 1) ferroelectric transistors, wherein a gate electrode (18 or 22, Ramaswamy ¶19) of the access transistor (12 or 14, Ramaswamy ¶19) is laterally adjacent (Ramaswamy fig. 1) to the node (39, Ramaswamy ¶32). It would have been obvious to one of ordinary skill in the art at the time of filing to use the arrangement of transistors disclosed by Ramaswamy in the device of Kitazaki, improving energy efficiency by increasing transistor density within the device.
Kitazaki does not disclose the memory device coupled to a board within a computing device. In the same field of endeavor, Sharma (fig. 1, 11) discloses a computing device 1100 (Sharma ¶55), comprising: a board 1102 (Sharma ¶55); and a component coupled to the board 1102, the component including a memory device DRAM (fig. 11, Sharma ¶56).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to replace the DRAM with the memory device of Kitazaki in order to remove the need of continuous power supply requirements of DRAM and improved write endurance.
Regarding claim 22, Kitazaki in view of Ramaswamy and Sharma discloses the computing device of claim 21,
further comprising a processor (1104, Sharma ¶55) coupled to the board, a communication chip (1106, Sharma ¶55) coupled to the board, or a camera (Sharma fig. 11) coupled to the board.
Regarding claim 23, Kitazaki in view of Ramaswamy and Sharma discloses the computing device of claim 21,
wherein the component is a packaged integrated circuit die (Sharma ¶1-3, 16, 19).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Seth Lawson whose telephone number is (703)756-5675. The examiner can normally be reached M-F 8-5 PST.
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/Seth D Lawson/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893