Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20210344618A1 (Zheng) in view of US10419338B2 (Gray) in view of US20190042915A1 (Akin) in view of US20150006776A1 (Liu) and further in view of US20090065813A1 (Cox).
In regards to claim 1 (Zheng) shows a system comprising:
an array of neural cores, the array having at least two dimensions; Zheng [0038] teaches this by describing a chiplet layer with an array of routers for an array of cores, interconnected in a clear, two-dimensional layout, showing the required multidimensional core array structure.
wherein at least one of the plurality of signal wires is disposed along each dimension of the array of neural cores, and each of the plurality of signal wires is disposed along at least one dimension of the array; Zheng [0039] teaches this concept by detailing how each router 450 is connected to four adaptable links, which include links running perpendicular and parallel, thus covering multiple dimensions of the router array. This setup ensures that signal wires are aligned with both the columns and rows, corresponding to the dimensions of the array.
a plurality of routers, each of which is operatively coupled to (i) one of the plurality of neural cores and (ii) at least two of the signal wires, one along each of the dimensions of the array of neural cores; Zheng [0038 - 0039] teaches that each router 450 is part of a chiplet layer connected to an array of cores, and each router is linked via adaptable links that extend in perpendicular directions, covering each dimension of the router array.
wherein each of the plurality of routers is configured to selectively route a signal from one of its at least two coupled signal wires to its coupled neural core; Zheng [0042] teaches that routers use multiplexers and adaptable links to dynamically choose which signal wire to connect, allowing selection of signal path from multiple signal wires to a specific core.
each of the plurality of routers is configured to selectively route a signal from its coupled neural core to one of its at least two coupled signal wires; Zheng [0045] teaches that routers use adaptable links with link switches, such as 528a and 528c, to dynamically connect and route signals from a neural core (router 450a) to any selected one of multiple signal paths, demonstrating the routers’ capability to selectively direct outputs from cores to various signal wires.
Zheng differs from the claimed invention in that it does not explicitly disclose wherein each of the neural cores comprises a plurality of ordered input wires, a plurality of ordered output wires; a plurality of synapses, each of the synapses operatively coupled to one of the plurality of input wires and one of the plurality of output wires; each of the synapses is adapted to apply a synaptic weight; a plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Gray teaches wherein each of the neural cores comprises a plurality of ordered input wires, a plurality of ordered output wires; Gray [Column 12 Line 55 - 65] teaches this with routers having structured input ports and output ports arranged in a specific order, demonstrating the architecture of processing elements with organized input and output pathways.
Gray teaches a plurality of synapses, each of the synapses operatively coupled to one of the plurality of input wires and one of the plurality of output wires; Gray [Column 13 Line 25 - 35] teaches this concept through switch circuits that create configurable connections between specific inputs and outputs, determining how signals propagate from input wires to output wires in a manner functionally similar to synaptic connections in neural networks.
Gray differs from the claimed invention in that it does not explicitly disclose each of the synapses is adapted to apply a synaptic weight; a plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Akin teaches each of the synapses is adapted to apply a synaptic weight; Akin [0033-0034] teaches that neural networks learn by changing connection strengths between neurons, where connections become stronger when specific signal patterns are repeated frequently.
Akin differs from the claimed invention in that it does not explicitly disclose a plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Liu teaches a plurality of signal wires, the plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; Liu [0044-0045, FIG. 4] teaches a multi-core chip interconnect comprising co-existing horizontally-oriented ring mesh segments (402, 404, 406, 408) and vertically-oriented ring mesh segments (410, 412, 414, 415) as structurally distinct, direction-specific wire structures, wherein each tile connects to one horizontally-oriented ring and one vertically-oriented ring, and the ring stop at each tile forms a plus-sign intersection point where the horizontal and vertical rings meet, thereby teaching one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh as co-existing wire mesh structures.
Liu differs from the claimed invention in that it does not explicitly disclose wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Cox teaches wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes; Cox [0082, 0087, 0095] teaches arranging metal routing layers in pairs of parallel routing grids where one layer’s wires primarily run vertically adjacent to another layer’s wires primarily running horizontally, and configuring the interconnect by selecting only the necessary connecting vias (e.g., VIA23 and VIA45) while omitting the remaining potential vias, thereby forming a vertical-only routing mesh and a horizontal-only routing mesh from the two parallel meshes.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to create efficient neural processing architectures with organized input/output pathways and configurable signal routing.
The motivation to combine Zheng, Gray, and Akin at the effective filing date of the invention is to create a neuromorphic computing architecture capable of dynamic signal routing and adaptive synaptic weight optimization.
The motivation to combine Zheng, Gray, Akin, and Liu at the effective filing date of the invention is to reduce energy consumption in neural core routing by separating the routing fabric into direction-specific mesh structures.
The motivation to combine Zheng, Gray, Akin, Liu, and Cox at the effective filing date of the invention is to efficiently form the direction-specific horizontal-only and vertical-only meshes from the parallel plus-sign meshes by selectively removing connecting vias, thereby increasing the number of useful routing tracks and relieving routing bottlenecks.
In regards to claim 2 (Zheng) shows the system of claim 1:
wherein at least one of the plurality of signal wires is disposed along both of the at least two dimensions; Zheng [0039] teaches this by describing adaptable links that connect columns and rows of routers, showing signal wires extending across both dimensions within the router array.
In regards to claim 3 (Zheng) shows the system of claim 1:
wherein each of the plurality of routers is coupled to its at least two of the signal wires at the edge of its coupled one of the plurality of neural cores; Zheng [0039] teaches this by detailing routers above adaptable links that connect in column and row arrangements. These links show routers at core edges connected to multiple signal paths aligned with the array’s dimensions.
In regards to claim 4 (Zheng) shows the system of claim 1:
wherein each of the plurality of routers is coupled to its one of the plurality of neural cores at a synapse of its one of the plurality of neural cores; Zheng [0039] teaches this by detailing routers above adaptable links that connect in column and row arrangements. These links show routers at core edges connected to multiple signal paths aligned with the array’s dimensions, demonstrating how routers couple to cores at specific junction points that function as synaptic connections.
In regards to claim 5 (Zheng) does not show the system of claim 1, wherein one signal wire corresponds to each of the plurality of input wires of the neural cores and one signal wire corresponds to each of the plurality of output wires of the neural cores.
Gray teaches wherein one signal wire corresponds to each of the plurality of input wires of the neural cores and one signal wire corresponds to each of the plurality of output wires of the neural cores; Gray [Column 5 Lines 18-27] teaches link structures where logically parallel wires form communicative coupling channels that carry messages directly between routers, establishing direct correspondence between router interface connections and signal paths.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to leverage Zheng’s architectural layout with Gray’s precise synaptic-like connections to improve signal routing and processing efficacy in neural network architectures.
In regards to claim 6 (Zheng) shows the system of claim 5:
wherein the signal wires are disposed in a plane parallel to the neural cores; Zheng [0039] teaches this by describing adaptable links positioned directly beneath the routers, indicating the signal wires’ placement in a parallel plane to the neural core array.
In regards to claim 7 (Zheng) shows the system of claim 5:
wherein the plurality of signal wires are disposed in a mesh; Zheng [0061] teaches this as it describes a mesh topology where routers are interconnected by mesh links, showing that signal wires form a mesh network across the router array.
In regards to claim 8 (Zheng) shows the system of claim 1:
wherein each of the plurality of routers is configured to selectively bypass its coupled neural core; Zheng [0052] teaches this by explaining how routers can connect to an interposer switch to bypass cores directly for faster inter-router communication, highlighting the use of multiplexers and bypass links in this configuration.
In regards to claim 9 (Zheng) shows the system of claim 1:
wherein each of the plurality of routers is configured to transmit a signal in two directions along the at least one signal wire; Zheng [0041] teaches this by detailing how each router is connected to adaptable links allowing signals to travel in both column and row directions, facilitated by multiplexers that manage the bidirectional flow on these links.
In regards to claim 10 (Zheng) shows the system of claim 1:
wherein each of the plurality of digital buffers is configured for signal restoration; Zheng [0049] teaches this with tri-state transistors that reconnect to power, resuming and restoring signal transmission, thus acting as digital buffers.
Zheng differs from the claimed invention in that it does not explicitly disclose further comprising a plurality of digital buffers, each of which is operatively coupled to one of the plurality of routers.
Gray teaches further comprising a plurality of digital buffers, each of which is operatively coupled to one of the plurality of routers; Gray [Column 11 Lines 30 - 50] teaches this with pipeline registers in the links between routers, which temporarily store and forward message data as it travels between router nodes.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to enhance signal integrity and processing speed within a neural network architecture by pairing Zheng’s method of signal restoration with Gray’s structured digital buffering.
In regards to claim 11 (Zheng) and (Gray) do not show the system of claim 1, wherein the synapses of the plurality of neural cores are configured as a trained neural network.
Akin teaches wherein the synapses of the plurality of neural cores are configured as a trained neural network; Akin [0033-0034] teaches how a neural network learns by changing connection strengths between neurons, making some connections stronger when certain signal patterns are repeated frequently, similar to how the brain learns from experience.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to build efficient neural processing architectures with structured signal routing pathways.
The motivation to combine Zheng, Gray, and Akin at the effective filing date of the invention is to develop a neural network system capable of dynamic synaptic weight optimization and adaptive learning.
In regards to claim 12 (Zheng) does not show the system of claim 1:
Gray teaches wherein a first direction along the signal wires corresponds to forward propagation and a second direction along the signal wires corresponds to backpropagation; Gray [Column 14 Line 50 - 65] teaches distinct signal directions for request messages and response messages, mirroring the concept of forward and backward signal propagation paths in neural networks.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to enable a more functional and bi-directional data flow similar to neural network operations, optimizing both data processing and network training efficiencies.
In regards to claim 13 (Zheng) shows a method comprising:
receiving signals at a plurality of routers via a plurality of signal wires; Zheng [0042] teaches receiving signals at routers via adaptable links, which dynamically connect routers to various signal sources, effectively describing how routers receive signals.
selectively routing, by each of the plurality of routers, the signals from at least one signal wire to a neural core; Zheng [0042] teaches routers using multiplexers to selectively connect to different signal paths, demonstrating selective signal routing to cores.
selectively routing, by the router, a signal from the neural core to the plurality of signal wires; Zheng [0045] illustrates routers dynamically directing signals from cores to other routers or network nodes via configurable link switches, showing bidirectional signal routing.
at least one of the plurality of signal wires is disposed along each dimension of an array of neural cores comprising the neural core, the array having at least two dimensions; Zheng [0039] teaches an interconnection network with adaptable links that connect routers in both row and column directions. Some links connect columns of routers while others extend perpendicularly to connect rows of routers, demonstrating signal wires disposed along each dimension of a two-dimensional array structure.
each of the plurality of signal wires is disposed along at least one dimension of the array; Zheng [0039] teaches adaptable links that each run along either row or column directions, ensuring every signal wire is positioned along at least one dimension of the router array.
each of the plurality of routers is configured to selectively route a signal from one of its at least two coupled signal wires to its coupled neural core; Zheng [0042] teaches that routers use multiplexers and adaptable links to dynamically choose which signal wire to connect, allowing selection of signal path from multiple signal wires to a specific core.
each of the plurality of routers is configured to selectively route a signal from its coupled neural core to one of its at least two coupled signal wires; Zheng [0045] teaches that routers use adaptable links with link switches, such as 528a and 528c, to dynamically connect and route signals from a neural core (router 450a) to any selected one of multiple signal paths, demonstrating the routers’ capability to selectively direct outputs from cores to various signal wires.
Zheng differs from the claimed invention in that it does not explicitly disclose wherein the neural core comprises a plurality of ordered input wires, a plurality of ordered output wires; a plurality of synapses, each of the synapses operatively coupled to one of the plurality of input wires and one of the plurality of output wires; the plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Gray teaches wherein the neural core comprises a plurality of ordered input wires, a plurality of ordered output wires; Gray [Column 12 Line 55 - 65] teaches this with routers having structured input ports and output ports arranged in a specific order, demonstrating the architecture of processing elements with organized input and output pathways.
Gray teaches a plurality of synapses, each of the synapses operatively coupled to one of the plurality of input wires and one of the plurality of output wires; Gray [Column 13 Line 25 - 35] teaches this concept through switch circuits that create configurable connections between specific inputs and outputs, determining how signals propagate from input wires to output wires in a manner functionally similar to synaptic connections in neural networks.
Gray differs from the claimed invention in that it does not explicitly disclose each of the synapses is adapted to apply a synaptic weight; the plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Akin teaches each of the synapses is adapted to apply a synaptic weight; Akin [0033-0034] teaches that neural networks learn by changing connection strengths between neurons, where connections become stronger when specific signal patterns are repeated frequently.
Akin differs from the claimed invention in that it does not explicitly disclose the plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Liu teaches the plurality of signal wires including at least three wire meshes, the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh; Liu [0044-0045, FIG. 4] teaches a multi-core chip interconnect comprising co-existing horizontally-oriented ring mesh segments (402, 404, 406, 408) and vertically-oriented ring mesh segments (410, 412, 414, 415) as structurally distinct, direction-specific wire structures, wherein each tile connects to one horizontally-oriented ring and one vertically-oriented ring, and the ring stop at each tile forms a plus-sign intersection point where the horizontal and vertical rings meet, thereby teaching one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh as co-existing wire mesh structures.
Liu differs from the claimed invention in that it does not explicitly disclose wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes.
Cox teaches wherein two wire meshes that include the horizontal-only mesh and the vertical-only mesh of the three wire meshes are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes; Cox [0082, 0087, 0095] teaches arranging metal routing layers in pairs of parallel routing grids where one layer’s wires primarily run vertically adjacent to another layer’s wires primarily running horizontally, and configuring the interconnect by selecting only the necessary connecting vias (e.g., VIA23 and VIA45) while omitting the remaining potential vias, thereby forming a vertical-only routing mesh and a horizontal-only routing mesh from the two parallel meshes.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to create efficient neural processing architectures with organized input/output pathways and configurable signal routing.
The motivation to combine Zheng, Gray, and Akin at the effective filing date of the invention is to create a neuromorphic computing architecture capable of dynamic signal routing and adaptive synaptic weight optimization.
The motivation to combine Zheng, Gray, Akin, and Liu at the effective filing date of the invention is to reduce energy consumption in neural core routing by separating the routing fabric into direction-specific mesh structures.
The motivation to combine Zheng, Gray, Akin, Liu, and Cox at the effective filing date of the invention is to efficiently form the direction-specific horizontal-only and vertical-only meshes from the parallel plus-sign meshes by selectively removing connecting vias, thereby increasing the number of useful routing tracks and relieving routing bottlenecks.
In regards to claim 14 (Zheng) shows the method of claim 13:
wherein at least one of the plurality of signal wires is disposed along both of the at least two dimensions; Zheng [0039] teaches this by describing adaptable links that connect columns and rows of routers, showing signal wires extending across both dimensions within the router array.
In regards to claim 15 (Zheng) shows the method of claim 13:
wherein each of the plurality of routers is coupled to its at least two of the signal wires at the edge of its coupled one of the plurality of neural cores; Zheng [0039] teaches this by detailing routers above adaptable links that connect in column and row arrangements. These links show routers at core edges connected to multiple signal paths aligned with the array’s dimensions.
In regards to claim 16 (Zheng) shows the method of claim 13:
wherein each of the plurality of routers is coupled to its one of the plurality of neural cores at a synapse of its one of the plurality of neural cores; Zheng [0039] teaches this by detailing routers above adaptable links that connect in column and row arrangements. These links show routers at core edges connected to multiple signal paths aligned with the array’s dimensions, demonstrating how routers couple to cores at specific junction points that function as synaptic connections.
In regards to claim 17 (Zheng) does not show the method of claim 13, wherein one signal wire corresponds to each of the plurality of input wires of the neural cores and one signal wire corresponds to each of the plurality of output wires of the neural cores.
Gray teaches wherein one signal wire corresponds to each of the plurality of input wires of the neural cores and one signal wire corresponds to each of the plurality of output wires of the neural cores; Gray [Column 5 Lines 18-27] teaches link structures where logically parallel wires form communicative coupling channels that carry messages directly between routers, establishing direct correspondence between router interface connections and signal paths.
The motivation to combine Zheng and Gray at the effective filing date of the invention is to leverage Zheng’s architectural layout with Gray’s precise synaptic-like connections to improve signal routing and processing efficacy in neural network architectures.
In regards to claim 18 (Zheng) shows the method of claim 17:
wherein the signal wires are disposed in a plane parallel to the neural cores; Zheng [0039] teaches this by describing adaptable links positioned directly beneath the routers, indicating the signal wires’ placement in a parallel plane to the neural core array.
In regards to claim 19 (Zheng) shows the method of claim 17:
wherein the plurality of signal wires are disposed in a mesh; Zheng [0061] teaches this as it describes a mesh topology where routers are interconnected by mesh links, showing that signal wires form a mesh network across the router array.
In regards to claim 20 (Zheng) shows the method of claim 13:
wherein each of the plurality of routers is configured to selectively bypass its coupled neural core; Zheng [0052] teaches this by explaining how routers can connect to an interposer switch to bypass cores directly for faster inter-router communication, highlighting the use of multiplexers and bypass links in this configuration.
Response to Arguments
Applicant’s arguments filed on August 04, 2026 have been fully considered but are not persuasive for the reasons set forth below.
With respect to independent claims 1 and 13, Applicant argues that Liu fails to disclose "the three wire meshes including one plus-sign mesh, one horizontal-only mesh, and one vertical-only mesh." This argument is not persuasive. Liu [0044]-[0045] and FIG. 4 disclose a ring mesh interconnect having co-existing horizontally-oriented ring interconnect segments (402, 404, 406, 408) and vertically-oriented ring interconnect segments (410, 412, 414, 415), wherein each tile connects to one horizontally-oriented ring and one vertically-oriented ring, and the ring stop at each tile forms the cross-over point between the horizontally-oriented ring and the vertically-oriented ring. The horizontally-oriented rings constitute a horizontal-only mesh, the vertically-oriented rings constitute a vertical-only mesh, and the ring stops at which the horizontal and vertical rings intersect constitute a plus-sign mesh, thereby teaching the recited three co-existing wire meshes.
Applicant further argues that the cited references fail to disclose the newly added limitation reciting that the horizontal-only and vertical-only meshes "are constructed from two parallel plus-sign meshes with connecting vias removed for one of the two wire meshes." This limitation is addressed by Cox. Cox [0082, 0087, 0095] discloses arranging metal routing layers as parallel routing grids in which one layer’s wires primarily run vertically adjacent to another layer’s wires primarily running horizontally, and configuring the interconnect by selecting only the necessary connecting vias while omitting the remaining potential vias, thereby forming a vertical-only routing mesh and a horizontal-only routing mesh from the parallel meshes. This is further consistent with Applicant’s own specification at paragraphs [0027]-[0030], which describes deriving the horizontal-only and vertical-only meshes from a plus-sign mesh by removing connecting vias.
The combination of Zheng, Gray, Akin, Liu, and Cox teaches every limitation of the amended claims, and the combination would have yielded predictable results. Accordingly, the rejections of claims 1-20 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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