Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed 12/22/2026. Claims 1, 13, 20 have been amended. Claims 1-20 are pending and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 6, 8-15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US 2019/0172998 A1) in view of Baek et al. (US 2008/0180989 A1) and further in view of Nakanishi et al. (US 2022/0302208 A1).
Claim 1. Tan discloses a semiconductor structure, a semiconductor (P 0077), comprising:
a magnetic layer, a magnetic layer (P 0005), located between a first electrode and a second electrode, a magnetic layer disposed between the first electrode and the second electrode (P 0006, 0142), formed on a substrate, on a substrate (P 0100);
a first write element electrically coupled to the magnetic layer adjacent to the first electrode, a first terminal is connected to a magnetic layer to magnetize the magnetic layer (P 0142) to write a bit (P 0144);
a second write element electrically coupled to the magnetic layer adjacent to the second electrode, a second terminal is connected to a magnetic layer to magnetize the magnetic layer (P 0142) to write a bit (P 0144); and
a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element, in a racetrack memory device in which bit values are read according to the presence or absence of the skyrmions (magnetic quasiparticles formed by individual electron spins, which may be generated and transported using an electric current) along the racetrack that form a series of bit values (P 0156).
Tan does not disclose a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element, each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements, as disclosed in the claims. However, in the same field of invention, Baek discloses a magnetic memory device is comprised of a plurality of magnetic memory cells connected to at least one bit line and the memory cells are also connected to a digit line are parallel and orthogonal to the bit lines (P 0038) wherein a current is passed through the digit line to apply a magnetic field to the memory elements to write data to the magnetic memory cells (P 0041). Furthermore, in the same field of invention, Nakanishi discloses an (MTJ) element is connected to the memory unit through a magnetic layer and functions as a read element for reading data in the memory unit of the storage device (P 0044 Fig 4). Therefore, considering the teachings of Tan, Baek and Nakanishi, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element, each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements with the teachings of Tan with the motivation to provide a more efficient so as to reduce loss of write margin in a memory cell (Baek: P 0003-0004) and provide with increased memory capacity (Nakanishi: P 0003).
Claim 2. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein the first write element and the second write element are configured to receive respective current pulses from the first electrode and the second electrode to polarize magnetic material corresponding to the plurality of storage elements formed by the magnetic layer, each of the terminals magnetize the magnetic layer (P 0142) when an electric current is applied along the racetrack (P 0156) wherein the current can be periodic (P 0160). Furthermore, Tan discloses an array of two-terminal MRAM devices may be assembled to form a memory device where the first electrode and the second electrode of multiple two-terminal magnetic random-access memory MRAM devices are connected to one or more word lines and one or more bit lines, respectively to form an array of memory cells that can each be individually read and written (P 0148).
Claim 3. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 2, and Tan discloses wherein each of the plurality of read elements is configured to read a respective output current from a respective one of the plurality of storage elements representative of a corresponding data state, each MRAM device forms a memory device with cells that can each be individually read and written (P 0148) by a device coupled to the racetrack (P 0156).
Claim 6. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements formed by the magnetic layer, the MRAM forms an array of memory cells that can each be individually read and written (P 0148).
Claim 8. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein the semiconductor structure is used in a neuromorphic computing task, the magnetic memory device can be used for neuromorphic computing (P 0161).
Claim 9. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein the magnetic layer, the first write element, the second write element, and the plurality of read elements form a respective one of a plurality of memory cells storing a given one of a plurality of states, the MRAM may store a given magnetic state (P 0146) and forms an array of memory cells that can each be individually read and written (P 0148) that each have a binary bit value of 1 or 0 (P 0160).
Claim 10. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 9, and Tan discloses wherein each of the plurality of states is independent of other ones of the plurality of states, the MRAM may store a given magnetic state (P 0146) and forms an array of memory cells that can each be individually read and written (P 0148) that each have a binary bit value of 1 or 0 (P 0160).
Claim 11. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein any of the plurality of read elements is selectively activatable to read one or more bits of data, the MRAM forms an array of memory cells that can each be individually read and written (P 0148).
Claim 12. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, and Tan discloses wherein each of portions of the magnetic layer is aligned on a single plane, the memory device consists of a magnetic layer plane (P 0090) the etched region of the magneto-ionic device may then be infilled with an electrical conductor (e.g., the same materials as the first electrode) such that the first electrode and the second electrode are accessible across the same plane (P 0102).
Claim(s) 13, 14, 15, 18 is/are directed to method claim(s) similar to the semiconductor structure claim(s) of Claim(s) 1, 2, 3, 6 and is/are rejected with the same rationale.
Claim 20. Tan discloses a semiconductor structure, comprising:
an array of racetrack memories, a racetrack memory device (P 0156),
each of the racetrack memories including: a magnetic layer, a magnetic layer (P 0005), located between a first electrode and a second electrode, a magnetic layer disposed between the first electrode and the second electrode (P 0006, 0142), on a substrate, on a substrate (P 0100);
a first write element electrically coupled to the magnetic layer adjacent to the first electrode, a first terminal is connected to a magnetic layer to magnetize the magnetic layer (P 0142) to write a bit (P 0144);
a second write element electrically coupled to the magnetic layer adjacent to the second electrode, a second terminal is connected to a magnetic layer to magnetize the magnetic layer (P 0142) to write a bit (P 0144); and
a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element, in a racetrack memory device in which bit values are read according to the presence or absence of the skyrmions (magnetic quasiparticles formed by individual electron spins, which may be generated and transported using an electric current) along the racetrack that form a series of bit values (P 0156).
Tan does not disclose a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements, as disclosed in the claims. However, in the same field of invention, Baek discloses a magnetic memory device is comprised of a plurality of magnetic memory cells connected to at least one bit line and the memory cells are also connected to a digit line are parallel and orthogonal to the bit lines (P 0038) to store bits in each memory cell (P 0040) wherein a current is passed through the digit line to apply a magnetic field to the memory elements to write data to the magnetic memory cells (P 0041). Furthermore, in the same field of invention, Nakanishi discloses an (MTJ) element is connected to the memory unit through a magnetic layer and functions as a read element for reading data in the memory unit of the storage device (P 0044 Fig 4). Therefore, considering the teachings of Tan, Baek and Nakanishi, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements with the teachings of Tan with the motivation to provide a more efficient so as to reduce loss of write margin in a memory cell (Baek: P 0003-0004) and provide with increased memory capacity (Nakanishi: P 0003).
Claim(s) 4-5, 7, 16-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US 2019/0172998 A1) in view of Baek et al. (US 2008/0180989 A1) and Nakanishi et al. (US 2022/0302208 A1) and further in view of Aiba et al. (US 2021/0294527 A1).
Claim 4. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, but Tan does not disclose wherein the first write element and the second write element are configured to receive respective current pulses from the first electrode and the second electrode to move a domain wall separating magnetic domains in magnetic material forming the magnetic layer in any of two opposing directions, as disclosed in the claims. However, Tan the propagation of spin textures, i.e. magnetic domains and magnetic waves may be manipulated (P 0156) representing domain walls (P 0157) the propagation of magnetic waves, such as magnons, may also be controlled, in part, by spatially varying the magnetic anisotropy, magnetic damping, and exchange interactions like DMI along a waveguide (P 0158). While paragraphs 0156-0158 appear to disclose that a domain wall may be propagated by any terminal in a respective direction, Tan does not explicitly disclose move a domain wall separating magnetic domains in magnetic material. In the same field of invention, Aiba discloses a magnetic domain wall may be moved (P 0098). Therefore, considering the teachings of Tan, Baek, Nakanishi and Aiba, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the first write element and the second write element are configured to receive respective current pulses from the first electrode and the second electrode to move a domain wall separating magnetic domains in magnetic material forming the magnetic layer in any of two opposing directions with the teachings of Tan, Baek and Nakanishi with the motivation to support the performance of well-known memory operations to preserve data stored data (Aiba P 0003-0005) and the Supreme Court in KSR International Co. v. Teleflex Inc. identified applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as a rationale to support a conclusion of obviousness which is consistent with the proper “functional approach” to the determination of obviousness as laid down in Graham.
Claim 5. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, but Tan does not disclose wherein the plurality of read elements are configured to perform parallel reading operations, as disclosed in the claims. However, in the same field of invention, Aiba discloses data can be read in parallel from a magnetic domain wall shift memory (P 0306). Therefore, considering the teachings of Tan, Baek, Nakanishi and Aiba, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the plurality of read elements are configured to perform parallel reading operations with the teachings of Tan, Baek and Nakanishi with the motivation to support the performance of well-known memory operations to preserve data stored data (Aiba P 0003-0005) and the Supreme Court in KSR International Co. v. Teleflex Inc. identified applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as a rationale to support a conclusion of obviousness which is consistent with the proper “functional approach” to the determination of obviousness as laid down in Graham.
Claim 7. Tan, Baek and Nakanishi disclose the semiconductor structure of claim 1, but Tan does not disclose wherein current pulses input to the first electrode and the second electrode cause an incremental control of an output signal to be a sequence of ascending or descending values, as disclosed in the claims. However, in the same field of invention, Aiba discloses a memory controller input to an magnetic storage line (MML) is incremented increase the value and repeats the process (P 0210). Therefore, considering the teachings of Tan, Baek, Nakanishi and Aiba, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein current pulses input to the first electrode and the second electrode cause an incremental control of an output signal to be a sequence of ascending or descending values with the teachings of Tan, Baek and Nakanishi with the motivation to support the performance of well-known memory operations to preserve data stored data (Aiba P 0003-0005) and the Supreme Court in KSR International Co. v. Teleflex Inc. identified applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as a rationale to support a conclusion of obviousness which is consistent with the proper “functional approach” to the determination of obviousness as laid down in Graham.
Claim(s) 16, 17, 19 is/are directed to method claim(s) similar to the semiconductor structure claim(s) of Claim(s) 4, 5, 7 and is/are rejected with the same rationale.
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks Made in an Amendment, filed 12/22/2025, with respect to 35 USC § 112 of Claims 1, 13 and 20 have been fully considered and are persuasive. The amendments to the claims overcome the rejection, therefore the rejection of Claims 1, 13 and 20 has been withdrawn.
Applicant’s arguments with respect to claim(s) 1, 13 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant states:
Notwithstanding the deficiencies of Tan and Back, Applicant amends present claim 1 to further prosecution. Present claim 1 is amended to recite, inter alia, "a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element, each of the plurality of read elements is electrically coupled to a respective one of a plurality of storage elements" (emphasis added). Support for this amendment can be found at least in 1 [0044] of the present specification. No new matter has been added.
The examiner has combined new prior art reference Nakanishi with Tan to reject the amended claims. Baek discloses a magnetic memory device is comprised of a plurality of magnetic memory cells connected to at least one bit line and the memory cells are also connected to a digit line are parallel and orthogonal to the bit lines (P 0038) wherein a current is passed through the digit line to apply a magnetic field to the memory elements to write data to the magnetic memory cells (P 0041). Furthermore, in the same field of invention, Nakanishi discloses an (MTJ) element is connected to the memory unit through a magnetic layer and functions as a read element for reading data in the memory unit of the storage device (P 0044 Fig 4)
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
The applicant argues:
During the interview, Examiner reviewed "Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade" to Bläsing et al ("hereinafter Bläsing"). Upon review, Examiner indicated that Applicant's position was correct and that "the write operation and the read operation [can] be performed by the same terminals" (like Tan, Baek, and Aiba do). In other words, it is possible to have the same element perform read and write functions, and since Tan does not disclose a write element/read element, one of ordinary skill in the art would know that Tan's terminals perform both functions, unlike present claim 1 which has electrodes, write elements, and read elements that are all separate elements. Therefore, Tan does not teach or suggest at least "a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element." Accordingly, Applicant respectfully requests reconsideration and withdrawal of the present rejection.
The examiner respectfully disagrees. Per the interview summary record, the examiner acknowledged the reference provided by the applicant. While Bläsing may describe a mechanism that may both read and write bits to a magnet memory, Tan does not disclose this mechanism. Therefore, the examiner cannot apply this functionality to Tan. Furthermore, limitations directed to the claimed read elements have been amended to clarify the configuration and function of the read elements.
The applicant argues:
Baek fails to cure the deficiencies of Tan. Back, like Tan, teaches applying "an electrical signal to each memory cell Mc to discriminate between the at least four different memory states and to thereby read the at least two bits of data from the memory cell Me" (Baek 1 [0045]). In other words, Baek fails to teach or suggest "a plurality of read elements electrically coupled to the magnetic layer" for the same reason Tan fails to teach or suggest at least "a plurality of read elements electrically coupled to the magnetic layer." Accordingly, Applicant respectfully requests reconsideration and withdrawal of the present rejection.
The examiner respectfully disagrees. In Figure 1A and Paragraph 0041, Baek discloses that one or both of the magnetic fields may be used to write a bit to one of the memory elements. Furthermore, Baek discloses that the memory cells Mc may be separately addressed by controller during read operations (P 0038) by applying a read current through a memory cell to determine a resistance characteristic of the memory cell (P 0045). This read current is clearly a different mechanism from applying a magnetic field to write the bit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to JOHN M HEFFINGTON at telephone number (571)270-1696.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M HEFFINGTON whose telephone number is (571)270-1696. The examiner can normally be reached on Monday through Friday from 9:30 am to 5:30 pm Eastern.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cesar B Paula, can be reached at telephone number 571-272-4128. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.H/Examiner, Art Unit 2145
5/4/2026
/CESAR B PAULA/Supervisory Patent Examiner, Art Unit 2145
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