DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 6-11, 14-16, 18, and 20-26 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-3, 6-8, and 22-23 recite a method and, therefore, is a process. Claims 18, 20-21, and 26 recites a non-transitory program storage device and, therefore, is an article of manufacture. Claims 9-11, 14-16, and 24-25 recites a device and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites
A method for resizing data, comprising:
receiving input data values for resizing;
generating, by the processing circuitry, a first vector in which a first number of data values from a first line of data values of the input data values is placed in a first portion of a first vector, and the first number of data values from a second line of data values of the input values is placed in a second portion of the first vector;
generating, by the processing circuitry, a second vector in which the first number of data values from the first line of data values of the input values is placed in a first portion of the second vector, and the first number of data values from the second line of data values of the input data values is placed in a second portion of the second vector;
receiving, by the processing circuitry, a first matrix of weights, wherein each weight of the first matrix of weights corresponds to an amount of weight to apply to a data value for a point on a first line of a set of resized data;
receiving, by the processing circuitry, a second matrix of weights, wherein each weight of the second matrix of weights corresponds to an amount of weight to apply to a data value for a point on the second line of the set of resized data;
multiplying, by the processing circuitry, the first vector and the first matrix of weights to determine data values for the first line of the set of resized data;
multiplying, by the processing circuitry, the second vector and the second matrix of weights to determine data values for the second line of the set of resized data and outputting the set of resized data;
wherein generating the first and second vectors includes generating a third vector that includes a second number of data values from the first line of data values of the input data values, and generating a fourth vector that includes the second number of data values from the second line of data values of the input data values, the second number being twice the first number, and each of the third and fourth vectors including first and second portions;
performing a shift and copy operation on the third vector to generate a fifth vector in which data values in the first portion of the third vector are copied to a first portion of the fifth vector, a last data value in the first portion of the third vector and all data values except one in the second portion of the third vector are copied to a second portion of the fifth vector; performing a shift and copy operation on the fourth vector to generate a sixth vector in which data values in the first portion of the fourth vector are copied to a first portion of the sixth vector, a last data value in the first portion of the fourth vector and all data values except one in the second portion of the fourth vector are copied to a second portion of the sixth vector; and swapping the data values in the second portion of the fifth vector with the data values in the first portion of the sixth vector to generate the first vector and the second vector.
The above underlined limitations are related to calculating, processing and organizing data by permuting data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “A processing circuitry”, “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights”. However, the additional element of “a processing circuitry” is recited at a high-level of generality (i.e., as a generic computer component for organizing and multiplying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 1 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a processing circuitry” is recited at a high-level of generality (i.e., as a generic computer component for organizing and multiplying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 2-3, 6-8, and 22-23 recite further steps and details to calculating, processing and organizing data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas.
Regarding claim 2, it is directed to a use of a matrix multiplier accelerator to do the matrix multiplication. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 2 recites the following additional element: “a matrix multiplier accelerator”. However, the additional element of “a matrix multiplier accelerator” is recited at a high-level of generality (i.e., as a generic computer component for matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 2 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a matrix multiplier accelerator” is recited at a high-level of generality (i.e., as a generic computer component for matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims does not amount to significantly more than the abstract idea.
Regarding claims 3, 6-8, and 22-23 they are directed to limitations that deals with the natural mathematical nature of vectors, permuting data and formulating the structure for the matrix multiplication operations. In particular claims 3, 6-8, and 22-23 do not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 9 recites
An electronic device, comprising:
one or more memories: and
matrix multiplier accelerator circuitry operably coupled to the one or more memories, the matrix multiplier accelerator circuitry configured to:
receive, from a memory of the one or more memories, input data values for resizing;
generate a first vector in which a first number of data values from a first line of data values of the input data values is placed in a first portion of the first vector, and the first number of data values from a second line of data values of the input data values is placed in a second portion of the first vector;
generate a second vector in which the first number of data values from the first line of data values of the input data values is placed in a first portion of the second vector, and the first number of data values from the second line of data values of the input data values is placed in a second portion of the second vector;
receive a first matrix of weights, wherein each weight of the first matrix of weights corresponds to an amount of weight to apply to a data value for a point on a first line of a set of resized data;
receive a second matrix of weights, wherein each weight of the second matrix of weights corresponds to an amount of weight to apply to a data value for a point on the second line of the set of resized data;
multiply the first vector and the first matrix of weights to determine data values for the first line of the set of resized data;
multiply the second vector and the second matrix of weights to determine values for the second line of the set of resized data and output the set of resized data.
wherein generating the first and second vectors includes generating a third vector that includes a second number of data values from the first line of data values of the input data values, and generating a fourth vector that includes the second number of data values from the second line of data values of the input data values, the second number being twice the first number, and each of the third and fourth vectors including first and second portions;
performing a shift and copy operation on the third vector to generate a fifth vector in which data values in the first portion of the third vector are copied to a first portion of the fifth vector, a last data value in the first portion of the third vector and all data values except one in the second portion of the third vector are copied to a second portion of the fifth vector; performing a shift and copy operation on the fourth vector to generate a sixth vector in which data values in the first portion of the fourth vector are copied to a first portion of the sixth vector, a last data value in the first portion of the fourth vector and all data values except one in the second portion of the fourth vector are copied to a second portion of the sixth vector; and swapping the data values in the second portion of the fifth vector with the data values in the first portion of the sixth vector to generate the first vector and the second vector.
The above underlined limitations are related to calculating, processing and organizing data by permuting data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 9 recites the following additional elements: “a matrix multiplier accelerator circuitry”, “one or more memories”, “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights”. However, the additional elements of “a matrix multiplier accelerator circuitry” and “one or more memories” are recited at a high-level of generality (i.e., as a generic computer component for organizing and multiplying data; and as a generic computer component for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 9 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “a matrix multiplier accelerator circuitry” and “one or more memories” are recited at a high-level of generality (i.e., as a generic computer component for organizing and multiplying data; and as a generic computer component for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing”, “receiving a first matrix of weights”, and “receiving a second matrix of weights” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 10-11, 14-16, and 24-25 recite further steps and details to calculating, processing and organizing data by permuting data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas. Accordingly, the claims recites an abstract idea.
Regarding claim 10, it is directed to a chip that compute the matrix multiplication operation using the generic components as disclosed above. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 10 recites the following additional element: “a chip”. However, the additional element of “a ship” is recited at a high-level of generality (i.e., as a generic computer component for comprising of other generic computer components to compute matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 10 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a chip”. However, the additional element of “a ship” is recited at a high-level of generality (i.e., as a generic computer component for comprising of other generic computer components to compute matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims does not amount to significantly more than the abstract idea.
Regarding claims 11, 14-16, and 24-25, they are directed to limitations that deals with the natural mathematical nature of vectors, and formulating the structure for the matrix multiplication operations. In particular claims 11, 14-16, and 24-25 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 21 recites
A non-transitory program storage device comprising instructions stored thereon to cause matrix multiplier accelerator circuitry to:
receive input data values for resizing;
place a first number of data values from a first line of data values of the input data values in a first vector;
place the first number of data values from a second line of data values of the input data values in a second vector;
perform a shift and copy operation on the first vector to generate a third vector in which data values of a first portion of the first vector are copied to a first portion of a third vector, a last value of the first portion of the first vector is copied to a leading position of a second portion of the third vector, and a subset of the data values of a second portion of the first vector is copied to the second portion of the third vector;
perform a shift and copy operation on the second vector to generate a fourth vector in which data values of a first portion of the second vector are copied to a first portion of a fourth vector, a last value of the first portion of the second vector is copied to a leading position of a second portion of the fourth vector, and a subset of the data values of a second portion of the second vector is copied to the second portion of the fourth vector;
swap the data values in the second portion of the third vector with the data values in the first portion of the fourth vector, to generate fifth and sixth vectors;
multiply a first matrix of weights, wherein each weight of the first matrix of weights corresponds to an amount of weight to apply to a data value for a point on a first line of a set of resized data; and
multiply a second matrix of weights, wherein each weight of the second matrix of weights corresponds to an amount of weight to apply to a data value for a point on a second line of the set of resized data; and
output the set of resized data.
The above underlined limitations are related to calculating, processing and organizing data by permuting data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 21 recites the following additional elements: “A non-transitory program storage device comprising instructions stored thereon”, “a matrix multiplier accelerator circuitry”, and “receiving input data values for resizing”. However, the additional elements of “A non-transitory program storage device comprising instructions stored thereon”, and “a matrix multiplier accelerator circuitry” are recited at a high-level of generality (i.e., as a generic computer component for storing instructions; and as a generic computer component for organizing and multiplying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 21 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “A non-transitory program storage device comprising instructions stored thereon”, and “a matrix multiplier accelerator circuitry” are recited at a high-level of generality (i.e., as a generic computer component for storing instructions; and as a generic computer component for organizing and multiplying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving input data values for resizing” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 18, 20, and 26 recite further steps and details to calculating, processing and organizing data by permuting data for matrix multiplication operations which amount to mathematical relationships/calculations and organizing data which falls within the “mathematical concepts” (see paragraphs [20,31-37,42,45,46,49-52,54]) and/or “mental processes” grouping of abstract ideas. Accordingly, the claims recites an abstract idea.
Regarding Claim 18, it is directed to a chip that compute the matrix multiplication operation using the generic components as disclosed above. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 18 recites the following additional element: “a chip”. However, the additional element of “a chip” is recited at a high-level of generality (i.e., as a generic computer component for comprising of other generic computer components to compute matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 18 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a chip” is recited at a high-level of generality (i.e., as a generic computer component for comprising of other generic computer components to compute matrix multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims does not amount to significantly more than the abstract idea.
Regarding Claims 20 and 26, it is directed to formulating the structure for the matrix multiplication operations. In particular claims 20 and 26 do not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Response to Amendment
Examiner notes that on page 10 of applicant’s arguments, the applicant amends the independent claim 1 (and 9) to include subject matter from allowable claim 5 and intervening claim 4. While it may appear that the applicant rewrote claim 1 to be equivalent to cancelled claim 5, it is different as the reasons for indicating allowable subject matter was based on replacing the same data into two different portions of two different vectors, the claim as amended now uses “swapping” instead for the two different vectors. See newly amended Claim 1 and the Office Action mailed 02/24/2026 (hereinafter Prior Office Action), page 41-42, and allowable subject matter below.
Allowable Subject Matter
The following is a statement of reasons for the indication of withdrawal of allowable subject matter of the Prior Office Action:
Prior Office Action notes that the claims that was indicated as allowable had a two “replace” operations that resulted in discarding of relevant information.
The claims as amended now consist of a “swap” operation, which differs from the reasons of indicating allowable subject matter in the Prior Office Action.
The claims would be allowable, once all related rejections and objections are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Redfern et al. (US 2018/0253402 A1) discloses memories, processing circuitry and matrix multiplication accelerators, manipulating the vector data based on the need of the device, having 2 vectors and 2 matrices for matrix multiplication, see par.4, 22, 31, and 53 and figure 1, however the reference does not disclose the vectors having two portions and generating the vectors using both shift and copy operations and swapping as disclosed by the claims.
Li et al. (NPL: “Reducing DRAM Image Data Access Energy Consumption in Video Processing”) discloses linearly and blocked mapped DRAM and its benefits, see page 305, however the reference does not disclose the multiplying 2 matrices with the 2 vectors generated using both shift and copy operations and swapping as disclosed by the claims.
Garg et al. (NPL: “A Low-Cost Energy Efficient Image Scaling Processor for Multimedia Applications”) discloses vectors of two portions using 2 lines of data to interpolate data, See figure 7, however the reference does not disclose the multiplying 2 matrices with the 2 vectors generated using both shift and copy operations and swapping as disclosed by the claims.
Hong et al. (US RE47,341 E) discloses the ability to interpolate using matrix data and vector, see figure 2, and col.4-5, however the reference does not disclose the multiplying 2 matrices with the 2 vectors generated using both shift and copy operations and swapping as disclosed by the claims.
Aho et al. (NPL: “Block-Level Parallel Processing for Scaling Evenly Divisible Images”) discloses block boundaries and respective benefits, and overlapping/boundary handling, see pages 2718-2719 and figures 2-4, however the reference does not disclose the multiplying 2 matrices with the 2 vectors generated using both shift and copy operations and swapping as disclosed by the claims.
Getreuer (NPL: “Linear Methods for Image Interpolation”) discloses and various extension methods for boundary handling, see section 14, however the reference does not disclose the multiplying 2 matrices with the 2 vectors generated using both shift and copy operations and swapping as disclosed by the claims.
Eichenberger et al. (US 9,575,753 B2) discloses the ability to permute data of vectors based on permutation vector/data, see figure 6 and Col. 8, ll.55-64 and Col.14, ll.40-56.
Joshi et al. (US 2011/06317764 A1) discloses the benefits of using symmetries in filter coefficients and interpolation filters, see paragraph 66.
The prior art of record does not teach or suggest a combination as claimed including: “wherein generating the first and second vector includes generating a third vector… a fourth vector… including first and second portions… performing a shift and copy operation… generate a fifth vector… generate a sixth vector… swapping the data values in the second portion of the fifth vector with the data values in the first portion of the sixth vector to generate the first vector and the second vector”.
Response to Arguments
Applicant’s arguments, see page 9, filed 06/24/2026, with respect to Objections to the Drawings have been fully considered and are persuasive. The Objections to the Drawings of the Office Action mailed 02/24/2026 has been withdrawn.
Applicant's arguments, see pages 10-11, filed 06/24/2026, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
On page 9, on the last paragraph, applicant argues that the claims are not directed to 3 of the 4 statutory categories (wherein the claims are clearly not a composition of matter i.e. the last statutory category not mentioned). This argument seems to be misplaced, if the claims are not directed to the statutory categories, then there would be an alternate basis for a rejection under 101 as the claims are not directed to one of the statutory categories.
On pages 9-10, on the last paragraph, applicant argues that there is a benefit of sharing cache memories with processors and ML accelerators. MPEP 2106.05(a) explains:
After the examiner has consulted the specification and determined that the disclosed invention improves technology, the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology. Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1316, 120 USPQ2d 1353, 1359 (Fed. Cir. 2016) (patent owner argued that the claimed email filtering system improved technology by shrinking the protection gap and mooting the volume problem, but the court disagreed because the claims themselves did not have any limitations that addressed these issues). That is, the claim must include the components or steps of the invention that provide the improvement described in the specification. (emphasis added)
The claims do not recite a cache. The claims do not recite a cache, processor, and accelerator on the same chip. Since the claims do not recite the components that provide the alleged improvements, Applicant’s argument is not persuasive.
Applicant’s remarks regarding the rejection of the claims under 35 U.S.C. 103 do not comply with 1.111(b) as the applicant does not explain why the amendment including newly claimed subject matter are patentable over the recited references.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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