DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 10-11, 16-17 and 18--22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saloio, Jr. et al. (US 9673611).
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With respect to claim 1, figure 1 of Saloio discloses a circuit comprising: a semiconductor device (14) having first (at 28) and second (input at 18) terminals and a command input (at 24), the semiconductor device configurable to enable an electrical connection between the first and second terminals responsive to a control signal at the command input (24) having a first state (on), and disable the electrical connection responsive to the control signal having a second state (off); a sensor circuit (18) having a sensor output (at 32) and configurable to provide a sensor signal at the sensor output representing a sensed quantity (quantity across the resistor 18) of at least one of: a voltage across the first and second terminals (the voltage across and current through 18 would represent a quantity output across the terminals of 14), a current through a diode across the first and second terminals , or a temperature of the semiconductor device during conduction of the current across the first and second terminals by the diode ( a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) inherently has an equivalent diode or intrinsic body diode. This diode is formed as a consequence of the MOSFET's structure, specifically the p-n junction between the body (substrate) and the drain/source regions. ), while the electrical connection is disabled (if the electrical connection is disabled the resistor still represents the disabled quantity furthermore only one need be present as the claim states at least one of in the alternative); and a control circuit (12 and 38) having a control input (at 32 or 30) and a control output (output at 26 or 24), the control input couple to the sensor output (at 32), the control output coupled to the command input, and the control circuit configurable to, responsive to the sensed quantity exceeding a threshold, provide the control signal having the first state at the control output (see Col. 3 lines 21-33: . A test of the functionality of the over-current fault detection circuitry comprises enabling high-side switch 14 for a time greater than T.sub.over-current when capacitor 20 is not yet charged. A successful test occurs if microcontroller 12 indicates an over-current fault during this time period. Following a successful test, high-side switch 14 may be enabled indefinitely, as described below, for normal system operation. If a fault is not detected, system 10 may disable, and then re-enable high switch 14 again for a time greater than T.sub.over-current. This process may be repeated a predetermined number of times. If an over-current fault has not been indicated after the process has been repeated the predetermined number of times, then the test has failed and proper action can be taken, such as alerting a technician so that the circuit may be repaired or replaced.”) to enable the electrical connection between the first and second terminals (the electrical connection is dependent on the state across the first and second terminals and enables based on that state).
With respect to claim 8, the circuit above discloses circuit of claim 1, wherein the circuit is implemented in an integrated circuit including a substrate, and the semiconductor device and the sensor circuit are implemented in the substrate (This is deemed intended use of the device however, the circuit may be implemented in and integrated circuit and is within the scope of the invention).
With respect to claim 10, the circuit above discloses the circuit of claim 1, wherein the control circuit is configurable to provide the control signal as a pulse signal (High-side switch 14 may be pulsed a predetermined number of times such that it is guaranteed that capacitor 20 will be fully charged ) the control input is a first control input (at 32+).
With respect to claim 11, the circuit above discloses a circuit comprising: a semiconductor device having first and second terminals and a command input (at 24), the semiconductor device configurable to enable an electrical connection between the first and second terminals responsive to a driver signal (from 12) at the command input (at 24) having a first state (conducting or high), and disable the electrical connection responsive to the driver signal having a second state (non-conducting or low), a sensor circuit (18 and 38) having a sensor output, the sensor circuit configurable to provide a sensor signal (from 18) indicating whether a diode ( a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) inherently has an equivalent diode or intrinsic body diode. This diode is formed as a consequence of the MOSFET's structure, specifically the p-n junction between the body (substrate) and the drain/source regions. ) across the first and second terminals is in an avalanche condition; (considered over current fault) and a driver circuit (20) having a driver control input and driver output, the driver control input coupled to the sensor output, and the driver circuit configurable to, responsive to the sensor signal indicating that the diode is in the avalanche condition (considered over current fault), provide the driver signal having the first state (charge state) at the driver output.
With respect to claim 16, the circuit above produces the circuit of claim 11, wherein the circuit is implemented in an integrated circuit including a substrate, and the semiconductor device and the sensor circuit are implemented on the substrate of the integrated circuit. (This is deemed intended use of the device however, the circuit may be implemented in and integrated circuit and is within the scope of the invention).
With respect to claim 17, the circuit above produces the circuit of claim 11, wherein the sensor circuit includes a voltage sensor (the voltage across and current through 18 would represent a quantity output across the terminals of 14), coupled between the first (at 28) and second terminals (downstream terminal of 18), the voltage sensor having an output coupled to the sensor output and configurable to provide the sensor signal representing whether a voltage between the first and second terminals exceeds a voltage threshold (threshold would be the output voltage coming from 18).
With respect to claim 18, the circuit above discloses the circuit of claim 11, wherein the driver circuit (20) is configurable to provide the driver signal.
With respect to claim 19, the circuit above discloses a system comprising: an integrated circuit (IC) including: a semiconductor device having first (at 28) and second terminals (input at 18) and a command input (at 24), the semiconductor device configured to enable an electrical connection between the first and second terminals responsive and a control signal (12) at the command input (12 produces 24) having a first state (on), and disable the electrical connection responsive to the control signal having a second state (off), a sensor circuit (18) having a sensor output (at + and - of 32) and configured to provide a sensor signal at the sensor output representing whether the semiconductor device is in an overstress condition while the electrical connection is disabled (when disabled the resistors output discloses whether or not it is in an overstress condition, generally when off no overstress condition exists) ; and a control circuit (12) having a control input (22) and a control output (at 24), the control input coupled to the sensor output (via 38), and the control circuit configurable to, responsive to the sensor signal indicating that the semiconductor device is in the overstress condition, provide the control signal having the first state to enable the electrical connection between the first and second terminals (the output of 18 would enable 14 to turn on in the event of an overstress condition).
With respect to claim 20 the circuit above discloses the system of claim 19, further comprising a test system comprising a voltage source (24) coupled between the first (18) and second terminals (28), the voltage source configurable to provide a test voltage between the first and second terminals to cause the overstress condition in the semiconductor device. (Here, because they are intentionally trying to stress out the transistors with the overcurrent condition, the alert based on the overstressed condition reads on the claim language.)
With respect to claim 21, the circuit above discloses the system of claim 20, wherein the overstress condition comprises at least one of: an overtemperature condition, an avalanche condition, or an overvoltage condition (here overvoltage condition).
With respect to claim 22, the circuit above discloses the circuit of claim 1, wherein the control circuit is configurable to detect an avalanche condition (overcurrent fault) in the semiconductor device responsive to the sensed quantity exceeding the threshold, and provide the control signal (24) having the second state responsive to the detection of the avalanche condition.
Claim(s) 1-2, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haeberlen et al. (US 9509284).
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With respect to claim 1, figure 10 of Haeberlen discloses a circuit comprising: a semiconductor device (fig 10) having first (21) and second (22) terminals and a command input (at 23 or 24), semiconductor device configurable to enable (via S.sub.LOAD) an electrical connection between the first and second terminals responsive to a control signal at the command input (23) having a first state (conducting/high), and disable the electrical connection responsive to the control signal having a second state (non-conducting / low); a sensor circuit (42) having a sensor output (at S.sub.LOAD) and configurable to provide a sensor signal at the sensor output representing a quantity of at least one of: a voltage across a diode ( a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) inherently has an equivalent diode or intrinsic body diode. This diode is formed as a consequence of the MOSFET's structure, specifically the p-n junction between the body (substrate) and the drain/source regions. ) across the first (21) and second (22) terminals, a current through a diode across the first and second terminals, or a temperature of the semiconductor device (see Col. 11 lines 11-17) during conduction of the current across the first and second terminals by the diode, while the electrical connection is disabled (note because the claim claims in the alternative either of the conditions can be met, furthermore the temperature sensor senses whether the circuit is on or off) ; and a control circuit (3) having a control input (at S.sub.LOAD) and a control output (output at 23 or 13), the control input coupled to the sensor output (at 42), the control output coupled to the command input, and the control circuit configurable to, responsive to the sensed quantity exceeding a threshold (based on SLoad), provide the control signal having the first state at the control output to enable the electrical connection between the first and second terminals (based on the temp sensor the drive circuit enables the electrical connection across the terminals).
With respect to claim 2, figure 10 of Haeberlen et al. 9509284 discloses the circuit of claim 1, wherein the sensor circuit Includes a thermal sensor circuit (42).
With respect to claim 11, the circuit above discloses a circuit comprising: a semiconductor device having first (21) and second terminals (22) and a command input (at 23), configurable to enable an electrical connection between the first and second terminals responsive to a driver signal (from 3) at the command input (at 23) having a first state (high to make 2 conductive), and disable the electrical connection responsive to the driver signal having a second state (low to make 2 non-conductive) a sensor circuit (42) having a sensor output, the sensor circuit configurable to provide a sensor signal indicating whether a diode across the first and second terminals is in an avalanche condition (above temperature threshold as indicated by SLoad) while the electrical connection is disabled (the sensor still senses while the connection is disabled); and a driver circuit (3) having a driver control input and driver output, the driver control input coupled to the sensor output, and the driver circuit configurable to, responsive to the sensor signal indicating that the diode is in the avalanche condition, provide the driver signal having the first state at the driver output to enable the electrical connection between the first and second terminals (based on the sensor the connection between the terminals is enabled).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-5, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haeberlen et al. (US 9509284) in view of Neidorff (US 9329615).
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With respect to claim 3 Haeberlen et al. discloses the circuit of claim 2 but fails to explicitly disclose the senor circuit, claim 2, wherein the thermal sensor circuit includes a proportional to absolute temperature (PTAT) current source configurable to provide the sensor signal responsive to the temperature, and the threshold represents a temperature threshold.
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Figure 3 of Neirdoff discloses the details of a temperature sensing circuit (PTAT; proportional to absolute temperature), wherein the thermal sensor circuit (100) includes a proportional to absolute temperature current source (104 IPTAT) configurable to provide the sensor signal responsive to the temperature, and the threshold represents a temperature threshold.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the circuit of Neirdoff in the sensor circuit of Haeberlan for the purpose of more completely disclosing the temperature sensing circuit and for the Neirdoff disclosed purpose of reducing temperature tolerance of the temperature sensitive circuit.
With respect to claim 4, the combination above would produce the circuit of claim 3, wherein the semiconductor device includes a first transistor (2 of Haeberlan) coupled between the first and second terminals, and the thermal sensor circuit includes: a second transistor (102) coupled between a voltage terminal and the sensor output (Output), the second transistor having a control terminal; a resistor (106) coupled between the voltage terminal and the control terminal; and a second current source (103) coupled between the sensor output and a ground terminal; and wherein the PTAT current source (104) is coupled between the control terminal and the ground terminal.
With respect to claim 5, the combination above discloses the circuit of claim 1, wherein the sensor circuit (42) includes a voltage sensor coupled between the first and second terminals, the voltage sensor having an output coupled to the sensor output and configurable to provide the sensor signal representing the voltage between the first and second terminals, and the threshold represents a voltage threshold.
With respect to claim 13, Haeberlen produces the circuit of claim 11 (see 102 above in view of Haeberlen), but fails to disclose wherein the sensor circuit includes a thermal sensor, the thermal sensor including a proportional to absolute temperature (PTAT) current source (104 IPTAT) configurable to provide the sensor signal representing whether a temperature of the semiconductor device exceeds a temperature threshold.
Figure 3 of Neirdoff discloses the details of a temperature sensing circuit (PTAT; proportional to absolute temperature), wherein the thermal sensor circuit (100) includes a proportional to absolute temperature current source (104 IPTAT) configurable to provide the sensor signal responsive to the temperature, and the threshold represents a temperature threshold.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the circuit of Neirdoff in the sensor circuit of Haeberlan for the purpose of more completely disclosing the temperature sensing circuit and for the Neirdoff disclosed purpose of reducing temperature tolerance of the temperature sensitive circuit.
The resulting combination would produce wherein the sensor circuit includes a thermal sensor, the thermal sensor including a proportional to absolute temperature (PTAT) current source (104 IPTAT) configurable to provide the sensor signal representing whether a temperature of the semiconductor device exceeds a temperature threshold.
With respect to claim 14, the combination (Haeberlan in view of Neirdoff) above produces the circuit of claim 13, wherein the semiconductor device includes a first transistor (2 of Haeberlan) coupled between the first and second terminals, and the thermal sensor (100) includes:a second transistor (102) coupled between a voltage terminal and the sensor output, the second transistor having a control terminal; a resistor (106) coupled between the voltage terminal and the control terminal; and a second current source (103) coupled between the sensor output and a ground terminal (coupled by virtue of the temperature sensor of Haeberlen being coupled between ground and the output) (alternatively it would be obvious to change NPN to a PNP amplifier which would cause the flipping of the current source 103 to be between ground and the output within the Nierdoff reference.); a third current source (1) coupled to the ground terminal; and a switch (3) coupled between the control terminal and the third current source, the switch having a switch control terminal coupled to the sensor output; and wherein the PTAT current source is coupled between the control terminal and the ground terminal (coupled by virtue of the temperature sensor of Haeberlen being coupled to the ground terminal) (alternatively it is obvious to change the current source and the resistor is obvious to a current sink and the resistor being a pull up resistor ).
With respect to claim 15, the combination above (Haeberlan in view of Neirdoff) produces the circuit of claim 13, wherein the temperature threshold is a first temperature threshold, and the sensor circuit (42) includes a thermal sensor circuit configurable to: provide the sensor signal having a first sensor signal state responsive to the temperature exceeding the first temperature threshold; and provide the sensor signal having a second sensor signal state responsive to the temperature being below a second temperature threshold different from the first temperature threshold (here, because of the circuit being trimmable, multiple thresholds would be present and would read on the claim as such).
Claim(s) 9, 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saloio, Jr. et al. (US 9673611). in view of Hamlyn (11726943).
With respect to claim 9, the circuit above discloses the circuit of claim 1, wherein the semiconductor device includes: a first field effect transistor (FET) (14) having a first gate, a first drain, and a first source, the first drain coupled to the first terminal, the first gate coupled to the command input,; and a second FET (16) having a second gate, a second source, and a second drain, the second source coupled to the first source, the second drain coupled to the second terminal, and the second gate coupled to the second source but fails to disclose the first FET having a body diode between the first source and the first drain, the body diode configurable to conduct a reverse current responsive to a voltage potential between the first drain and the first source exceeding a breakdown voltage of the first FET .
Hamlyn (3A-c and 4C) teaches connecting a body diode between the source and drain. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teaching of Hamlyn in the circuit of Saloio for the purpose of blocking leakage current.
With respect to claim 27, Saloio discloses the circuit of claim 11, wherein (14) having a first gate, a first drain, and a first source, the first drain coupled to the first terminal, the first gate coupled to the command input and a second FET (16) having a second gate, a second source, and a second drain, the second source coupled to the first source, the second drain coupled to the second terminal, and the second gate coupled to the second source but fails to disclose ,the FET having a body diode between the first source and the first drain, the body diode configurable to conduct a reverse current responsive to a voltage potential between the first drain and the first source exceeding a breakdown voltage of the first FET.
Hamlyn (3A-c and 4C) teaches connecting a body diode between the source and drain. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teaching of Hamlyn in the circuit of Saloio for the purpose of blocking leakage current.
With respect to claim 28, Saloio discloses the system of claim 19, wherein semiconductor device includes: a first field effect transistor (FET) (14) having a first gate, a first drain, and a first source, the first drain coupled to the first terminal, the first gate coupled to the command input,: and a second FET (16) having a second gate, a second source, and a second drain, the second source coupled to the first source, the second drain coupled to the second terminal, and the second gate coupled to the second source, but fails to disclose the FET having a body diode between the first source and the first drain, the body diode configurable to conduct a reverse current responsive to a voltage potential between the first drain and the first source exceeding a breakdown voltage of the first FET.
Hamlyn (3A-c and 4C) teaches connecting a body diode between the source and drain. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teaching of Hamlyn in the circuit of Saloio for the purpose of blocking leakage current.
Claim(s) 25 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saloio, Jr. et al. (US 9673611). in view of Mills et al. 9537581.
With respect to claim 25, Saloio discloses the circuit of claim 1 but fails to disclose, wherein the control circuit is coupled to the command input via an isolation barrier, and the control circuit includes an isolation driver configurable to provide the control signal via the isolation barrier.
Figure 1 of Mills teaches the use of an opto-isolation for a sensor to a driver having a different domain.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teaching of Mills in the circuit of Salio for the purpose of more efficient signaling.
With respect to claim 26, the combination above produces the circuit of claim 25, wherein the control signal includes an optical signal.
Response to Arguments
Applicant's arguments filed 9/22/2025 have been fully considered but they are not persuasive.
With respect to applicant’s argument that NEITHER Saloio or Haeberlen discloses at least the elements of claim 1, the Examiner disagrees.
Applicant argues over-current fault is detected through the voltage drop on a resistor, rather than a votlage across the switch while a switch is enabled to conduct current rather than being disabled, the examiner agrees, but the current also detects when no overcurrent fault is detected and is indicative of the situation when no overcurrent fault is detected. Secondly, the condition is in the alternative, wherein one of 3 conditions, the resistor does indeed detect the voltage across the first and second terminals at least even when the electrical connection is disabled and at least for this reason anticipated claim1.
With respect to Haberlen, similarly since the conditions of claim 1 are stated in the alternative at least the voltage across the terminals. Secondly, no specific value of threshold is disclosed thus any threshold can be selected. With respect to applicant’s argument HEMTs have no diode the examiner agrees (except HEMT may have diodes in certain situations) however because the language is argued in the alternative, claim 1 is still anticipated by Haeberlan.
Allowable Subject Matter
Claims 6-7, 23-24 and 29-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, the prior art fails to suggest or disclose the voltage sensor having an output coupled to the sensor output and configurable to provide the sensor signal representing the voltage between the first and second terminals, and the threshold represents a voltage threshold.
With respect to claim 23, the prior art fails to suggest or disclose the circuit of claim 9, wherein each of the sensor circuit and the control circuit includes a respective first power terminal and a respective second power terminal, and the circuit further comprises a third transistor coupled between the first terminal and the first power terminals of the sensor circuit and the control circuit, and the second power terminals of the sensor circuit and the control circuit are coupled to the second source.
With respect to claim 29, the prior art of record fails to suggest or disclose wherein the control circuit is configurable to provide the control signal as a multi-cycle pulsed signal, and set a duty cycle of the control signal based on the sensed quantity.
With respect to claim 30, the prior art of record fails to suggest or disclose wherein the control circuit is configurable to provide the control signal as a multi-cycle pulsed signal, and set a duty cycle of the control signal based on the sensed quantity.
With respect to claim 31, the prior art of record fails to suggest or disclose wherein the control circuit is configurable to provide the control signal as a multi-cycle pulsed signal, and set a duty cycle of the control signal based on the sensed quantity.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2836
Prosecution Insights