Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Claims 1-20 remain pending in the application.
Claims 1 and 11 have been amended.
The amendment filed 12/19/2025 is sufficient to overcome the 35 U.S.C. 101 rejections of claims 1-20. The previous rejections have been withdrawn.
The amendment filed 12/19/2025 is sufficient to overcome the 103 rejections under McConaghy in view of Shao, Pivovar, and Morency of claims 1-4, 6-8, 11-14, and 16-18, the 103 rejections of claims 5 and 15 over McConaghy in view of Shao, Pivovar, Morency, and further in view of Veldhoven, and the 103 rejections of claims 9-10 and 19-20 over McConaghy in view of Shao, Pivovar, Morency, and further in view of Gao. The previous rejections have been withdrawn.
Response to Arguments
Argument 1, regarding the 35 U.S.C. 101 rejections, applicant argues that the rejections should be withdrawn because the claims are directed towards using machine learning for circuit sizing, resulting in more efficient circuit sizing than a generic circuit simulator. Examiner agrees and the rejections have been withdrawn.
Argument 2, regarding the prior art rejections, applicant argues that none of the cited prior art teaches “finding a candidate size by using a plurality of neural network agents", "identifying, from all samples selected by all of the neural network agents, a given sample ...that... represents the candidate size", or "updating weights of each neural network agent ....based on, at least in part, a difference between the simulation measurement of the circuit simulator on the candidate size and the corresponding measurement estimate of the each neural network agent", as recited in amended claims 1 and 11.
Applicant’s arguments are not persuasive because applicant does not argue why the teachings of McConaghy do not read on the cited limitations. McConaghy teaches finding a candidate size of the analog circuit by using a plurality of neural network agents that learn by reinforcement learning, …wherein finding the candidate size further comprises: calculating, by each neural network agent…, a measurement estimate for each of a plurality of samples randomly generated in a trust region of a design space, wherein each sample represents a set of transistor sizes of the analog circuit (building blocks may be corresponding to transistor sizes, C10:L17-18, C12:L8-12. Building blocks are chosen based on calculated metric values and calculated by ensembles, a form of machine learning, C6:L42-49, C7:L26-31, C31:L53-55).
Applicant’s arguments are not persuasive because applicant does not argue why the teachings of Morency do not read on the cited limitations. Morency teaches identifying, from all samples selected by all of the neural network agents, a given sample having a given measurement estimate that minimizes the value metric among the all samples, wherein the given sample represents the candidate size (circuits with the most extreme values, the corner cases, that fail to meet the desired measurement specifications are identified and tested upon, C6:L21-32. These extreme values may include conditions in which the single most extreme values (global minimum or maximum) for any circuit measurement were found, C11:L27-29). Applicant argues that none of the cited art teaches “updating weights of each neural network agent ....based on, at least in part, a difference between the simulation measurement of the circuit simulator on the candidate size and the corresponding measurement estimate of the each neural network agent”. This argument is moot in view of Cao et al (Pub. No.: US 20180322234 A1), hereafter Cao. Cao teaches updating weights of each neural network agent ....based on, at least in part, a difference between the simulation measurement of the circuit simulator on the candidate size and the corresponding measurement estimate of the each neural network agent (In view of P0028 of the specification of the instant application, an example of the difference between the simulation requirement of the circuit simulator on the candidate size and the corresponding estimate of each neural network agent is a mean squared error (MSE). Weights are updated via error back propagation in accordance with leveraged probability for weight calculations in order to minimize the mean squared error (MSE) between outputs of predictive model 174 and predetermined values of a circuit simulator, P0031. Predictive model 174 may take the form of an artificial neural network. P0032).
The full rejections are outlined below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 11-14, and 16-18 are rejected under 35 U.S.C. 103 as being
unpatentable over McConaghy et al (Pub.No.: US 8443329 B2) hereafter McConaghy in view of Cao et al (Pub. No.: US 20180322234 A1), hereafter Cao, and further in view of Pivovar et al (Pub.No.: CN 115210822 A), hereafter Pivovar and Morency et al (Pub.No.: US 10896274 B1), hereafter Morency. (Pivovar relies on the priority date of January 17, 2020, the filing date of its US provisional application 62/962806).
Regarding claims 1 and 11, McConaghy teaches a method for sizing an analog circuit comprising: receiving an input indicating a specification of an analog circuit and a plurality of design parameters (Electrical circuiting component includes a target analog response and stored input parameters. C6:L13-21); finding a candidate size of the analog circuit by using a plurality of neural network agents that learn by reinforcement learning, …wherein finding the candidate size further comprises: calculating, by each neural network agent…, a measurement estimate for each of a plurality of samples randomly generated in a trust region of a design space, wherein each sample represents a set of transistor sizes of the analog circuit (building blocks may be corresponding to transistor sizes, C10:L17-18, C12:L8-12. Building blocks are chosen based on calculated metric values and calculated by ensembles, a form of machine learning, C6:L42-49, C7:L26-31, C31:L53-55); selecting, …, a sample having a corresponding measurement estimate that optimizes a value metric (“While the sized initial candidate topologies fail to meet a pre-determined criteria, in accordance with a search algorithm: (i) searching the candidate topologies for other candidate topologies; (ii) selecting parameters for the other candidate topologies to obtain sized other candidate topologies; (iii) calculating performance metric values for the sized other candidate topologies to obtain other calculated performance metric values; and (iv) in accordance with the other calculated performance metric values, determining if the sized other candidate topologies fail to meet the pre-determined criteria”, C37:L46-63. Candidate topologies map to design space, metric values map to measurement estimate, trust region is the candidate topologies where other candidate topologies are searched for. In step ii, selecting parameters within the candidate topologies includes selecting the optimal candidate size);… performing, by a circuit simulator, a circuit simulation on the candidate size to produce a simulation measurement (receiving simulation measurements in the form of performance values from a SPICE circuit simulator. Input for the spice circuit simulator includes devices connections, types, and parameters, which would include a candidate size. C16:L66-67, C17:L1-3)… and iterating the calculating, the selecting, the performing, and the updating until the simulation measurement indicates that a final candidate size satisfies the specification and the design parameters; and outputting the final candidate size as the circuit size of the analog circuit (steps of calculating, selecting, performing, and updating are done iteratively until a target relation value is reached for a sized candidate topology analog, C8:L16-67).
McConaghy does not appear to explicitly teach “updating weights of each neural network agent ....based on, at least in part, a difference between the simulation measurement of the circuit simulator on the candidate size and the corresponding measurement estimate of the each neural network agent”.
updating weights of each neural network agent ....based on, at least in part, a difference between the simulation measurement of the circuit simulator on the candidate size and the corresponding measurement estimate of the each neural network agent (In view of P0028 of the specification of the instant application, an example of the difference between the simulation requirement of the circuit simulator on the candidate size and the corresponding estimate of each neural network agent is a mean squared error (MSE). Weights are updated via error back propagation in accordance with leveraged probability for weight calculations in order to minimize the mean squared error (MSE) between outputs of predictive model 174 and predetermined values of a circuit simulator, P0031. Predictive model 174 may take the form of an artificial neural network. P0032).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy and Cao before them, to include Cao’s specific teachings of error back propagation being used to update weights of a neural network in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of error back propagation being used to update weights of a neural network (see Cao P0031-P0032) and using machine learning to design analog machine-learning ensembles (see McConaghy C31:L52-56).
McConaghy in view of Cao does not appear to teach “calculating updates to the trust region for the next iteration”.
Pivovar teaches calculating updates to the trust region for the next iteration (machine learning model 262 iteratively calculates updates to the trust region as it collects more information about the region with algorithm 104. Page 11, paragraph 3. Also taught in US provisional application at P0054).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, and Pivovar before them, to include Pivovar’s specific teachings of iteratively updating the trust region in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of iteratively updating the trust region (see Pivovar, page 11 paragraph 3, or its provisional application at P0054) and limiting or restricting a search space (trust region) in order to make it more trustworthy and easier to understand (see McConaghy C17:L10-14).
McConaghy in view of Cao does not appear to explicitly teach “with each neural network agent for a corresponding process, voltage, temperature (PVT) condition…for the corresponding PVT condition… identifying from samples selected by all of the neural network agents a candidate size that has a worst measurement estimate”.
Morency teaches with each neural network agent for a corresponding process, voltage, temperature (PVT) condition…for the corresponding PVT condition (“Therefore, it is common for IC designers, and for designers of analog and mixed signal IC's to perform circuit simulations in the presence of Process, Voltage and Temperature variations (hereafter PVT)”, C1:L48-51. Testing may be done with neural network processors, C27:L42-43)… identifying, from all samples selected by all of the neural network agents, a given sample having a given measurement estimate that minimizes the value metric among the all samples, wherein the given sample represents the candidate size (circuits with the most extreme values, the corner cases, that fail to meet the desired measurement specifications are identified and tested upon, C6:L21-32. These extreme values may include conditions in which the single most extreme values (global minimum or maximum) for any circuit measurement were found, C11:L27-29).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, Pivovar, and Morency before them, to include Morency’s specific teachings of using PVT as design parameters, identifying a circuit size that meets the PVT parameters specified, and progressively testing under the worst PVT conditions in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of testing under the worst PVT conditions (see Morency, C6:L27-34) and designing electrical circuits that can meet performance requirements, and deal with robustness issues such as environmental factors or manufacturing varations (see McConaghy C1:L35-44).
Regarding claims 2 and 12, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. McConaghy further teaches selecting an initial candidate size that optimizes simulation measurements (MOJITO algorithm uses data mining to, using samples in the design space (possible topologies and sizings), extract parameters, including a candidate size, used to optimize correlation between target waveform and current candidate circuit’s waveform. If sizings/topologies fail to meet the criteria set, searching algorithm continues to find appropriate sizing/topology. C31:L13-25, C34:L10-15) generated by the circuit simulator on initial samples in the design space (input data was derived from SPICE circuit simulator, C34:L37);
Pivovar further teaches initializing the trust region centered at the initial candidate size (trust region is initialized by the user-given parameters, including size. Page 4 paragraph 5, page 5 paragraph 4. Also taught in US provisional application at P0012, P0016); and initializing a neural network agent, which is trained with at least the initial candidate size and a corresponding simulation measurement (Neural network is trained with a plurality of data samples collected with use of a Monte Carlo simulator. Page 8, paragraph 3. Also taught in US provisional application at P0033).
Regarding claims 3 and 13, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. Pivovar further teaches wherein the trust region searched in a current iteration is centered at the candidate size identified in a previous iteration (The trust region in the current iteration depends on the previous iteration as it decreases in size each iteration based on data collected by algorithm 104, page 11, paragraph 3. Also taught in US provisional application at P0054).
Regarding claims 4 and 14, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. Morency teaches wherein the design parameters include a plurality of PVT conditions (“Therefore, it is common for IC designers, and for designers of analog and mixed signal IC's to perform circuit simulations in the presence of Process, Voltage and Temperature variations (hereafter PVT)”, C1:L48-51), the method further comprises: identifying the circuit size that satisfies the specification (“FIGS. 12-15 indicate, among other things, the extent to which various test cases for which the preliminary implementation of the preliminary circuit design satisfies a performance specification in the set of performance specifications”, C9:L19-23) under a worst one of the PVT conditions (Test designer focuses on worst ‘worst’ behaving cases/conditions and attempts to fix those first. C10:L44-51); testing, by the circuit simulator, the circuit size under all of the PVT conditions except the worse PVT condition (full set of PVT samples are tested after the worst conditions are tested until PVT conditions are met, C6:L21-37); and progressively exploring the PVT conditions that fail the testing until a final circuit size is found to satisfy the specification and all of the PVT conditions (“During the circuit refinement stage to improve yield, only the extreme cases corners (and their associated corner-specific subsets Monte Carlo iteration indices) are considered when simulating trial modified circuits, before reverting to the full set of PVT samples for a final verification. This greatly reduces the overall number of simulations required during the circuit refinement/yield improvement process”, C6:L27-34. Test designers progressively reach a final circuit design that performs well over PVT variations. C10:L34-43).
Regarding claims 6 and 16, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. McConaghy further teaches wherein the circuit size is a solution for a constraint satisfaction problem defined by a set of constraints (“For example, for ECDs, test benches specify the circuit analysis and test harness to measure performance; objectives and constraints specify the targets of each performance metric”, C10:L22-25) and a set of circuit variables (Set of optimal sized-circuits depends partially on topology and sizing variables, C11:L33-38), with each circuit variable corresponding to a set of predetermined sizing values (MOJITO algorithm searches for a solution to a multi-constraint problem, where the solution includes a set of optimal sized-circuits. C10:L61-67, C11:L1-5).
Regarding claims 7 and 17, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. Pivovar further teaches wherein updating the trust region further comprises: calculating a ratio to estimate an accuracy of a neural network agent in the trust region with respect to the simulation measurements in the trust region; and calculating a change to a radius of the trust region based on the ratio (Machine learning model calculates the relative importance of each design variable. Some design variables have a significant effect on the residual error, but other design variables have a small effect on the residual error. Using this data, the machine learning model determines accuracy of the data determined by the trust region and iteratively decrease the size of the trust region. Page 11, paragraph 3. Also taught in US provisional application at P0054).
Regarding claims 8 and 18, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. Pivovar further teaches wherein each of the neural network agents is a multi-layer neural network that learns by reinforcement learning (Machine learning model may be a multi-layer perceptron (basic feed-forward neural network). These models routinely use reinforcement learning. Page 22, paragraph 2. Also taught in US provisional application at P0094).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over McConaghy in view of Cao, Pivovar, Morency, and further in view of Veldhoven et al (Pub.No.: US 11101810 B1), hereafter Veldhoven and Le et al (Pub.No.: US 20210182466 A1), hereafter Le.
Regarding claims 5 and 15, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 4 and 14 as outlined above. Morency further teaches adding, to a condition pool, a next worst PVT condition among the PVT conditions that fail the testing, wherein the condition pool initially includes the worst PVT condition (“the designer may choose to re-simulate only those PVT conditions in which the single most extreme values (global minimum or maximum) for any circuit measurement were found”, C11:L26-29. When testing, designer may choose to group, or pool, together failed conditions to test those conditions further).
McConaghy does not appear to teach adding, to an agent pool, a next neural network agent for the next worst PVT condition, wherein the agent pool initially includes the neural network agent for the worst PVT condition; and iteratively searching, by the neural network agents in the agent pool, a common trust region for an updated circuit size that satisfies the specification under respective PVT conditions in the condition pool; and incrementing the agent pool and the condition pool for the iteratively searching until the final circuit size is found to satisfy the specification and all of the PVT conditions.
Veldhoven teaches adding, to an agent pool, a next neural network agent for the next worst PVT condition, wherein the agent pool initially includes the neural network agent for the worst PVT condition (“For example, analog circuits, such as implemented for incorporation of ADCs, are known to be voltage and/or temperature dependent. Consequently, voltage-temperature (“VT”) corner information can be provided to the neural network 102 as an input to enable the neural network 102 to correct for voltage and/or temperature drifts that can cause errors in the operation of the ADC 101 so that the neural network 102 can further compensate for such voltage and/or temperature drifts. Moreover, temperature and voltage information are often typically readily available on integrated circuits”, C6:L64-67, C7:L1-7. Corner information is mapped to failed/worst PVT conditions. This information is fed to the neural network for the neural network to ultimately correct the failed conditions.)
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, Pivovar, Morency, and Veldhoven before them, to include Veldhoven’s specific teachings of including the most extreme PVT condition information to a neural network in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of including the most extreme PVT condition information to a neural network (see Veldhoven C6:L64-67, C7:L1-7) and designing electrical circuits that can meet performance requirements, and deal with robustness issues such as environmental factors or manufacturing varations (see McConaghy C1:L35-44), as well as including this information in a machine learning to design analog machine-learning ensembles (see McConaghy C31:L52-56).
McConaghy in view of Cao, Pivovar, Morency, and Veldhoven does not appear to teach iteratively searching, by the neural network agents in the agent pool, a common trust region for an updated circuit size that satisfies the specification under respective PVT conditions in the condition pool; and incrementing the agent pool and the condition pool for the iteratively searching until the final circuit size is found to satisfy the specification and all of the PVT conditions.
Le teaches iteratively searching, by the neural network agents in the agent pool, a common trust region for an updated circuit size that satisfies the specification under respective PVT conditions in the condition pool (“ML model 503 is constructed and trained using cloud computational resources 505. That model receives as inputs properly formatted sensor data 507, such as PVT (Process Monitor, Voltage and Temperature) data, etc., and produces by inference digital output signals that are applied to a change control circuit 509. The change control circuit functions to adapt operation of the target analog circuit 511 to achieve the desired performance characteristics under those changed conditions”, P0071. The changes to the circuit include circuit size as recited in P0001. Analysis for changes to the circuit are done with the a Monte Carlo algorithm, and the searching process is repetitive for each of the various conditions as recited in P0077); and incrementing the agent pool and the condition pool for the iteratively searching until the final circuit size is found to satisfy the specification and all of the PVT conditions (“ML model is activated to infer the control register bits necessary to perform the self-adaptation to affect the circuit in the desired manner, typically reflected by certain characteristic of its output (e.g. current, voltage, etc.). To verify the accuracy of the ML model, its inferred output is compared to that obtained from the simulation data for the same PVT condition. If the error is below a certain percentage, the ML model is deemed accurate. The process is repeated for a large number of PVT conditions”, P0077. “Repeating the process” here maps to incrementing the pool of neural network agents and conditions, and this is done until the model under a changed characteristic, such as circuit size, is below an error percentage).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, Pivovar, Morency, Veldhoven, and Le before them, to include Le’s specific teachings of searching for a specific circuit size that meets PVT conditions in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of finding a circuit size that meets specific PVT conditions (see Le P0071, P0077) and designing electrical circuits that can meet performance requirements, and deal with robustness issues such as environmental factors or manufacturing varations (see McConaghy C1:L35-44).
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over McConaghy in view of Cao, Pivovar, Morency, and further in view of Gao et al (Pub.No.: CN 106780605 A), hereafter Gao.
Regarding claims 9 and 19, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. McConaghy does not appear to teach wherein the value metric is an output of a value function applied to the measurement estimate generated by a neural network agent taking the candidate size as input.
Gao teaches wherein the value metric is an output of a value function applied to the measurement estimate generated by a neural network agent taking the candidate size as input (Candidate size is used as an input to the neural network. Neural network outputs a value metric in its optimized cost function. Page 4, paragraph 6. These claims are interpreted broadly due to “value metric” being vague).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, Pivovar, and Gao before them, to include Gao’s specific teachings of using candidate size as an input to a neural network for outputting a value metric in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of using candidate size as an input to a neural network for outputting a value metric (see Le page 4 paragraph 6) and including this information in a machine learning to design analog machine-learning ensembles (see McConaghy C31:L52-56).
Regarding claims 10 and 20, McConaghy in view of Cao, Pivovar, and Morency teaches the limitations of claims 1 and 11 as outlined above. McConaghy does not appear to teach wherein the value metric is an output of a value function that evaluates a sum of normalized measurements.
Gao teaches wherein the value metric is an output of a value function that evaluates a sum of normalized measurements (cost function which outputs a value includes normalized coefficients, page 6, paragraphs 2 and 3).
Accordingly, it would have been obvious to a person having ordinary skill in the
art before the effective filing date of the claimed invention, having the teachings of
McConaghy, Cao, Pivovar, and Gao before them, to include Gao’s specific teachings of outputting a value metric based on evaluating normalized values in McConaghy’s system of analog circuit design. One would have been motivated to make such a combination of outputting a value metric based on evaluating normalized values (see Le page 6 paragraphs 2 and 3) and including this information in a machine learning to design analog machine-learning ensembles (see McConaghy C31:L52-56).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/I.M./Examiner, Art Unit 2141
/MATTHEW ELL/Supervisory Patent Examiner, Art Unit 2141