DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 18MAR2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa et al. (US PGPub No. 2016/0077966 A1), hereinafter referred to as STABRAWA in view of TSIEN (US Patent No. 7,814,292).
Consider Claim 1,
STABRAWA teaches a mobile device (STABRAWA, e.g., ¶0019, wireless.), comprising:
a communication device configured to communicate over a cellular communications network to access a computing system (STABRAWA, e.g., Fig 3:330; ¶0019, wireless link.);
at least one microprocessor configured to access memory via virtual addresses (STABRAWA, e.g., Fig 3:340, processor; ¶0004, working set of the process and/or thread may be in a virtual address space (i.e., uses virtual addresses).); and
a first memory coupled within the mobile device to the at least one microprocessor (STABRAWA, e.g., Fig 3:310, memory.);
wherein the mobile device is configured to:
transmit, via the communication device, a request to borrow, from the computing system, an amount of a second memory of the computing system (STABRAWA, e.g., Fig 7; ¶0139, request to create an external memory allocation is considered a request to borrow.);
maintain a memory map configured to map a first region of the virtual addresses in the first memory and a second region of the virtual addresses into the second memory of the computing system (STABRAWA, e.g., ¶0005, describes that virtual memory may be in primary memory or may be swapped to a second memory; ¶0163-0167, describes various techniques for mapping virtual addresses to physical addresses.);
divide the second region of the virtual addresses into a plurality of sub-regions of the virtual addresses (STABRAWA, e.g., ¶0167. Slabs may be a portion of the virtual address space corresponding to external memory.);
cache data of a subset of the plurality of sub-regions of the virtual addresses in the first memory (STABRAWA, e.g., ¶0018, client may operate locally available memory as cache for externally allocated memory; ¶0164, read portion of the virtual address space from external memory into client memory.); and
maintain a status map configured to indicate, for each respective sub-region of the virtual addresses among the plurality of sub-regions, whether the first memory caches data for the respective sub-region that is mapped to the second memory of the computing system (STABRAWA, e.g., ¶0163, using a map for the virtual address space; ¶0164, page fault handler triggered to move memory from external side to client side. The data structure used to determine if portions of a memory region are mapped to the local address space is considered analogous to the claimed memory status map.).
STABRAWA further describes that memory is arranged in pages (STABRAWA, e.g., ¶0004), but fails to describe wherein the second region of virtual address is a minimal unit in defining mapping to physical addresses in a translation lookaside buffer or wherein the respective sub-region is accessed via caching in the first memory when the status map is configured to indicate that the first memory caches data for the respective sub-region that is mapped to the second memory of the computing system and wherein the respective sub-region is accessed without going through the first memory when the status map is configured to indicate that the first memory does not cache data for the respective sub-region that is mapped to the second memory of the computing system. TSIEN describes systems and methods for managing placement of memory pages and is considered analogous prior art. TSIEN does describe wherein the second region of virtual address is a minimal unit in defining mapping to physical addresses in a translation lookaside buffer (TSIEN, e.g., Col 1:40-59, each page table entry stores an address to a group of physical addresses, such as a page. Further, the TLB stores a page table entry. The region defined by a page table entry is considered to be a minimal unit in defining mapping to physical addresses.) and wherein a respective sub-region is accessed via caching in the first memory when the status map is configured to indicate that the first memory caches data for the respective sub-region that is mapped to the second memory of the computing system and wherein a respective sub-region is accessed without going through the first memory when the status map is configured to indicate that the first memory does not cache data for the respective sub-region that is mapped to the second memory of the computing system (TSIEN, e.g., Col 1:40-59, describes that each page table entry can define whether the associated page (sub-region) is to be cached or uncached.). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of STABRAWA with at least the identified teachings of TSIEN because it improves the efficiency of the memory system by bypassing cache use when it is not needed.
Consider Claim 2,
The system of STABRAWA and TSIEN, as combined, further teaches to use a first portion of the first memory to cache data stored in a second potion of the amount of second memory borrowed from the computing system (STABRAWA, e.g., ¶0018, local memory as cache.).
Consider Claim 3,
The system of STABRAWA and TSIEN, as combined, further teaches to store a memory status map representative of, in the first memory, cache availability statuses of regions of virtual memory addresses (STABRAWA, e.g., ¶0163, map all or a portion of an external memory allocation; ¶0164, page fault if address is not loaded. The data structure used to determine if portions of a memory region are mapped to the local address space is considered analogous to the claimed memory status map.).
Consider Claim 4,
The system of STABRAWA and TSIEN, as combined, further teaches to, in response to a first virtual memory address being accessed by the at least one microprocessor:
determine, based on the memory status map, that a third region of virtual memory addresses containing the first virtual memory address is mapped to the amount of the second memory on the computing system but lacks cache availability in the first memory; communicate, using the communication device, with the computing system to retrieve, from the amount of the second memory of the computing system, first data in the third region of virtual memory addresses; write the first data in the first potion of the first memory; and update the memory status map to indicate the first data of the third region of virtual memory addresses having cache availability in the first memory (STABRAWA, e.g., ¶0164, describes page fault handling which includes loading the faulting page from the external appliance to the local memory.).
Consider Claim 5,
The system of STABRAWA and TSIEN, as combined, further teaches to, in response to a second virtual memory address being accessed by the at least one microprocessor:
determine, based on the memory status map, that the third region of virtual memory addresses containing the second virtual memory address is mapped to the amount of the second memory on the computing system and has cache availability in the first memory; and map the second virtual memory address to the first potion of the first memory (STABRAWA, e.g., ¶0164, load data from mapped area on external appliance to the client cache space.).
Consider Claim 6,
The system of STABRAWA and TSIEN, as combined, further teaches to:
generate a memory fault in response to a determination that the third region of virtual memory addresses containing the first virtual memory address is mapped to the amount of the second memory of the computing system but lacks cache availability in the first memory (STABRAWA, e.g., ¶0164, page fault.).
Consider Claim 7,
The system of STABRAWA and TSIEN, as combined, further teaches wherein the memory fault is configured to cause the mobile device to retrieve the first data from the computing system (STABRAWA, e.g., ¶0164, load data from mapped area on external appliance to the client cache space.).
Consider Claim 8,
The system of STABRAWA and TSIEN, as combined, further teaches: a memory management unit configured to, responsive to the memory fault, use the communication device to retrieve the first data from the computing system and store the first data into the first region in the first memory (STABRAWA, e.g., ¶0164, load data from mapped area on external appliance to the client cache space.).
Consider Claim 9,
The system of STABRAWA and TSIEN, as combined, further teaches wherein the mobile device is configured via instructions injected into an application, the instructions when executed cause the mobile device to make the determination that the third region of virtual memory addresses containing the first virtual memory address is mapped to the amount of the second memory of the computing system but lacks cache availability in the first memory (STABRAWA, e.g., ¶0166, dirty page eviction).
Claims 10-20 are rejected towards a method and non-transitory computer storage medium including substantially identical subject matter and are rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 18MAR2026 have been fully considered but they are not persuasive.
The applicant argues that the cited art fails to describe wherein the second region of virtual address is a minimal unit in defining mapping to physical addresses in a translation lookaside buffer. STABRAWA clearly describes using pages (see, e.g., ¶0004) and TSIEN clearly describes storing page addresses in the TLB (see, e.g., Col 1:40-59). The applicant’s specification further discloses the minimal unit may be a page (see, e.g., ¶0341). For at least these reasons the applicant’s arguments are not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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/Gary W. Cygiel/Primary Examiner, Art Unit 2137