DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Prior Art Rejections
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
Applicant asserts Magklis does not teach extracting “a scalar value for a vector from a scalar field of a vector register based on an immediate field value in an instruction” let alone “multiplying the vector by the scalar value”; and that Fig. 6A is not related to Figs. 11 and 12 in the context of the claimed elements, as the index is a data element within register B that is multiplied by a vector in register A to generate content for populating the result registers. Examiner respectfully disagrees.
In Magklis, index 208 is a field in an instruction 200 ([0057]), wherein the value determines what element in register B that is to be multiplied by a vector in register A. In Fig. 6A, the index value of 1 means element b.sub.1 is selected from register B to be multiplied by the vector in register A, which the resulting products populates the result register. Moreover, the citation of Magklis in page 8 of remarks state “wherein the specified data element (index 1) within a repeating sub-portion (data group) of register B is selected and this data element is multiplied by the vector represented by the respective data group of register A” (emphasis added), is further evidence the index is a field used to select and is not the value that is used to multiply with the vector. Fig. 11 merely shows the circuit configuration of the scenario of Fig. 6A where each lane of element 382 corresponds to a data group in register B.
The Examiner further notes the figures are merely used to teach the concepts of how the index value may be used and are not a strict representation of the number of lanes or lane sizes, as paragraph [0061] of Magklis states “The number of lanes in each register is intentionally not definitively illustrated in FIG. 9A corresponding to the fact that the number of lanes may be freely defined depending on the relative width of the data elements, the number of data elements in each lane, and the available register width” (emphasis added). Regarding Fig. 12, the figure shows a second function which does not require source register 382 to contain repeating data groups (as an example, the contents would be similar to register A in Fig. 6A), and as such each lane may correspond to a single element, thus a scalar value.
In summary, Fig. 6A explicitly shows the index field is used for selecting an element, or scalar value to be multiplied with a vector. Fig. 12 is a configuration of Fig. 11 wherein a single lane is selected by the instruction ([0063]), and the lane may be a single element ([0061]), or scalar value.
Applicant asserts the immediate-index illustrated in Fig. 28 of Guttag is not relevant to the claimed steps of multiplying “the immediate field value by a size of the vector to yield an offset value”, retrieving “a base value from a base register identified by a register pointer in the instruction,” and adding “the base value to the offset value to define an address in memory from which to read the vector” and is silent with respect to these features because the global address unit of Guttag does not multiply the alleged immediate-field “by a size of the vector to yield an offset value,” where such offset value is added to a base value “to define an address in memory from which to read the vector,” where that base value is retrieved “from a base register identified by a register pointer in the instruction”. Examiner respectfully disagrees
Applicant correctly identified the immediate-index is described as an offset field in Guttag. The Examiner notes the terminology in Guttag, such as the “offset field”, is not to be mistaken as the exact same term in the application, such as the “offset value”. Because inventors may be their own lexicographers, all correspondence between Guttag and the application is based on the description of the terms and not merely the term itself. In Guttag, when the offset field is selected, it is scaled by a data size (Fig. 28 element 28; paragraph [0525]), wherein the scaling is a left shift operation. In binary, left shifting is equivalent to multiplying the value by a power of two (2, 4, 8, 16, 32, …), hence a multiplication. Thus, the scaling multiplies the offset field by the data size to produce a scaled result, which corresponds to multiplying “the immediate field value by a size of the vector to yield an offset value”.
Next, address registers 611 of Guttag contain base addresses, wherein one of the registers is selected by the instruction ([0526]), which is retrieving “a base value from a base register identified by a register pointer in the instruction”. Then, the addition/subtraction unit 615 adds (or subtracts) the base address retrieved from the address register with the scaled result to produce a resultant address ([0526]), which corresponds to adding “the base value to the offset value to define an address in memory from which to read the vector”. Therefore, Guttag does teach the recited limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-12, 15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Magklis et al. (U.S. Pub. No. US 20190377573 A1, hereinafter “Magklis”) in further view of Guttag et al. (U.S. Pub. No. US 20030105793 A1, hereinafter “Guttag”).
As per claim 1, Magklis teaches a processing unit (Magklis: Fig. 1; [0051]), comprising: circuitry to extract a scalar value for a vector from a scalar field of a vector register (Magklis: Fig. 12, wherein lane 0 of element 382 corresponds to the scalar; [0063]) based on an immediate field value in an instruction (Magklis: Fig. 6A; [0057]);
read the vector from the address in the memory (Magklis: Fig. 2; [0052]) and multiply the vector by the scalar value (Magklis: Fig. 12 elements 400, 402, 404, 406).
However, while Magklis allows using the index for multiple pieces of information ([0059] “a selected complex pair from the data groups of register B identified by the index”, [0043] “a “complex pair” (represented by two individual data values)”) that are nonadjacent ([0044] “perform the multiply-accumulate of complex numbers using a selected permutation of the data values”), Magklis does not explicitly teach multiply the immediate field value by a size of the vector to yield an offset value; retrieve a base value from a base register identified by a register pointer in the instruction; add the base value to the offset value to define an address in memory from which to read the vector.
Guttag teaches multiply the immediate field value by a size of the vector to yield an offset value (Guttag: Fig. 28 element 614; [0525]); retrieve a base value from a base register identified by a register pointer in the instruction (Guttag: Fig. 28 elements 611, 615; [0526]); add the base value to the offset value to define an address in memory from which to read the vector (Guttag: Fig. 28; [0526]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine, with a reasonable expectation of success, the index field (Fig. 6A element 208) and load/store unit (Fig. 1 element 22) of Magklis with the addressing unit of Guttag (Fig. 28). One would have been motivated to combine these references because both references disclose accessing memory based on instructions, and Guttag improves Magklis by reducing the number of instructions of a loop, which “can greatly improve the performance of the process” (Guttag: [0548]).
As per claim 2, Magklis/Guttag further teaches the processing unit of claim 1, further comprising: circuitry that implements an element-by-element sum, wherein the circuitry that implements the element-by-element sum is to: receive an output from the circuitry that reads the vector from the memory (Magklis: [0063]);
generate a target vector by summing a previous instance of the target vector with the output received from the circuitry that reads the vector from the memory (Magklis: [0063]);
and store the target vector (Magklis: [0063]).
As per claim 3, Magklis/Guttag further teaches the processing unit of claim 2, wherein the target vector is stored in the vector register (Magklis: [0036]).
As per claim 7, Magklis/Guttag further teaches the processing unit of claim 1, wherein the memory and the circuitry are on the same ship (Magklis: Fig. 1, [0051]).
As per claim 8, Magklis/Guttag further teaches the processing unit of claim 1, wherein the vector register is internal to the processing unit (Magklis: [0030]).
As per claim 9, Magklis/Guttag further teaches the processing unit of claim 8, wherein the vector register comprises a 128-bit register (Magklis: [0063]).
As per claim 10, Magklis/Guttag further teaches the processing unit of claim 8, wherein the vector register comprises at least one of a 128-bit register, a 256-bit register, and a 512-bit register (Magklis: [0063] The examiner notes “the vector register” is interpreted as a single register.).
As per claim 11, the claim is directed to a system that implements the same features as the processing unit of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Magklis/Guttag teaches a system, comprising: memory that stores a vector (Magklis: Fig. 2, [0052]).
As per claim 12, Magklis/Guttag further teaches the system of claim 11, wherein the processing unit comprises a Central Processing Unit (Magklis: [0051]).
As per claim 15, Magklis/Guttag further teaches the system of claim 11, wherein the processing unit is further configured to implement an element-by-element sum of a plurality of vector-scalar multiplications (Magklis: Fig 12, [0063]).
As per claim 17, Magklis/Guttag further teaches the system of claim 11, wherein the vector register is internal to the processing unit (Magklis: [0030]).
Claims 6, 13, 14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Magklis in view of Guttag in further view of Gradstein et al. (U.S. Pub. No. US 20200201932 A1, hereinafter “Gradstein”).
As per claim 6, Magklis/Guttag teaches the processing unit of claim 1. However, Magklis/Guttag does not explicitly teach wherein the memory comprises a local cache memory.
Gradstein teaches wherein the memory comprises a local cache memory (Gradstein: [0124]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to substitute, with a reasonable expectation of success, the memory of Magklis (Fig. 1 element 14) with the internal cache of Gradstein. One would have been motivated to combine these references because both references disclose memory storing data for vector multiplication and Gradstein improves Magklis by allowing low latency cache access to memory (Gradstein: [0379]).
As per claim 13, Magklis/Guttag teaches the system of claim 11. However, Magklis/Guttag does not explicitly teach wherein the processing unit comprises a Graphics Processing Unit.
Gradstein teaches wherein the processing unit comprises a Graphics Processing Unit (Gradstein: [0383]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine, with a reasonable expectation of success, the processing apparatus of Magklis (Fig. 1) with the graphics processing unit processor of Gradstein. One would have been motivated to combine these references because both references disclose processing units that compute vector multiplication, and achieve the predictable result of a graphics processing unit capable of vector multiplication.
As per claim 14, Magklis/Guttag teaches the system of claim 11. However, Magklis/Guttag does not explicitly teach wherein the processing unit comprises a Data Processing Unit.
Gradstein teaches wherein the processing unit comprises a Data Processing Unit (Gradstein: [0383]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine, with a reasonable expectation of success, the processing apparatus of Magklis (Fig. 1) with the accelerator circuit of Gradstein. One would have been motivated to combine these references because both references disclose processing data to compute vector multiplication, and achieve the predictable result of a data processing unit capable of vector multiplication.
As per claim 16, Magklis/Guttag teaches the system of claim 11. However, Magklis/Guttag does not explicitly teach wherein the memory comprises a local cache memory.
Gradstein teaches wherein the memory comprises a local cache memory (Gradstein: [0124]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to substitute, with a reasonable expectation of success, the memory of Magklis (Fig. 1 element 14) with the internal cache of Gradstein. One would have been motivated to combine these references because both references disclose memory storing data for vector multiplication and Gradstein improves Magklis by allowing low latency cache access to memory [0379].
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Magklis in view of Guttag in further view of Luick et al. (U.S. Pub. No. US 20090106527 A1, hereinafter “Luick”).
As per claim 18, the claim is directed to a processing unit that implements the same features as the processing unit of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Magklis/Guttag teaches a processing unit, comprising: a vector register (Magklis: [0030]);
and second circuitry that implements an element-by-element sum by receiving a plurality of outputs from the first circuitry (Magklis: [0063]),
However, while Magklis suggests the source registers and output register as 128-bits (Magklis Fig. 11), and that a source register can also be the output register (Magklis [0033], [0036]), Magklis does not explicitly teach wherein an output of the second circuitry comprises an output vector having a same size as the vector.
Luick teaches wherein an output of the second circuitry comprises an output vector having a same size as the vector (Luick: [0078-0079]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to substitute, with a reasonable expectation of success, the data types of Magklis with the data types of Luick. One would have been motivated to combine these references because both references disclose data for vector multiplication, and the combination allows for a more robust processing technique that allows for more useful applications within the field.
As per claim 19, Magklis/Guttag/Luick further teaches the processing unit of claim 18, wherein the first circuitry is configured to implement a matrix multiplication with the vector (Magklis: Fig. 12, [0063]).
As per claim 20, Magklis/Guttag/Luick further teaches the processing unit of claim 18, wherein the vector register comprises at least one of a 128-bit register, a 256-bit register, and a 512-bit register (Magklis: [0063]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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