Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/4/2026 has been entered.
Remarks
This Office Action is responsive to Applicants' Amendment filed on June 4, 2026, in which claims 1, 11, and 18 are currently amended. Claims 2-3 are canceled. Claims 1 and 4-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 11, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
The previous rejections to claims 1-17 under 35 U.S.C. § 112(b) are hereby withdrawn, as necessitated by applicant's amendments and remarks made to the rejections.
Applicant’s arguments with respect to rejection of claims 1-10 and 18-20 under 35 U.S.C. 101 based on amendment have been considered and are persuasive. The rejections to claims 1-110 and 18-20 under 35 U.S.C. § 101 are hereby withdrawn, as necessitated by applicant's amendments and remarks made to the rejections.
Applicant’s arguments with respect to rejection of claims 1-10 and 18-20 under 35 U.S.C. 103 based on amendment have been considered, however, are not persuasive.
With respect to Applicant’s arguments on p. 11 of the Remarks submitted 6/4/2026 that “neither Zhang nor Henry disclose or suggest selecting an activation function circuit based on vector size of an input vector”, Examiner respectfully disagrees. Henry discloses ([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124.") where Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits. This activation is based on a vector/row size/bit-width ([¶0056] "The sequencer 128 fetches instructions from the program memory 129 and executes them" [¶0077] " The instructions flow down the pipeline and control the various functional units […] the initialize NPU instruction specifies the activation function to be performed on the accumulator 202 value 217, and a value indicating the specified activation function is saved in a configuration register for later use by the AFU 212 portion of the pipeline once the final accumulator 202 value 217 has been generated" [¶0085] "As shown, on clock 1, the 512 16-bit data words of row 17 are read out of the data RAM 122 and provided to the 512 NPUs 126"). Henry clearly discloses a processor whose NNU/sequencer fetches and executes instructions and that the activation function data is read from RAM as rows of data words (vectors) of a vector size (8/9-bit and wide 12/16-bit size configurations). For at least these reasons and those further detailed below, Examiner asserts that the interpretation of Henry to cover the amended claim limitations is reasonable and should be maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 4-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 11, and 18, “the first activation function” lacks antecedent basis. “A first activation function” is recommended.
The remaining claims are rejected with respect to their dependence on the rejected claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, 7-11, and 15-20 are rejected under U.S.C. §102(a)(1) as being anticipated by Henry (US20170103300A1).
Regarding claim 1, Henry teaches A processor, comprising:([¶0043] "Referring now to FIG. 1, a block diagram illustrating a processor 100 that includes a neural network unit (NNU) 121 is shown. The processor 100 includes an instruction fetch unit 101, an instruction cache 102, and instruction translator 104, a rename unit 106, reservation stations 108, media registers 118, general purpose registers (GPR) 116, execution units 112 other than the NNU 121, and a memory subsystem 114.")
a lookup table that matches a plurality of activation functions to a plurality of activation function circuits such that each activation function is matched with at least one activation function circuit ([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124." Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits.)
that is capable of approximating that activation function ([¶0065] "circuitry of the AFU 212 performs the activation function in a single clock cycle. In one embodiment, the AFU 212 comprises tables that receive the accumulated value and output a value that closely approximates the value that the true activation function would provide for some of the activation functions, e.g., sigmoid, hyperbolic tangent, softplus.")
approximation circuitry to: receive a processor instruction comprising an input vector of a vector size ([¶0056] "The sequencer 128 fetches instructions from the program memory 129 and executes them" [¶0077] " The instructions flow down the pipeline and control the various functional units […] the initialize NPU instruction specifies the activation function to be performed on the accumulator 202 value 217, and a value indicating the specified activation function is saved in a configuration register for later use by the AFU 212 portion of the pipeline once the final accumulator 202 value 217 has been generated" [¶0085] "As shown, on clock 1, the 512 16-bit data words of row 17 are read out of the data RAM 122 and provided to the 512 NPUs 126" Henry clearly discloses a processor whose NNU/sequencer fetches and executes instructions and that the activation function data is read from RAM as rows of data words (vectors) of a vector size (8/9-bit and wide 12/16-bit size configurations))
select, from the lookup table and based on the vector size, a first activation function circuit from among the plurality of activation function circuits, which is capable of operating on the vector size of the input vector ([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124." Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits.)
apply, the first activation function to the input vector using the selected first activation function circuit; ([¶0075] "The fourth row, at address 3, specifies an activation function instruction. The activation function instruction instructs the AFU 212 to perform the specified activation function on the accumulator 202 value 217 to generate the result 133. The activation functions according to one embodiment are described in more detail below" [¶0252] "The tan h 3022, sigmoid 3024 and softplus 3026 modules perform their respective activation functions (described above)")
generate an output vector including a result of the first activation function applied to the input vector;([¶0065] "The AFU 212 receives the output 217 of the accumulator 202. The AFU 212 performs an activation function on the accumulator 202 output 217 to generate a result 133 of FIG. 1" [¶0057] "The N NPUs 126 generate N result words 133 that may be written back to a row of the weight RAM 124 or to the data RAM 122. Preferably, the weight RAM 124 and the data RAM 122 are directly coupled to the N NPUs 126" [¶0115] "At clock 521, once all 512 results associated with the 512 NPUs 126 have been generated and written to the row buffer 1104, the row buffer 1104 begins to write its contents to the data RAM 122 or weight RAM 124" Henry explicitly discloses that each NPU generates result 133 and that the 512 NPUs write AFU outputs back as results to a row of data RAM. This is an explicit row/vector of activation function results)
send the output vector to a node of a machine learning model for training or inference ([¶0096] "if the results are simply to be used by the next layer, then the architectural program may not need to read the results from the data RAM 122" [¶0065] "(The normalized result is sometimes referred to as an “activation” that, as described herein, is the output of an instant node that a receiving node multiplies by a weight associated with the connection between the outputting node and the receiving node to generate a product that is accumulated with other products associated with the other input connections to the receiving node.)").
Regarding claim 4, Henry teaches The processor of claim 1, wherein the lookup table is used for data aggregation during the first activation function. ([¶0065] "the control register 127, selects one of the activation functions to perform on the accumulator 202 output 217").
Regarding claim 5, Henry teaches The processor of claim 1, wherein the input vector is part of a matrix.(Henry [¶0169] "As understood in the context of the present disclosure, a convolution kernel is a matrix of coefficients, which may also be referred to as weights, parameters, elements or values.").
Regarding claim 7, Henry teaches The processor of claim 1, wherein the activation function comprises a sigmoid function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below.").
Regarding claim 8, Henry teaches The processor of claim 1, wherein the activation function comprises a tan h(x) function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below.").
Regarding claim 9, Henry teaches The processor of claim 1, wherein the activation function comprises a non-linear function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below." sigmoid and htan are non-linear).
Regarding claim 10, Henry teaches The processor of claim 1, wherein the input vector comprises N elements and wherein each of the N elements are processed during a single clock cycle.(Henry [¶0065] "circuitry of the AFU 212 performs the activation function in a single clock cycle" [¶0073] "the 512 data words from row 17 of the data RAM 122 are provided to the corresponding data input 207 of the 512 NPUs 126 and the 512 weight words from row" [¶0057] "The N NPUs 126 generate N result words 133 that may be written back to a row of the weight RAM 124 or to the data RAM 122. Preferably, the weight RAM 124 and the data RAM 122 are directly coupled to the N NPUs 126" [¶0115] "At clock 521, once all 512 results associated with the 512 NPUs 126 have been generated and written to the row buffer 1104, the row buffer 1104 begins to write its contents to the data RAM 122 or weight RAM 124").
Regarding claim 11, Henry teaches a system, comprising: ([¶0045] "The instruction fetch unit 101 controls the fetching of architectural instructions 103 from system memory (not shown) into the instruction cache 102. The instruction fetch unit 101 provides a fetch address to the instruction cache 102 that specifies a memory address at which the processor 100 fetches a cache line of architectural instruction bytes into the instruction cache 102")
a lookup table that matches a plurality of activation functions to a plurality of activation function circuits such that each activation function is matched with at least one activation function circuit ([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124." Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits.)
capable of approximating that activation function; ([¶0065] "circuitry of the AFU 212 performs the activation function in a single clock cycle. In one embodiment, the AFU 212 comprises tables that receive the accumulated value and output a value that closely approximates the value that the true activation function would provide for some of the activation functions, e.g., sigmoid, hyperbolic tangent, softplus.")
and a processor to: receive a processor instruction comprising an input vector of a vector size;([¶0056] "The sequencer 128 fetches instructions from the program memory 129 and executes them" [¶0077] " The instructions flow down the pipeline and control the various functional units […] the initialize NPU instruction specifies the activation function to be performed on the accumulator 202 value 217, and a value indicating the specified activation function is saved in a configuration register for later use by the AFU 212 portion of the pipeline once the final accumulator 202 value 217 has been generated" [¶0085] "As shown, on clock 1, the 512 16-bit data words of row 17 are read out of the data RAM 122 and provided to the 512 NPUs 126" Henry clearly discloses a processor whose NNU/sequencer fetches and executes instructions and that the activation function data is read from RAM as rows of data words (vectors) of a vector size (8/9-bit and wide 12/16-bit size configurations))
select, from the lookup table and based on the vector size, a first activation function circuit, from among the plurality of activation function circuits, which is capable of operating on the vector size of the input vector([¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection to the sign restorer 3034, which converts the positive form output of the mux 3032 to a negative form if the original accumulator 202 value 217was a negative value, e.g., to two's-complement form." [¶0077] " the initialize NPU instruction specifies the activation function to be performed on the accumulator 202 value 217")
apply the first activation function to the selected first activation function circuit such that all elements of the input vector are processed during a single clock cycle; ([¶0065] "circuitry of the AFU 212 performs the activation function in a single clock cycle" [¶0073] "the 512 data words from row 17 of the data RAM 122 are provided to the corresponding data input 207 of the 512 NPUs 126 and the 512 weight words from row 0 of the weight RAM 124 are provided to the corresponding weight input 206 of the 512 NPUs 126." [¶0076] "the execution of the write AFU output instruction may be overlapped with the execution of other instructions in a pipelined nature such that the write AFU output instruction effectively executes in a single clock cycle" The input vector is interpreted as the set of values held across the NPUs/accumulators)
and generate an output vector including a result of the first activation function applied to the input vector; and ([¶0053] "The weight RAM 124 is arranged as W rows of N weight words, and the data RAM 122 is arranged as D rows of N data words. Each data word and each weight word is a plurality of bits, preferably 8 bits, 9 bits, 12 bits or 16 bits. Each data word functions as the output value (also sometimes referred to as an activation) of a neuron of the previous layer in the network" Activation data word (bit vector) interpreted as output vector based on the performed first activation function)
send the output vector to a node of a machine learning model for training or inference([¶0096] "if the results are simply to be used by the next layer, then the architectural program may not need to read the results from the data RAM 122" [¶0065] "(The normalized result is sometimes referred to as an “activation” that, as described herein, is the output of an instant node that a receiving node multiplies by a weight associated with the connection between the outputting node and the receiving node to generate a product that is accumulated with other products associated with the other input connections to the receiving node.)").
Regarding claim 15, Henry teaches The system of claim 11, wherein the processor is to perform the activation function in an absence of a memory read or memory write.(Henry [¶0075] "The fourth row, at address 3, specifies an activation function instruction. The activation function instruction instructs the AFU 212 to perform the specified activation function on the accumulator 202 value 217 to generate the result 133" [¶0076] "The fifth row, at address 4, specifies a write AFU output instruction that instructs the 512 NPUs 126 to write back their AFU 212 output as results 133 to a row of the data RAM 122" Henry explicitly discloses the activation instruction operating on the already-resident (in absence of a memory read or write) accumulator 202 value 217 to generate result 133).
Regarding claim 16, Henry teaches The system of claim 11, wherein the activation function comprises a non-linear function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below." sigmoid and htan are non-linear).
Regarding claim 17, Henry teaches The system of claim 11, wherein the activation function comprises at least one of a sigmoid function and a tan h(x) function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below.").
Regarding claim 18, Henry teaches A device, comprising: a processor to: ([¶0043] "Referring now to FIG. 1, a block diagram illustrating a processor 100 that includes a neural network unit (NNU) 121 is shown. The processor 100 includes an instruction fetch unit 101, an instruction cache 102, and instruction translator 104, a rename unit 106, reservation stations 108, media registers 118, general purpose registers (GPR) 116, execution units 112 other than the NNU 121, and a memory subsystem 114.")
receive a processor instruction comprising an input vector for a first activation function from among a plurality of activations functions performable by the processor, the input vector having a vector size([¶0056] "The sequencer 128 fetches instructions from the program memory 129 and executes them" [¶0077] " The instructions flow down the pipeline and control the various functional units […] the initialize NPU instruction specifies the activation function to be performed on the accumulator 202 value 217, and a value indicating the specified activation function is saved in a configuration register for later use by the AFU 212 portion of the pipeline once the final accumulator 202 value 217 has been generated" [¶0085] "As shown, on clock 1, the 512 16-bit data words of row 17 are read out of the data RAM 122 and provided to the 512 NPUs 126" Henry clearly discloses a processor whose NNU/sequencer fetches and executes instructions and that the activation function data is read from RAM as rows of data words (vectors) of a vector size (8/9-bit and wide 12/16-bit size configurations))
select, from a lookup table and based on the vector size, a first activation function circuit from among a plurality of activation function circuits capable of operating on the vector size of the input vector;([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124." Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits.)
wherein the lookup table matches the plurality of activation functions to the plurality of activation function circuits such that each activation function is matched with at least one activation function circuit ([¶0224] "The control register 127 includes the following fields […] activation function 2934 […] output command 2956" [¶0230] "The activation function 2934 specifies the function applied to the accumulator 202 value 217 to generate the output 133 of the NPU 126" [¶0256] "The mux 3032 selects the appropriate input specified by the activation function 2934 value and provides the selection" [¶0104] "select one of the activation function circuit outputs" [¶0225] "The configuration 2902 implies the size of the input words received from the data RAM 122 and the weight RAM 124." Henrys control register 127 contains an activation-function field 2934 whose value identifies the activation function, and that value drives mux 3032, where each value corresponds to a mux input and each mux input is wired to a particular activation function circuit, to select the corresponding activation-function circuit/module output. A register is synonymous with a table and the control register 127 is interpreted as a lookup table that matches activation function to activation function circuits.)
that is capable of approximating that activation function;([¶0065] "circuitry of the AFU 212 performs the activation function in a single clock cycle. In one embodiment, the AFU 212 comprises tables that receive the accumulated value and output a value that closely approximates the value that the true activation function would provide for some of the activation functions, e.g., sigmoid, hyperbolic tangent, softplus.")
apply, the first activation function to the input vector using the selected first activation function circuit; ([¶0075] "The fourth row, at address 3, specifies an activation function instruction. The activation function instruction instructs the AFU 212 to perform the specified activation function on the accumulator 202 value 217 to generate the result 133. The activation functions according to one embodiment are described in more detail below" [¶0252] "The tan h 3022, sigmoid 3024 and softplus 3026 modules perform their respective activation functions (described above)")
generate an output vector including a result of the first activation function applied to the input vector; and ([¶0065] "The AFU 212 receives the output 217 of the accumulator 202. The AFU 212 performs an activation function on the accumulator 202 output 217 to generate a result 133 of FIG. 1" [¶0057] "The N NPUs 126 generate N result words 133 that may be written back to a row of the weight RAM 124 or to the data RAM 122. Preferably, the weight RAM 124 and the data RAM 122 are directly coupled to the N NPUs 126" [¶0115] "At clock 521, once all 512 results associated with the 512 NPUs 126 have been generated and written to the row buffer 1104, the row buffer 1104 begins to write its contents to the data RAM 122 or weight RAM 124" Henry explicitly discloses that each NPU generates result 133 and that the 512 NPUs write AFU outputs back as results to a row of data RAM. This is an explicit row/vector of activation function results)
send the output vector to a node of a machine learning model for training or inference([¶0096] "if the results are simply to be used by the next layer, then the architectural program may not need to read the results from the data RAM 122" [¶0065] "(The normalized result is sometimes referred to as an “activation” that, as described herein, is the output of an instant node that a receiving node multiplies by a weight associated with the connection between the outputting node and the receiving node to generate a product that is accumulated with other products associated with the other input connections to the receiving node.)").
Regarding claim 19, Henry teaches The device of claim 18, wherein the activation function is performed in an absence of performing a memory read or memory write.(Henry [¶0075] "The fourth row, at address 3, specifies an activation function instruction. The activation function instruction instructs the AFU 212 to perform the specified activation function on the accumulator 202 value 217 to generate the result 133" [¶0076] "The fifth row, at address 4, specifies a write AFU output instruction that instructs the 512 NPUs 126 to write back their AFU 212 output as results 133 to a row of the data RAM 122" Henry explicitly discloses the activation instruction operating on the already-resident (in absence of a memory read or write) accumulator 202 value 217 to generate result 133).
Regarding claim 20, Henry teaches The device of claim 18, wherein the activation function comprises at least one of a sigmoid function and a tan h(x) function.(Henry [¶0230] "the activation functions 2934 include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below.").
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under U.S.C. §103 as being unpatentable over the combination of Henry and Chen (US20200034698A1).
Regarding claim 6, Henry teaches The processor of claim 1.
However, Henry doesn't explicitly teach, wherein the activation function is made available on a vector instruction list.
Chen, in the same field of endeavor, teaches The processor of claim 1, wherein the activation function is made available on a vector instruction list.([¶0045] "[0045] the controller unit 11 is configured to extract a first instruction from the storage unit, parse the first instruction to obtain an operation code of the operation instruction and an operation domain, extract input data and weight data corresponding to the operation domain, and the operation code, the input data and the weight data are transmitted to the operation unit, and the operation code includes at least one of the following codes: an operation code of the matrix operation instruction, a vector operation instruction operation code, an activation operation instruction operation code, an offset operation instruction operation code, a convolution operation instruction operation code, a conversion operation instruction operation code and the like;").
Henry as well as Chen are directed towards neural network accelerators. Therefore, Zhang and Henry as well as Chen are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Zhang and Henry with the teachings of Chen by having the activation function as part of a vector instruction list. Chen provides as additional motivation for combination ([Abstract] “The technical solution provided by this application has advantages of a fast calculation speed and energy-saving”).
Claims 12, 13, and 14 are rejected under U.S.C. §103 as being unpatentable over the combination of Henry and Zhang ("nn-Meter: Towards Accurate Latency Prediction of Deep-Learning Model Inference on Diverse Edge Devices", 2021).
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Table 6 of Zhang
Regarding claim 12, Henry teaches The system of claim 11.
However, Henry doesn't explicitly teach wherein the processor comprises a Central processor.
Zhang, in the same field of endeavor, teaches The system of claim 11, wherein the processor comprises a Central processor.([¶0044] "The processor 100 is an electronic device that functions as a central processing unit (CPU) on an integrated circuit").
Henry as well as Zhang are directed towards neural network hardware acceleration. Therefore, Zhang as well as Henry are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Henry by using a table-driven architectural mapping approach as taught by Zhang to provide an explicit lookup table that matches activation functions to corresponding activation circuits within Henry’s neural network accelerator. In other words it would have been obvious to use the processor system in Henry as one of the hardware targets in Zhang. Henry provides as additional motivation for combination ([¶0130] “the media registers 118 can concurrently write to or read from the buffer 1704 while the NPUs 126 are also reading from or writing to the weight RAM 124 (although preferably the NPUs 126 stall, if they are currently executing, to avoid accessing the weight RAM 124 while the buffer 1704 is accessing the weight RAM 124). This may advantageously provide improved performance”). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 13, Henry teaches The system of claim 11.
However, Henry doesn't explicitly teach wherein the processor comprises a Graphics processor.
Zhang, in the same field of endeavor, teaches The system of claim 11, wherein the processor comprises a Graphics processor. ([p. 86 §5.1] "Conv and DWConv take 94.2%, 91.91%, 75.5% of the model latency on the CPU, GPU, and VPU, respectively" See Table 6).
Henry as well as Zhang are directed towards neural network hardware acceleration. Therefore, Zhang as well as Henry are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Henry by using a table-driven architectural mapping approach as taught by Zhang to provide an explicit lookup table that matches activation functions to corresponding activation circuits within Henry’s neural network accelerator. In other words it would have been obvious to use the processor system in Henry as one of the hardware targets in Zhang. Henry provides as additional motivation for combination ([¶0130] “the media registers 118 can concurrently write to or read from the buffer 1704 while the NPUs 126 are also reading from or writing to the weight RAM 124 (although preferably the NPUs 126 stall, if they are currently executing, to avoid accessing the weight RAM 124 while the buffer 1704 is accessing the weight RAM 124). This may advantageously provide improved performance”). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 14, Henry teaches The system of claim 11.
However, Henry doesn't explicitly teach wherein the processor comprises a Data processor.
Zhang, in the same field of endeavor, teaches The system of claim 11, wherein the processor comprises a Data processor. ([p. 86 §5.1] "Conv and DWConv take 94.2%, 91.91%, 75.5% of the model latency on the CPU, GPU, and VPU, respectively" VPU interpreted as data processor. See also Table 6.).
Henry as well as Zhang are directed towards neural network hardware acceleration. Therefore, Zhang as well as Henry are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Henry by using a table-driven architectural mapping approach as taught by Zhang to provide an explicit lookup table that matches activation functions to corresponding activation circuits within Henry’s neural network accelerator. In other words it would have been obvious to use the processor system in Henry as one of the hardware targets in Zhang. Henry provides as additional motivation for combination ([¶0130] “the media registers 118 can concurrently write to or read from the buffer 1704 while the NPUs 126 are also reading from or writing to the weight RAM 124 (although preferably the NPUs 126 stall, if they are currently executing, to avoid accessing the weight RAM 124 while the buffer 1704 is accessing the weight RAM 124). This may advantageously provide improved performance”). This motivation for combination also applies to the remaining claims which depend on this combination.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Henry (US20170103304A1) has a disclosure substantially matching the primary reference.
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/SIDNEY VINCENT BOSTWICK/Examiner, Art Unit 2124
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