DETAILED ACTION
This office action addresses Applicant’s response filed on 1 April 2026. Claims 1-24 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-14, 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus (US 2020/0006621) in view of Falcon (US 2019/0006572), McDermott (“Quantum–classical interface based on single flux quantum digital logic”), El Bouayadi (US 2019/0027800, hereinafter, “Bouayadi”), Karalekas (US 2021/0357797), and Li (US 2020/0250564)
Regarding claim 1, Mutus discloses a system capable of information processing based at least in part on quantum computing using quantum states of quantum bits (¶33), comprising: a cryostat system (¶34); a quantum computing module enclosed by the cryostat system at the low cryogenic temperature (¶¶33-34), the quantum computing module comprising a plurality of first integrated chips structured to support a plurality of quantum bit circuits, wherein each quantum bit circuit is structured as a superconducting circuit at the low cryogenic temperature to exhibit different quantum states as a quantum-mechanical system and to quantum-mechanically interact with other quantum bit circuits via quantum entanglement to cause superposition or correlation of different quantum states of the quantum bit circuits (¶¶33, 34, 49);
a quantum bit management circuit module enclosed by the cryostat system, located adjacent to the quantum computing module and coupled to be maintained at a cryogenic temperature, the quantum bit management circuit module comprising a second integrated chip configured to include non-quantum mechanical digital circuitry that performs digital processing at the low cryogenic temperature, and wherein the second integrated chip is engaged to the first integrated chip to form a multichip module to transfer signals therebetween; and electrically conductive bumps formed to engage the first and second integrated chips to each other (¶¶33, 35); and
communication links to facilitate the information processing, the communication links including one or more of first communication links formed between the quantum computing module and the quantum bit management circuit module where each of the one or more of first communication links is configured to provide communications with a first communication latency (¶35)
Mutus does not appear to explicitly disclose the quantum computing module further comprising a plurality of readout resonators supported by the plurality of first integrated chips and structured to interact with the plurality of quantum bit circuits, respectively, to produce quantum bit circuit readout signals. However, these features are known, as admitted by Applicant (Specification ¶55). Falcon also discloses these limitations (¶104). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus and Falcon, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing determination of qubit state. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum system comprising a chip having quantum circuit elements and a chip having non-quantum circuit elements. Falcon discloses that the quantum circuit chip includes readout resonators, which is well-known. The teachings of Falcon are directly applicable to Mutus in the same way, so that Mutus’s quantum chip would include readout resonators to allow determination of qubit state.
Mutus does not appear to explicitly disclose a cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and higher cryogenic temperatures; circuit modules enclosed by the cryostat system at the higher cryogenic temperatures and structured to communicate with the quantum bit management circuit module in connection with the control signals and readout signals; quantum bit control circuits supported by the second integrated chip and structured to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and quantum bit readout circuits supported by the second integrated chip and structured to output readout signals from the quantum bit circuits, respectively, the readout signals representing quantum states of the quantum bit circuits, respectively, the quantum bit control circuits and quantum bit readout circuits structured to include superconducting circuits at the low cryogenic temperature and operable to operate with the control signals and readout signals based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature; wherein the control signals are generated based in part on qubit readout information from the quantum bit management circuit module operated at the low cryogenic temperature; circuit modules enclosed by the cryostat system at the higher cryogenic temperatures and structure to communicate with the quantum bit management circuit module in connection with the control signals and readout signals; electrically conductive wires, including at least one flexible superconducting cable comprising electrically conductive cable segments, coupled between the quantum bit management circuit module and at least one of the circuit modules situated at higher temperature stages of the cryostat system to provide communications and transfer signals therebetween, each of the electrically conductive cables coupled between the quantum bit management circuit module and at least one of the circuit modules situated at higher temperature stages of the cryostat system to provide communications and transfer signals therebetween.
McDermott discloses a cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and higher cryogenic temperatures; a quantum computing module enclosed by the cryostat system at the low cryogenic temperature, the quantum computing module comprising a first integrated chip structured to support a plurality of quantum bit circuits, wherein each quantum bit circuit is structured as a superconducting circuit at the low cryogenic temperature to exhibit different quantum states as a quantum-mechanical system; a quantum bit management circuit module enclosed by the cryostat system, located adjacent to the quantum computing module and coupled to be maintained at a cryogenic temperature, the quantum bit management circuit module comprising a second integrated chip configured to include non-quantum mechanical digital circuitry that performs digital processing at the low cryogenic temperature, and wherein the second integrated chip is engaged to the first integrated chip to form a multichip module to transfer signals therebetween; circuit modules enclosed by the cryostat system at the higher cryogenic temperatures and structured to communicate with the quantum bit management circuit module in connection with the control signals and readout signals; quantum bit control circuits supported by the second integrated chip and structured to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and quantum bit readout circuits supported by the second integrated chip and structured to output readout signals from the quantum bit circuits, respectively, the readout signals representing quantum states of the quantum bit circuits, respectively, the quantum bit control circuits and quantum bit readout circuits structured to include superconducting circuits at the low cryogenic temperature and operable to operate with the control signals and readout signals based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature; wherein the control signals are generated based in part on qubit readout information from the quantum bit management circuit module operated at the low cryogenic temperature; circuit modules enclosed by the cryostat system at the higher cryogenic temperatures and structure to communicate with the quantum bit management circuit module in connection with the control signals and readout signals (p. 3, Fig. 1 and last paragraph); and
electrically conductive wires, including at least one flexible superconducting cable comprising electrically conductive cable segments, coupled between the quantum bit management circuit module and at least one of the circuit modules situated at higher temperature stages of the cryostat system to provide communications and transfer signals therebetween, each of the electrically conductive cables coupled between the quantum bit management circuit module and at least one of the circuit modules situated at higher temperature stages of the cryostat system to provide communications and transfer signals therebetween according to different temperature ranges corresponding to the different cryogenic stages (p. 3, Fig. 1; p. 14, ¶3 flexible Kapton tape).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, and McDermott, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of reducing wire count, heat load, and latency. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum system comprising a quantum circuit chip bonded to a non-quantum circuit chip. McDermott teaches that the chips are in a low temperature stage in a cryostat and communicate with additional chips in higher temperature stages in the cryostat through superconducting cables, in order to reduce wire count, heat load, and latency. The teachings of McDermott are directly applicable to Mutus in the same way, so that Mutus would similarly implement communicatively-coupled chips in low-temp and high-temp stages of a cryostat in order to reduce wire count, heat load, and latency.
Mutus does not appear to explicitly disclose the electrically conductive cable segments coupled between the quantum bit management circuit module and the at least one of the circuit modules via at least some of the electrically conductive bumps. Bouayadi discloses these limitations (¶66). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, and Bouayadi, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing cables to connect to components. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum computing system. McDermott teaches that the quantum computing system includes chips connected by flexible cables. Bouayadi teaches that the cable connections are formed by electrically conductive bumps. The teachings of Bouayadi are directly applicable to Mutus and McDermott, so that they would similarly use bumps to allow connections between cables and components.
Mutus does not appear to explicitly disclose communication links to facilitate the information processing at different speeds during operation of the system, comprising one or more of second communication links formed between quantum computing module and at least one of the circuit modules where each of the one or more of second communication links is configured to provide communications with a second communication latency longer than the first communication latency, and one or more of third communication links formed between the quantum computing module, the quantum bit management circuit module, and one or more processors at room temperature and located external to the cryostat system where each of the one or more of third communication links is configured to provide communications with a third communication latency longer than the second communication latency, the non-quantum mechanical digital circuitry configured to communicate with the one or more processors via at least some of the communication links to provide digital information based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature to the one or more processors. Karalekas discloses these limitations (Fig. 9, communications links at stage 970 stage having lower latency than those at stage 960, which in turn have lower latency that those at stages 910-950; ¶¶16, 17, 76, 104, 105). McDermott also discloses the same (p. 3, Fig. 1 and last paragraph; p. 11, Fig. 6 and second paragraph, SFQ communicating with room-temperature FPGA and RAM). Furthermore, persons having ordinary skill in the art would know that communication latencies increase with distance and/or temperature due to physics. Finally, if Karalekas and/or McDermott are found to be unclear regarding the non-quantum mechanical digital circuitry configured to communicate with the one or more processors via at least some of the communication links to provide digital information based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature to the one or more processors, Li also discloses the same (Fig. 1A, ¶40).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, Bouayadi, McDermott, Karalekas, and Li because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing communications between various elements of a quantum computing system for control and measurement of quantum processing elements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum computing system including a quantum computing chip and quantum bit management module in a cryostat. McDermott teaches that the quantum computing system should include additional circuitry located in the cryostat and external to the cryostat. Karalekas, McDermott, and Li teach that the quantum computing chip is connected to the control and measurement circuitry of the management module and circuits in and external to the cryostat using communication links of increasing latencies. The teachings of Karalekas, McDermott, and Li are directly applicable to Mutus in the same way, so that the elements of the Mutus’s quantum computing system can communicate with each other to perform control and measurement of the quantum processor.
Regarding claim 2, Mutus does not appear to explicitly disclose discloses that the electrically conductive bumps are to provide mechanical engagement between the first and second integrated chips and are not electrically connected to a circuit in either the first integrated chip or the second integrated chip; and the quantum computing module and quantum bit management circuit module are coupled to each other to exchange information via conductive or inductive coupling; McDermott discloses these limitations (p. 3, last 3 lines). Motivation to combine remains consistent with claim 1.
Regarding claim 3, Mutus discloses that the electrically conductive bumps are connected so that at least part the electrically conductive bumps form electrical conductive paths between the quantum bit management circuit module and quantum computing module for transfer of part of the control signals and readout signals without using other wiring between the quantum bit management circuit module and quantum computing module (¶35).
Regarding claim 8, Mutus does not appear to explicitly disclose that the quantum bit management circuit module and quantum computing module are structured to include capacitive coupling circuitry to enable capacitive coupling between the quantum bit management circuit module and quantum computing module to provide signaling separate from the electrical conductive paths formed by electrically conductive bumps; McDermott discloses these limitations (p. 3, last 3 lines). Motivation to combine remains consistent with claim 1.
Regarding claim 9, Mutus does not appear to explicitly disclose that the quantum bit management circuit module and quantum computing module are structured to include magnetic coupling circuitry to enable magnetic induction coupling between the quantum bit management circuit module and quantum computing module to provide signaling separate from the electrical conductive paths formed by electrically conductive bumps; McDermott discloses these limitations (p. 3, last 3 lines). Motivation to combine remains consistent with claim 1.
Regarding claim 10, Mutus does not appear to explicitly disclose a flexible non-conductive material on which the electrically conductive wires are formed and separated from one another so that the flexible non-conductive material and the electrically conductive wires form a flexible ribbon that connects at least one of the circuit modules and the quantum bit management circuit module. McDermott discloses these limitations (p. 3, Fig. 1; p. 14, ¶3 flexible Kapton tape). Motivation to combine remains consistent with claim 1.
Regarding claim 11, Mutus does not appear to explicitly disclose that each quantum bit circuit includes a superconducting Josephson junction circuit at the low cryogenic temperature; Falcon discloses these limitations (¶91). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, McDermott, Bouayadi, Karalekas, Li, and Falcon, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of forming quantum processing systems with conventional qubit architectures. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum processing system comprising qubits. Falcon teaches that qubits are Josephson junction circuits. The teachings of Falcon are directly applicable to Mutus in the same way, so that Mutus would similarly use Josephson junction circuits for quantum processing.
Regarding claim 12, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a superconducting switching circuit that is different from a Josephson junction circuit. Li discloses these limitations (¶38). Motivation to combine remains consistent with claim 1.
Regarding claim 13, Mutus discloses that the quantum bit management circuit module includes a Josephson junction circuit (¶35). Li also discloses these limitations (¶¶38-39). Motivation to combine remains consistent with claim 1.
Regarding claim 14, Mutus discloses that the quantum bit management circuit module includes a single flux quantum (SFQ) logic circuit (¶35). Li also discloses these limitations (¶27). Motivation to combine remains consistent with claim 1.
Regarding claim 21, Mutus discloses that the quantum bit management circuit module and the quantum computing module are maintained at the same low cryogenic temperature (¶34). If Mutus is found to be unclear regarding this limitation, McDermott (p. 3, Fig. 1 and last paragraph) and Li (¶27) disclose the same. Motivation to combine remains consistent with claim 1.
Regarding claim 22, Mutus does not appear to explicitly disclose the quantum bit readout circuits supported by the second integrated chip and structured to interact with the plurality of readout resonators supported by the first integrated chip, respectively, to receive the quantum bit circuit readout signals, respectively, and output the readout signals, respectively. Falcon discloses the plurality of readout resonators supported by the first integrated chip (¶104). McDermott discloses the quantum bit readout circuits supported by the second integrated chip and structured to interact with the plurality of readout resonators supported by the first integrated chip, respectively, to receive the quantum bit circuit readout signals, respectively, and output the readout signals, respectively (p. 3, both paragraphs). Motivation to combine remains consistent with claim 1.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Kunkee (US 9,761,547).
Regarding claim 4, Mutus does not appear to explicitly disclose that the electrically conductive bumps include electrically conductive isolation bumps located to form isolation fences to reduce crosstalk between the electrically conductive wires. Falcon discloses these limitations (¶¶103, 104). If Falcon is found to be unclear regarding these limitations, Kunkee also discloses the same (Fig. 5 and related text, especially col. 6, lines 61-64; col. 3, lines 46-51). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, McDermott, Bouayadi, Karalekas, Li, Falcon, and Kunkee, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of optimizing designs by minimizing electromagnetic (EM) interactions between circuit elements, such as transmission lines. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mutus discloses a circuit having conductive bumps. Falcon and Kunkee teach that the bumps should form isolation fences between circuit elements such as transmission lines, in order to reduce EM interactions between those elements. The teachings of Falcon and Kunkee are directly applicable to Mutus in the same way, so that Mutus’s conductive bumps would similarly form isolation fences around circuit elements such as transmission lines, in order to optimize the design by reducing EM interactions between those circuit elements.
Claim(s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Oliver (US 2017/0133336).
Regarding claim 5, Mutus does not appear to explicitly disclose that the quantum computing module includes electrically conductive isolation bumps located to form isolation fences separating the quantum bit circuits to reduce crosstalk therebetween and to decrease decoherence of the quantum bit circuits. Falcon discloses these limitations (¶¶103, 104). If Falcon is found to be unclear regarding these limitations, Oliver also discloses the same (¶¶311, 314). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, McDermott, Bouayadi, Karalekas, Li, Falcon, and Oliver, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the routine substitution of an element with a known alternative, to achieve the predictable results of reducing interactions between circuit elements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mutus discloses a quantum processing chip with bumps, which persons having ordinary skill in the art would recognize naturally act to reduce electromagnetic interference between circuit elements, as taught by Falcon and Oliver. The teachings of Falcon and Oliver are directly applicable to Mutus in the same way, so that Mutus would similarly use the conductive bumps to reduce interactions between circuit elements.
Regarding claim 7, Mutus does not appear to explicitly disclose that the quantum computing module includes electrically conductive isolation walls separating the quantum bit circuits to reduce crosstalk therebetween and to decrease decoherence of the quantum bit circuits. Falcon (¶¶103, 104) and Oliver teach these limitations (¶¶30, 311). Motivation to combine remains consistent with claim 5.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Wilder (US 2020/0395651).
Regarding claim 6, Mutus does not appear to explicitly disclose electrically conductive isolation walls located to form isolation walls separating the electrically conductive wires to reduce crosstalk between the electrically conductive wires. Falcon discloses electrically conductive isolation bumps to reduce crosstalk between the electrically conductive wires (¶¶103, 104), and Wilder discloses electrically conductive isolation walls separating electrically conductive wires to reduce crosstalk between the electrically conductive wires (¶39). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, McDermott, Bouayadi, Karalekas, Li, Falcon, and Wilder, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of reducing interactions between transmission lines. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mutus discloses a circuit having conductive bumps. Falcon teaches isolating transmission lines using the conductive bumps, and Wilder teaches that circuit elements such as transmission lines should be separated by isolation walls to reduce interactions between the elements. The teachings of Falcon and Wilder are directly applicable to Mutus in the same way, so that Mutus would similarly separate circuit elements such as transmission lines using isolation walls, in order to reducing interactions between those circuit elements.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Sank (US 2023/0010205).
Regarding claim 15, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a quantum flux parametron circuit. Sank discloses these limitations (¶124). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Sank, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of determining qubit states. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum circuit including additional circuitry coupled to qubits. McDermott teaches that the additional circuitry includes readout circuitry, and Sank teaches that the readout circuitry includes a quantum flux parametron (QFP) circuit coupled to the qubit to determine the state of the qubit. The teachings of McDermott and Sank are directly applicable to Mutus in the same way, so that Mutus would similarly use a QFP circuit to readout qubit states.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Mukhanov (US 9,520,180).
Regarding claim 16, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a nanowire switch. Mukhanov discloses these limitations (col. 11, lines 57-64). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Mukhanov, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing superconducting circuits to store information. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a superconducting circuit. Mukhanov teaches that the circuit includes a nanowire switch to allow information storage and retrieval. The teachings of Mukhanov are directly applicable to Mutus in the same way, so that Mutus would similarly use a circuit including a nanowire switch for information storage and retrieval.
Regarding claim 17, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a superconducting ferromagnetic transistor. Mukhanov discloses these limitations (col. 21, lines 11-14). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Mukhanov, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing superconducting circuits to store information. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a superconducting circuit. Mukhanov teaches that the circuit includes a superconducting ferromagnetic transistor to allow information storage and retrieval. The teachings of Mukhanov are directly applicable to Mutus in the same way, so that Mutus would similarly use a circuit including a superconducting ferromagnetic transistor for information storage and retrieval.
Regarding claim 18, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a superconducting spintronic device. Mukhanov discloses these limitations (col. 11, lines 27-44). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Mukhanov, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing superconducting circuits to store information. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a superconducting circuit. Mukhanov teaches that the circuit includes a superconducting spintronic device to allow information storage and retrieval. The teachings of Mukhanov are directly applicable to Mutus in the same way, so that Mutus would similarly use a circuit including a superconducting spintronic device for information storage and retrieval.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Yoon (US 11,525,878).
Regarding claim 19, Mutus does not appear to explicitly disclose that the quantum bit management circuit module includes a field-effect superconducting device. Yoon discloses these limitations (col. 1, lines 15-18). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Yoon, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of implementing a circuit with improved cryogenic devices. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a superconducting circuit in a cryostat. Yoon teaches a superconducting field-effect transistor, which is an improved cryogenic circuit element. The teachings of Yoon are directly applicable to Mutus in the same way, so that Mutus’s superconducting circuit would similarly utilize a superconducting field-effect transistor as an improved cryogenic circuit element.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Jones (US 2021/0350270).
Regarding claim 20, Mutus does not appear to explicitly disclose optical transmitter and receiver devices to enable transmission and reception of optical signals between the cryogenic stages situated at the highest temperature of the cryostat system and the room temperature electronics to provide communications therebetween. Jones discloses these limitations (¶¶10, 15). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Jones, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing communication between elements of the quantum processing system. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum processing system including quantum circuit chips. McDermott, Karalekas, and Jones teach that the quantum processing system includes additional processing elements, including at higher temperature stages within a cryostat and at room temperature, which Jones teaches are communicatively coupled using optical transmission lines. The teachings of McDermott, Karalekas, and Jones are directly applicable to Mutus in the same way, so that Mutus would similarly use optical transmission lines to allow communication between different elements of the quantum processing system.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, and Kelly (US 2020/0012961).
Regarding claim 23, Mutus does not appear to explicitly disclose that the quantum bit readout circuits supported by the second integrated chip are structured to include a plurality of readout resonators supported by the second integrated chip and structured to interact with the plurality of quantum bit circuits supported by the first integrated chip, respectively, to produce quantum bit circuit readout signals; and the quantum bit readout circuits supported by the second integrated chip are structured to interact with the plurality of readout resonators, respectively, to receive the quantum bit circuit readout signals, respectively, and output the readout signals, respectively. Kelly teaches that the quantum bit readout circuits supported by the second integrated chip are structured to include a plurality of readout resonators supported by the second integrated chip and structured to interact with the plurality of quantum bit circuits supported by the first integrated chip, respectively, to produce quantum bit circuit readout signals (¶45). McDermott discloses the quantum bit readout circuits supported by the second integrated chip and structured to interact with the plurality of readout resonators supported by the first integrated chip, respectively, to receive the quantum bit circuit readout signals, respectively, and output the readout signals, respectively (p. 3, both paragraphs).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Bouayadi, Karalekas, Li, Jones, and Kelly, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing measurement of qubit states. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses quantum circuit chips and additional chips. McDermott teaches that the additional chip includes readout circuitry that measures qubit states by interacting with a readout resonator, which can be located on the additional chip, as taught by Kelly. The teachings of McDermott and Kelly are directly applicable to Mutus in the same way, so that Mutus would similarly include readout resonators and readout circuitry on the additional chips to allow measurement of qubit state.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mutus, Falcon, McDermott, Karalekas, and Li.
Regarding claim 24, Mutus discloses a method of information processing based at least in part on quantum computing using quantum states of quantum bits (¶33), comprising: operating a quantum computing module comprising a plurality of first integrated chips structured to support a plurality of quantum bit circuits operable to exhibit different quantum states as a quantum-mechanical system and to cause to quantum-mechanically interactions amongst the quantum bit circuits to cause superposition or correlation of different quantum states of the quantum bit circuits (¶¶33, 34, 49).
Mutus does not appear to explicitly disclose the quantum computing module further comprising a plurality of readout resonators supported by the plurality of first integrated chips and structured to interact with the plurality of quantum bit circuits, respectively, to produce quantum bit circuit readout signals. However, these features are known, as admitted by Applicant (Specification ¶55). Falcon also discloses these limitations (¶104). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus and Falcon, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing determination of qubit state. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum system comprising a chip having quantum circuit elements and a chip having non-quantum circuit elements. Falcon discloses that the quantum circuit chip includes readout resonators, which is well-known. The teachings of Falcon are directly applicable to Mutus in the same way, so that Mutus’s quantum chip would include readout resonators to allow determination of qubit state.
Mutus does not appear to explicitly disclose causing quantum bit control circuits to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and operating quantum bit readout circuits to output readout signals from the quantum bit circuits, respectively, the readout signals representing quantum states of the quantum bit circuits, respectively, thermally coupling the quantum bit circuits, the quantum bit control circuits, and quantum bit readout circuits to a common cryogenic stage; coupling the quantum bit circuits, the quantum bit control circuits and quantum bit readout circuits via capacitive coupling or inductive coupling to apply the control signals from the quantum bit control circuits to the quantum bit circuits, respectively; using electrically conductive wires, including at least one flexible superconducting cable comprising electrically conductive cable segments, coupled between a quantum bit management circuit module and one or more circuit modules at one or more higher temperatures than the temperature of the common cryogenic stage coupled to the quantum bit circuits, the quantum bit control circuits, and quantum bit readout circuits to transmit information in connection with operating the quantum bit circuits, the quantum bit control circuits and quantum bit readout circuits using the electrically conductive cable segments, each of the electrically conductive cable segments configured to transmit the information according to different temperature ranges, wherein the quantum bit control circuits and quantum bit readout circuits are structured to include superconducting circuits at a low cryogenic temperature and operable to operate with the control signals and readout signals based on digital processing performed by non-quantum mechanical digital circuitry at the low cryogenic temperature, the non-quantum mechanical digital circuitry configured to communicate with one or more processors at room temperature to provide digital information based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature to the one or more processors, wherein the control signals are generated based in part on qubit readout information from the quantum bit management circuit module operated at the low cryogenic temperature.
McDermott discloses causing quantum bit control circuits to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and operating quantum bit readout circuits to output readout signals from the quantum bit circuits, respectively, the readout signals representing quantum states of the quantum bit circuits, respectively, thermally coupling the quantum bit circuits, the quantum bit control circuits, and quantum bit readout circuits to a common cryogenic stage; coupling the quantum bit circuits, the quantum bit control circuits and quantum bit readout circuits via capacitive coupling or inductive coupling to apply the control signals from the quantum bit control circuits to the quantum bit circuits, respectively; wherein the quantum bit control circuits and quantum bit readout circuits are structured to include superconducting circuits at a low cryogenic temperature and operable to operate with the control signals and readout signals based on digital processing performed by non-quantum mechanical digital circuitry at the low cryogenic temperature, (p. 3, Fig. 1 and last paragraph);
using electrically conductive wires, including at least one flexible superconducting cable comprising electrically conductive cable segments, coupled between a quantum bit management circuit module and one or more circuit modules at one or more higher temperatures than the temperature of the common cryogenic stage coupled to the quantum bit circuits, the quantum bit control circuits, and quantum bit readout circuits to transmit information in connection with operating the quantum bit circuits, the quantum bit control circuits and quantum bit readout circuits using the electrically conductive cable segments, each of the electrically conductive cable segments configured to transmit the information according to different temperature ranges (p. 3, Fig. 1; p. 14, ¶3 flexible Kapton tape);
the non-quantum mechanical digital circuitry configured to communicate with one or more processors at room temperature to provide digital information based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature to the one or more processors, wherein the control signals are generated based in part on qubit readout information from the quantum bit management circuit module operated at the low cryogenic temperature (p. 3, Fig. 1 and last paragraph; p. 11, Fig. 6 and second paragraph, SFQ communicating with room-temperature FPGA and RAM).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, and McDermott, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of reducing wire count, heat load, and latency. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum system comprising a quantum circuit chip bonded to a non-quantum circuit chip. McDermott teaches that the chips are in a low temperature stage in a cryostat and communicate with additional chips in higher temperature stages in the cryostat through superconducting cables, in order to reduce wire count, heat load, and latency. The teachings of McDermott are directly applicable to Mutus in the same way, so that Mutus would similarly implement communicatively-coupled chips in low-temp and high-temp stages of a cryostat in order to reduce wire count, heat load, and latency.
If McDermott is found to be unclear regarding transmitting the information according to different temperature ranges and the non-quantum mechanical digital circuitry configured to communicate with one or more processors at room temperature to provide digital information based on the digital processing by the non-quantum mechanical digital circuitry at the low cryogenic temperature to the one or more processors, Karalekas (Fig. 9, communications links at stage 970 stage having lower latency than those at stage 960, which in turn have lower latency that those at stages 910-950; ¶¶16, 17, 76, 104, 105) and Li (Fig. 1A, ¶40) also disclose these limitations. Furthermore, persons having ordinary skill in the art would know that communication latencies increase with distance and/or temperature due to physics.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mutus, Falcon, McDermott, Karalekas, and Li because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing communications between various elements of a quantum computing system. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mutus discloses a quantum computing system including a quantum computing chip and quantum bit management module in a cryostat. McDermott teaches that the quantum computing system should include additional circuitry located in the cryostat and external to the cryostat. Karalekas, McDermott, and Li teach that the quantum computing chip is connected to the management module and circuits in and external to the cryostat using communication links of increasing latencies. The teachings of Karalekas, McDermott, and Li are directly applicable to Mutus in the same way, so that the elements of the Mutus’s quantum computing system can communicate with each other.
Response to Arguments
Applicant's arguments filed 1 April 2026 have been fully considered but they are not persuasive.
New limitations are addressed above in the new grounds of rejection, and are not further addressed here.
Applicant asserts that combination of Kelly teaches away from the first plurality of first integrated chips supporting the plurality of quantum bit circuits and the plurality of readout resonators. Remarks 10. The examiner disagrees. The disclosure of a more-preferred embodiment does not constitute ‘teaching away’. Here, Kelly states at ¶39 that “to further relax the layout constraints, the qubit readout elements also may be moved to the same chip on which the wiring and lossy materials are formed” (emphasis added). Kelly does not require that the readout elements be located on the second chip, or otherwise indicate that keeping the readout elements on the same chip would render the device inoperable or unsuited for its intended purpose. Rather, moving the readout resonator to the second chip may have some advantages over the known embodiment where the resonator is on the first chip. See In re Urbanski, 117 USPQ2d 1499, 1504 and Allied Erecting v. Genesis Attachments, 119 USPQ2d 1132, 1138, where preferred embodiments that achieved advantages through features conflicting with the proposed combination were nevertheless found not to ‘teach away’ from the proposed combination.
Furthermore, locating the readout resonator on the same chip as the qubits is conventional (which Kelly is suggesting an improvement over), as Applicant clearly knows (see Specification ¶55). The location of the readout resonator is also clearly not considered a distinguishing feature, since Applicant discloses the readout resonator being on either the first or second chip, and treats them equally as alternatives. Thus, such a feature is not an advancement over the prior art and could not be the basis for allowability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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18 June 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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