DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 10/22/2025.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Grochowski et al. (U.S. 5,416,913), in view of Shippy (U.S. 2014/0173312), in view of Lin (U.S. 2016/0210154).
As per claim 1:
Grochowski, Shippy, and Lin disclosed a processing device comprising:
an instruction fetch unit (Grochowski: Figure 2, column 3 lines 37-42);
a first execution pipeline (Shippy: Figure 5 elements 520 and 536, paragraphs 36-38)(Grochowski: Figure 3 element 12, column 4 lines 50-60)(Shippy disclosed different types of instructions with different numbers of execution stages. The combination allows for the decoded microcode output to control the functionality of the execution stages. The decode stages of the u-pipe decoder and corresponding decoded microcode output to the execution stage(s) reads upon the first execution pipeline.) including:
a first decode unit coupled to the instruction fetch unit (Grochowski: Figure 3 element 12, column 4 lines 50-56);
a first execution control unit coupled to the first decode unit (Grochowski: Figure 3 element 12, column 4 lines 50-60)(The decoded microcode output reads upon the first execution control unit.), and having a plurality of execution stages (Shippy: Figure 5 element 536, paragraphs 36-38)(Grochowski: Figure 3 element 12, column 4 lines 50-60)(Shippy disclosed different types of instructions with different numbers of execution stages. The combination allows for the decoded microcode output to control the functionality of the execution stages.);
a second execution pipeline (Shippy: Figure 5 elements 520 and 536, paragraphs 36-38)(Grochowski: Figure 3 element 14, column 4 lines 50-60)(Shippy disclosed different types of instructions with different numbers of execution stages. The combination allows for the decoded microcode output to control the functionality of the execution stages. The decode stages of the v-pipe decoder and corresponding decoded microcode output to the execution stage reads upon the second execution pipeline.) including:
a second decode unit coupled to the instruction fetch unit (Grochowski: Figure 3 element 14, column 4 lines 50-56);
a second execution control unit coupled to the second decode unit (Grochowski: Figure 3 element 14, column 4 lines 50-60)(The decoded microcode output reads upon the second execution control unit.); and
a dependency circuit coupled to the first decode unit and the second decode unit, the dependency circuit configured to identify data dependencies between instructions (Grochowski: Figures 3-4 elements 12, 14, and 19, column 4 lines 3-7, column 4 lines 50-56, column 5 lines 20-24, and column 7 lines 11-30)(The dependency logic identifies data dependencies between instructions.);
a set of execution units coupled to the first execution control unit and the second execution control unit (Grochowski: Figure 2, column 3 lines 49-64) wherein:
the first execution pipeline is configured to use the set of execution units to execute any instruction of a first instruction set in the execution stages, the first instruction set including all single and multi-cycle instructions executable by the processing device (Shippy: Figure 5 element 536, paragraphs 36-38)(Grochowski: Figures 2-3 element 12, column 3 lines 18-27 column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14)(Grochowski disclosed the U-Pipe decoder and output microcode controls execution for all types of instructions in the instruction set. Grochowski disclosed single-cycle instruction execution. Shippy disclosed a combined single and multi-cycle instruction execution. The combination allows for the decoded microcode output to control the functionality of the execution stages. The execution stages connected to the U-Pipe decoder can execute all processor instructions, including all single and multiple execution stage instructions.); and
the second execution pipeline is configured to:
use the set of execution units to execute any single-cycle instruction of a second instruction set, in parallel with execution of any instruction of the first instruction set by the first execution pipeline, in which the second instruction set is a subset of the first instruction set such that a remainder of the first instruction set is not in the second instruction set (Shippy: Figure 5 element 536, paragraphs 36-38)(Grochowski: Figures 2-3 element 14, column 3 lines 18-27, column 3 lines 49-64, column 4 lines 3-27, column 4 lines 50-60, and column 5 lines 7-14)(Shippy disclosed a combined single and multi-cycle instruction execution. The combination allows for the decoded microcode output to control the functionality of the execution stages. The V-Pipe decoder and output microcode controls execution for a subset of types of instructions in the instruction set. The execution stages connected to the V-Pipe decoder execute a subset of the single-cycle instructions. Instruction pairs that are decoded by the U-Pipe and V-Pipe decoders that aren’t dependent are executed in parallel.); and
execute sequential instructions provided by the instruction fetch unit responsive to a dependency between the sequential instructions identified by the dependency circuit, and the sequential instructions being in the subset of the first instruction set (Lin: Figure 12, paragraph 202)(Shippy: Figure 5 elements 534-536, paragraphs 36-38)(Grochowski: Figures 2-3 element 14, column 3 lines 18-27, column 3 lines 49-64, column 4 lines 3-27, column 4 lines 50-60, and column 5 lines 7-14)(Lin disclosed a dependency checker to determine if two instructions can or cannot be executed in parallel. Shippy disclosed parallel integer units, coupled to parallel queues and issue units. Grochowski disclosed a subset V-pipe decoder to execute a subset of the single-cycle instructions. The combination allows for performing a dependency check in Grochowski to selectively issue queued instructions to the pair of integer execution units. If the dependency checker detects a dependency, then “these two instructions cannot be executed in parallel.” Instead, they are executed sequentially.).
The advantage of implementing multiple execution state pipelines is that longer instructions can be implemented within a faster clocked processor, which increases performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the multiple stage execution units of Shippy into the processor of Grochowski for the above reason.
The advantage of implementing dependency checking is that instructions can be issued out-of-order and in parallel to execution units when dependencies don’t occur, which increases processor throughput. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the dependency checking of Lin for the above advantage.
As per claim 2:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1 further comprising a register file coupled to the set of execution units (Grochowski: Figure 2, column 5 lines 56-59), wherein each instruction in the second instruction set utilizes a register operand mode, an immediate addressing mode, or a combination thereof (Grochowski: Table 1)(The v-pipe instructions use registers.).
As per claim 3:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein the second instruction set includes only reduced instruction set computer (RISC) instructions and the remainder of the first instruction set includes complex instruction set computer (CISC) instructions (Grochowski: Figure 2, column 3 lines 49-64)(The instructions executed during the execution stage take a single cycle for execution. Official notice is given that RISC instructions can take a single clock cycle for execution and that CISC instructions can be implemented within instruction sets for the advantage of executing more complex operations. Thus, it would have been obvious to one of ordinary skill in the art to implement the V-Pipe instructions as RISC operations and the remaining U-pipe instructions as CISC operations.).
As per claim 4:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein the second instruction set includes only instructions that can be executed in one clock cycle (Grochowski: Figure 2, column 3 lines 49-67) and the remainder of the first instruction set includes instructions that are executed in more than one clock cycle (Grochowski: Figure 2, column 3 lines 49-64)(Official notice is given that CISC instructions taking multiple clock cycles can be implemented within instruction sets for the advantage of executing more complex operations. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple clock cycle CISC operations within the U-pipe.).
As per claim 5:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein:
the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units (Grochowski: Figure 2, column 3 lines 49-67, table 1)(Grochowski disclosed ALU operations executable by execution stages for both the U and V pipes. Official notice is given that load/store, multiplier, and floating-point units can be implemented for the advantage of increased functionality. Thus, it would have been obvious to implement these execution units within Grochowski.);
the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit (Grochowski: Figure 2, column 3 lines 49-67, table 1);
the first execution control unit is configured to control the remainder of the set of execution units (Grochowski: Figure 2, column 3 lines 49-67, table 1)(In view of the above official notice, these added execution units and corresponding instructions are only implemented in the U-pipe.); and
the second execution control unit is not configured to control the remainder of the set of execution units (Grochowski: Figure 2, column 3 lines 49-67, table 1)(In view of the above official notice, these added execution units and corresponding instructions are only implemented in the U-pipe.).
As per claim 6:
Grochowski, Shippy, and Lin disclosed the processing device of claim 5, wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit (Grochowski: Figure 2, column 3 lines 49-67, table 1)(Grochowski disclosed ALU operations executable by execution stages for both the U and V pipes. Official notice is given that load/store, multiplier, and floating-point units can be implemented for the advantage of increased functionality. Thus, it would have been obvious to implement these execution units within Grochowski.).
As per claim 7:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein:
the first execution control unit is configured to cause the set of execution units to execute an instruction of the first instruction set in a first number of pipeline stages (Grochowski: Figure 2, column 3 lines 49-64)(Official notice is given that CISC instructions taking multiple clock cycles can be implemented within instruction sets for the advantage of executing more complex operations. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple clock cycle CISC operations within the U-pipe.); and
the second execution control unit is configured to cause the set of execution units to execute an instruction of the second instruction set in a second number of pipeline stages that is less than the first number of pipeline stages (Grochowski: Figure 2, column 3 lines 49-67).
As per claim 8:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein: the instruction fetch unit is configured to receive a first instruction (Grochowski: Figure 2, column 3 lines 37-42) and provide the first instruction to either the first execution control unit or the second execution control unit based on whether the first instruction is in the second instruction set (Grochowski: Figure 3 elements 12 and 14, column 5 lines 7-14)(For paired instructions, the first instruction is sent to the U-pipe decoder and the second instruction is sent to the V-pipe decoder.).
As per claim 9:
Grochowski, Shippy, and Lin disclosed the processing device of claim 1, wherein the first decode unit and the second decode unit are coupled to operate in parallel (Grochowski: Figures 2-3 elements 12 and 14, column 3 lines 49-53 and column 4 lines 50-56).
As per claim 10:
Grochowski, Shippy, and Lin disclosed the processing device of claim 8, wherein the first execution control unit is configured to cause the set of execution units to execute a first instruction and the second execution control unit is configured to cause the set of execution units to execute a second instruction in parallel with the first instruction (Grochowski: Figures 2-3 elements 12 and 14, column 3 lines 49-64, column 4 lines 50-56, and column 5 lines 7-14)(The decoded first instruction microcode and second instruction microcode allows for parallel execution of a pair of instructions during the execute stage.)
As per claim 11:
Grochowski, Shippy, and Lin disclosed a processing device comprising:
a first decode unit (Grochowski: Figure 3 element 12, column 4 lines 50-56);
a second decode unit coupled in parallel with the first decode unit (Grochowski: Figure 3 element 14, column 4 lines 50-56);
a dependency circuit coupled to the first decode unit and the second decode unit, the dependency circuit configured to identify data dependencies between instructions (Grochowski: Figures 3-4 elements 12, 14, and 19, column 4 lines 3-7, column 4 lines 50-56, column 5 lines 20-24, and column 7 lines 11-30)(The dependency logic identifies data dependencies between instructions.);
a first execution control unit coupled to the first decode unit (Grochowski: Figure 3 element 12, column 4 lines 50-60)(The decoded microcode output reads upon the first execution control unit.), and having a plurality of execution stages (Shippy: Figure 5 element 536, paragraphs 36-38)(Grochowski: Figure 3 element 12, column 4 lines 50-60)(Shippy disclosed different types of instructions with different numbers of execution stages. The combination allows for the decoded microcode output to control the functionality of the execution stages.);
a second execution control unit coupled to the second decode unit (Grochowski: Figure 3 element 14, column 4 lines 50-60)(The decoded microcode output reads upon the second execution control unit.), and having a single execution stage that is exclusive of the execution stages of the first execution control unit (Shippy: Figure 5 element 536, paragraphs 36-38)(Grochowski: Figure 3 element 12, column 4 lines 50-60)(The combination allows for the decoded microcode output to control the functionality of the execution stages. The control for the single-stage integer execution units is separate from the control for the multi-stage execution units.); and
a set of execution units coupled to the first execution control unit and the second execution control unit (Grochowski: Figure 2, column 3 lines 49-64) wherein:
the first decode unit and the first execution control unit are configured to cause the set of execution units to execute in the execution stages a first instruction having a first addressing mode and a second instruction having a second addressing mode that is different from the first addressing mode (Shippy: Figure 5 elements 536 and 548-550, paragraphs 36-38)(Grochowski: Figures 2-3 element 12, column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14, table 1)(Shippy disclosed load/store instructions. The U-Pipe decoder and output microcode controls execution for all types of instructions in the instruction set. The combination allows for the decoded microcode output to control the functionality of the execution stages. The U-pipe and V-pipe instructions include instructions referencing operands. The combination allows for load/store instructions to be included in the U-Pipe decoder. Official notice is given that load/store instructions can include memory offset addressing for the advantage of allowing programmers to provide memory access instructions that access offset values within data structures in memory. Thus, it would have been obvious to one of ordinary skill in the art to implement load/store instructions with memory offset addressing in the U-pipe.); and
the second decode unit and the second execution control unit are configured to:
cause the set of execution units to execute the first instruction having the first addressing mode and not configured to cause the set of execution units to execute the second instruction having the second addressing mode (Grochowski: Figures 2-3 element 14, column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14, table 1)(The V-Pipe decoder and output microcode controls execution for a subset of types of instructions in the instruction set. The U-pipe and V-pipe instructions include instructions referencing operands. In view of the above official notice, the V-pipe doesn’t include the added load/store instructions.); and
execute the sequential instructions responsive to the dependency circuit identifying a data dependency between the sequential instructions (Lin: Figure 12, paragraph 202)(Shippy: Figure 5 elements 534-536, paragraphs 36-38)(Grochowski: Figures 2-3 element 14, column 3 lines 18-27, column 3 lines 49-64, column 4 lines 3-27, column 4 lines 50-60, and column 5 lines 7-14)(Lin disclosed a dependency checker to determine if two instructions can or cannot be executed in parallel. Shippy disclosed parallel integer units, coupled to parallel queues and issue units. Grochowski disclosed a subset V-pipe decoder to execute a subset of the single-cycle instructions. The combination allows for performing a dependency check in Grochowski to selectively issue queued instructions to the pair of integer execution units. If the dependency checker detects a dependency, then “these two instructions cannot be executed in parallel.” Instead, they are executed sequentially.).
The advantage of implementing multiple execution state pipelines is that longer instructions can be implemented within a faster clocked processor, which increases performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the multiple stage execution units of Shippy into the processor of Grochowski for the above reason.
The advantage of implementing dependency checking is that instructions can be issued out-of-order and in parallel to execution units when dependencies don’t occur, which increases processor throughput. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the dependency checking of Lin for the above advantage.
As per claim 12:
Grochowski, Shippy, and Lin disclosed the processing device of claim 11, wherein the first addressing mode includes at least one of a register operand mode or an immediate addressing mode (Grochowski: Figures 2-3 element 12, column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14, table 1)(The U-Pipe decoder and output microcode controls execution for all types of instructions in the instruction set. The U-pipe and V-pipe instructions include instructions referencing operands. In view of the above official notice, the U-pipe includes the added immediate value instructions).
As per claim 13:
Grochowski, Shippy, and Lin disclosed the processing device of claim 11, wherein the first instruction utilizes only a register operand mode, an immediate addressing mode, or a combination thereof (Grochowski: Figures 2-3 element 12, column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14, table 1)(The U-Pipe decoder and output microcode controls execution for all types of instructions in the instruction set. The U-pipe and V-pipe instructions include instructions referencing operands. In view of the above official notice, the U-pipe includes the added immediate value instructions).
As per claim 14:
Grochowski, Shippy, and Lin disclosed the processing device of claim 11, wherein the second addressing mode is not a register operand mode or an immediate addressing mode (Grochowski: Figures 2-3 element 14, column 3 lines 49-64, column 4 lines 50-60, and column 5 lines 7-14, table 1)(The V-Pipe decoder and output microcode controls execution for a subset of types of instructions in the instruction set. Official notice is given that register indirect instructions can be implemented in the V-pipe for the advantage of allowing memory accesses to data structures. Thus, it would have been obvious to one of ordinary skill in the art to implement such instructions in the V-pipe.).
As per claim 15:
Grochowski, Shippy, and Lin disclosed the processing device of claim 11, wherein:
the first execution control unit includes a first number of execution stage circuits (Grochowski: Figure 2, column 3 lines 49-64)(Official notice is given that CISC instructions taking multiple clock cycles can be implemented within instruction sets for the advantage of executing more complex operations. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple clock cycle CISC operations within the U-pipe.); and
the second execution control unit includes a second number of execution stage circuits that is less than the first number of execution stage circuits (Grochowski: Figure 2, column 3 lines 49-67).
As per claim 16:
Grochowski, Shippy, and Lin disclosed the processing device of claim 15, wherein:
the second decode unit and the second execution control unit are configured to cause the set of execution units to execute the first instruction in a single clock cycle (Grochowski: Figure 2, column 3 lines 49-67); and
the first decode unit and the first execution control unit are configured to cause the set of execution units to execute the second instruction in more than one clock cycle (Grochowski: Figure 2, column 3 lines 49-64)(Official notice is given that CISC instructions taking multiple clock cycles can be implemented within instruction sets for the advantage of executing more complex operations. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple clock cycle CISC operations within the U-pipe.).
As per claim 17:
Grochowski, Shippy, and Lin disclosed the processing device of claim 13, wherein:
the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units (Grochowski: Figure 2, column 3 lines 49-67, table 1)(Grochowski disclosed ALU operations executable by execution stages for both the U and V pipes. Official notice is given that load/store, multiplier, and floating-point units can be implemented for the advantage of increased functionality. Thus, it would have been obvious to implement these execution units within Grochowski.);
the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit (Grochowski: Figure 2, column 3 lines 49-67, table 1); and
the first execution control unit but not the second execution control unit is configured to control the remainder of the set of execution units (Grochowski: Figure 2, column 3 lines 49-67, table 1)(In view of the above official notice, these added execution units and corresponding instructions are only implemented in the U-pipe.).
As per claim 18:
Grochowski, Shippy, and Lin disclosed the processing device of claim 17, wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit (Grochowski: Figure 2, column 3 lines 49-67, table 1)(Grochowski disclosed ALU operations executable by execution stages for both the U and V pipes. Official notice is given that load/store, multiplier, and floating-point units can be implemented for the advantage of increased functionality. Thus, it would have been obvious to implement these execution units within Grochowski.).
As per claim 19:
Grochowski, Shippy, and Lin disclosed the processing device of claim 11 further comprising an instruction fetch unit, wherein the first decode unit and the second decode unit are coupled to the instruction fetch unit in parallel (Grochowski: Figures 2-3 elements 12 and 14, column 3 lines 49-53 and column 4 lines 50-56).
As per claim 20:
Grochowski, Shippy, and Lin disclosed the processing device of claim 19, wherein the first execution control unit and the second execution control unit are configured to cause the set of execution units to execute instructions in parallel (Grochowski: Figures 2-3 elements 12 and 14, column 3 lines 49-64, column 4 lines 50-56, and column 5 lines 7-14)(The decoded first instruction microcode and second instruction microcode allows for parallel execution of a pair of instructions during the execute stage.).
Response to Arguments
The arguments presented by Applicant in the response, received on 10/22/2025 are considered persuasive.
Applicant argues for claims 1 and 11:
“It appears the Office Action attempts to correct this deficiency of Grochowski and Shippy by Official Notice that "dependency checking can be performed between all decoded instructions for the advantage of ensuring correct execution order and allowing more parallelized execution." Office Action, p. 6. The Office Action fails to explain why such dependency checking is needed or useful. Grochowski teaches checking dependency of instruction pairs, and further dependency checking provides no advantage because no dependencies beyond those already detected by Grochowski affect execution. For this reason, Applicant respectfully traverses the Examiner's taking of Official Notice that "dependency checking can be performed between all decoded instructions for the advantage of ensuring correct execution order and allowing more parallelized execution" when no dependencies relevant to Grochowski are present beyond those already detected by Grochowski. Applicant specifically denies that this was well known in the art at the time of the invention because such additional dependency checking serves no purpose. Applicant therefore respectfully requests that the Examiner provide documentary evidence supporting the assertion or withdraw the Official Notice.”
This argument is found to be persuasive for the following reason. Due to applicant’s traversal and request for providing documentary evidence supporting the official notice, a new reference has been used in the rejection that has replaced the previous official notice.
The advantage of performing the dependency checking in Lin is that it allows for parallel single-cycle integer execution using the two integer execution units of Shippy. However, the combination allows for single cycle instruction dependencies that prevents parallel execution of single-cycle instructions and forces sequential execution. Thus, reading upon the claimed limitation at issue.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183