Prosecution Insights
Last updated: April 19, 2026
Application No. 17/506,135

DISPLAY TRANSFERRING STRUCTURE AND DISPLAY DEVICE INCLUDING THE SAME

Final Rejection §103
Filed
Oct 20, 2021
Examiner
HSIEH, HSIN YI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
4 (Final)
51%
Grant Probability
Moderate
5-6
OA Rounds
3y 10m
To Grant
57%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allow Rate
321 granted / 631 resolved
-17.1% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
57 currently pending
Career history
688
Total Applications
across all art units

Statute-Specific Performance

§103
39.3%
-0.7% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
35.3%
-4.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 631 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions A typo was found in the Office Action mailed on 10/18/2024: the elected species for Category II should be Species I as stated in the Applicant’s reply filed on 7/3/2024, and not Species II as stated in the Office Action. Thus, the typo is corrected here. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (WO 2019192041 A1, please see the machine translation attached in the office action mailed on 10/18/2024). Regarding claim 1, Zhang et al. teach a display transferring apparatus (LED display screen, the variation of the embodiment of Fig. 2 modified to have 3 columns of protrusions of 40 instead of two columns of protrusions of 40 in the gap between the horizontally placed semiconductor chip 20 in Fig. 2 as disclosed in [0038], please see the modified Fig. 2 below) comprising: a transferring substrate (10/30; Fig. 1, [0033]) comprising a mold (30; Fig. 1, [0033]) including a plurality of recesses (recesses of 30 to accommodate the chip 20; Fig. 1, [0034]), and a plurality of protrusions (40; Fig. 1, [0037]) provided on an outer surface (the top surface) of the mold (30), the outer surface (the top surface of 30) being connected to the plurality of recesses (recesses of 30 to accommodate the chip 20); and a plurality of semiconductor chips (20) respectively provided in the plurality of recesses (recesses of 30 to accommodate the chip 20), wherein the plurality of recesses comprise a first recess (the left recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below) and a second recess (the right recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below) nearest to the first recess (the left recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below) in a first direction (horizontal direction in the modified Fig. 2 below), wherein the plurality of protrusions (40) comprise a first protrusion (the bottommost left one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), a second protrusion (the bottommost middle one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), and a third protrusion (the bottommost right one of the nine 40s between the two recesses of 30; see modified Fig. 2 below) arranged in a row (see modified Fig. 2 below) between the first recess (the left recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below) and the second recess (the right recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below) in the following order: the first recess (the left recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below), the first protrusion (the bottommost left one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), the second protrusion (the bottommost middle one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), the third protrusion (the bottommost right one of the nine 40s between the two recesses of 30; see modified Fig. 2 below) and the second recess (the right recesses of 30 to accommodate the chip 20 in the modified Fig. 2 below), wherein s, which defines a space between the first protrusion (the bottommost left one of the nine 40s between the two recesses of 30; see modified Fig. 2 below) and the second protrusion (the bottommost middle one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), and a space between the second protrusion (the bottommost middle one of the nine 40s between the two recesses of 30; see modified Fig. 2 below) and the third protrusion (the bottommost right one of the nine 40s between the two recesses of 30; see modified Fig. 2 below), satisfies a condition: s ≤ (w1-w2)/2, wherein, w1 is a width of each of the plurality of semiconductor chips (the horizontal width of 20s in Fig. 2) and w2 is a width of each of the plurality of protrusions (the diameter of 40s; s ≤ (w1-w2)/2 is the same as 2 * s + w2 ≤ w1, i.e. the length of two times the space between the adjacent protrusions plus a dimeter of one protrusion is less than a width of the chip 20, and the modified Fig. 2 below clearly shows the length of the two times the space between the adjacent protrusions plus the diameter of a protrusion is less than the horizonal width w1 of 20). Zhang et al. do not teach semiconductor chips are micro semiconductor chips. Parameters such as the size of the semiconductor chips in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the actual need ([0033]) such as the desired performance and size in leisure squares, commercial streets, hospitals, railway stations, concerts, and other places ([0002]) during device fabrication. Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the size of the semiconductor chips within the micro range as claimed in order to achieve the desired performance and size ([0033, 0002]). PNG media_image1.png 104 99 media_image1.png Greyscale PNG media_image2.png 99 87 media_image2.png Greyscale [AltContent: textbox (First protrusion)][AltContent: textbox (Second protrusion)][AltContent: textbox (Third protrusion)][AltContent: textbox (40)][AltContent: textbox (20)][AltContent: textbox (30)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (w1)][AltContent: textbox (2 * s + w2)][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: arrow] Modified Fig. 2 of Zhang showing the variation of the embodiment of Fig. 2 modified to have 3 columns of protrusions of 40 instead of two columns of protrusions of 40 in the gap between the horizontally placed semiconductor chip 20 in Fig. 2 as disclosed in [0038]. Regarding claim 2, Zhang et al. teach the display transferring apparatus of claim 1, wherein the width of each of the plurality of protrusions (the diameter of 40s) is less than the width of each of the plurality of micro semiconductor chips (the horizontal width width of 20s in Fig. 2; see the modified Fig. 2). Regarding claim 5, Zhang et al. teach the display transferring apparatus of claim 1, wherein the plurality of protrusions (40) comprise a different material (a material for 3D printing or silk-screen printing; [0047]) from a material of the mold (30 of a hot melt adhesive for low temperature and low pressure injection; [0046]). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. as applied to claim 5 above, and further in view of Vockenberger (US 2019/0393117 A1). Regarding claim 6, Zhang et al. teach wherein the plurality of protrusions (40). Zhang et al. do not teach the plurality of protrusions comprise a metal material. In the same field of endeavor of 3D printing, Vockenberger teaches the plurality of protrusions (111; Fig. 1, [0063]) comprise a metal material (copper; [0063]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Zhang et al. and Vockenberger, and to use the metal for the protrusion as taught by Vockenberger, because Zhang et al. teach using a material for 3D printing to create the protrusions ([0037]), but is silent about the actual material, and Vockenberger teaches that metal can be used to form protrusions made by 3D printing ([0066] of Vockenberger). Response to Arguments Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fu et al. (CN 110265424 A) teach a display panel having grooves to contain the micro light emitting diodes. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra V Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HSIN YI HSIEH/Primary Examiner, Art Unit 2899 1/29/2026
Read full office action

Prosecution Timeline

Oct 20, 2021
Application Filed
Feb 21, 2024
Response Filed
Jul 03, 2024
Response Filed
Oct 14, 2024
Non-Final Rejection — §103
Jan 06, 2025
Interview Requested
Jan 15, 2025
Applicant Interview (Telephonic)
Jan 15, 2025
Examiner Interview Summary
Jan 21, 2025
Response Filed
Apr 13, 2025
Final Rejection — §103
Jun 09, 2025
Response after Non-Final Action
Jul 17, 2025
Request for Continued Examination
Jul 19, 2025
Response after Non-Final Action
Jul 25, 2025
Non-Final Rejection — §103
Oct 07, 2025
Interview Requested
Oct 20, 2025
Applicant Interview (Telephonic)
Oct 20, 2025
Examiner Interview Summary
Oct 29, 2025
Response Filed
Jan 29, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598786
FIELD EFFECT TRANSISTOR STRUCTURES
2y 5m to grant Granted Apr 07, 2026
Patent 12575243
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 10, 2026
Patent 12550486
OPTOELECTRONIC DEVICE WITH AXIAL THREE-DIMENSIONAL LIGHT-EMITTING DIODES
2y 5m to grant Granted Feb 10, 2026
Patent 12538616
LIGHT EMITTING DIODE WITH OPTIMISED ELECTRIC INJECTION FROM A SIDE ELECTRODE
2y 5m to grant Granted Jan 27, 2026
Patent 12538617
3D LIGHT-EMITTING DIODE AND ASSOCIATED MANUFACTURING METHOD
2y 5m to grant Granted Jan 27, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
51%
Grant Probability
57%
With Interview (+6.2%)
3y 10m
Median Time to Grant
High
PTA Risk
Based on 631 resolved cases by this examiner. Grant probability derived from career allow rate.

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