DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
Claims 17 and 19-20 have been withdrawn. Applicant is reminded to cancel withdrawn claims in their response to this action.
Response to Amendment
The RCE with amendments filed 05 November, 2025 have been entered. Claims 1-4, 8-17, 19-20, and 23-26 remain pending in the application. Claims 17 and 19-20 have been withdrawn by Applicant. Claims 18 and 21-22 have been canceled.
Response to Arguments
Claim Rejection Under 35 U.S.C. § 103
Applicant’s arguments, see Remarks pg. 4-9, filed 11/05/2025, with respect to the rejections of claims 1-4, 8-16, and 21-13 under 35 U.S.C. § 103 have been fully considered and are persuasive as it pertains to the amended claim limitations. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Elkin, further in view of Lin. See the claim rejections below for details.
Applicant argues that cited reference Elkin teaches away from the claimed symmetric layout. Specifically, Applicant cites Figs. 11-12 and ¶ [0053], [0055].
This argument is not persuasive. While portions of Elkin’s disclosure may teach specific embodiments and recite alleged benefits or advantages of said embodiments, one of ordinary skill in the art would consider of plurality of design factors when solving a particular problem. Elkin’s priority of reducing transistor count does not preclude other design considerations, such as reducing circuit sensitivity to process variations or minimizing parasitic mismatch (Lin, I. Introduction, ¶ 1). Furthermore, the new grounds of rejection do not make reference to the portions of Elkin cited by Applicant.
Additionally, Examiner notes that the application disclosure does not provide a particular definition of symmetry or symmetrical, and therefore these terms are interpreted herein by the Examiner to be defined as having “balanced proportions” (“Symmetry”, Merriam-Webster).
Claim Objections
Claim 14 is objected to because of the following informalities:
In Claim 14, line 8, the phrase “a second third OR operation” should read either “a second OR operation” or “a third OR operation”
In Claim 14, line 11, the phrase “the second third OR operation” should read either “the second OR operation” or “the third OR operation”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-16, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Elkin et al. (US 20210124559 A1), hereinafter Elkin, in view of Lin et al. (“Analog Placement Based on Symmetry-Island Formulation”, 2009), hereinafter Lin.
The rejections of claims 1-4, 8-9, and 24 make reference to the following figure, which is an annotated version of Elkin Fig. 8, hereinafter referred to as annotated Fig. 8A.
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Regarding claim 1, Elkin teaches an integrated circuit comprising:
a first adder integrated circuit (Elkin, annotated Fig. 8A, 802); and
a second adder integrated circuit (Elkin, annotated Fig. 8A, 806),
wherein the first adder integrated circuit comprises:
a first logic gate group (Elkin, annotated Fig. 8A, 104) that outputs a first internal signal and a second internal signal (Elkin, annotated Fig. 8A, 105 and 106 respectively) based on a first input signal and a second input signal (Elkin, annotated Fig. 8A, 101 and 102 respectively);
a second logic gate group (Elkin, annotated Fig. 8A, 107) that outputs a first sum signal (Elkin, annotated Fig. 8A, 108) based on the second internal signal and a third input signal (Elkin, annotated Fig. 8A, 103); and
a third logic gate group (Elkin, annotated Fig. 8A, 109) that outputs a first carry signal (Elkin, annotated Fig. 8A, 110) based on the first internal signal, the second internal signal, and the third input signal,
wherein the second adder integrated circuit comprises:
a fourth logic gate group (Elkin, annotated Fig. 8A, 114) that outputs a third internal signal and a fourth internal signal (Elkin, annotated Fig. 8A, 115 and 116 respectively) based on a fourth input signal and a fifth input signal (Elkin, annotated Fig. 8A, 111 and 112 respectively);
a fifth logic gate group (Elkin, annotated Fig. 8A, 117) that outputs a second sum signal (Elkin, annotated Fig. 8A, 118) based on the fourth internal signal and a sixth input signal (Elkin, annotated Fig. 8A, 113); and
a sixth logic gate group (Elkin, annotated Fig. 8A, 119) that outputs a second carry signal (Elkin, annotated Fig. 8A, 120) based on the third internal signal, the fourth internal signal, and the sixth input signal,
wherein, in a layout of the integrated circuit, logic gates of the first logic gate group are housed in a first block group (Elkin, annotated Fig. 8A, 114), logic gates of the second logic gate group and the third logic gate group are housed in a second block group (Elkin, annotated Fig. 8A, 121), logic gates of the fourth logic gate group are housed in a third block group (Elkin, annotated Fig. 8A, 114), and logic gates of the fifth logic gate group and the sixth logic gate group are housed in a fourth block group (Elkin, annotated Fig. 8A, 122), and…
Elkin does not explicitly teach:
wherein the first adder integrated circuit and the second adder integrated circuit are arranged adjacent to each other in the layout to have a symmetrical structure, in which the second block group is adjacent to the fourth block group.
However, Lin teaches the common and advantageous practice of arranging pairs of analog circuit modules in a layout to have a symmetrical placement and arranged as close to each other as possible (Lin, I. Introduction, ¶ 1 and Fig. 1).
Lin is considered to be analogous to the claimed invention because it is in the same field of analog circuit layout design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to layout the first and second adder circuits as taught by Elkin in an adjacent and symmetrical arrangement as taught by Lin. This modification would have been obvious because symmetrical placement reduces the effects of parasitic mismatch and reduces sensitivity to process variation, and furthermore placing symmetrical modules in closest proximity provides better parasitic matching and other electrical properties (Lin, I. Introduction, ¶ 1).
Regarding claim 2, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 1 above. Elkin further teaches wherein the first logic gate group comprises:
a first negative AND (NAND) gate (Elkin, annotated Fig. 8A, 201) that outputs the first internal signal by performing a NAND operation on the first input signal and the second input signal; and
a first OR-AND-Inverter (OAI) gate (Elkin, annotated Fig. 8A, 506 comprising 203 and 204) that outputs, as the second internal signal, a result of performing an exclusive negative OR (XNOR) operation on the first input signal and the second input signal based on the first internal signal, the first input signal, and the second input signal.
Regarding claim 3, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 2 above. Elkin further teaches wherein the first OAI gate comprises:
a first OR gate (Elkin, annotated Fig. 8A, 204) that outputs a result of performing a first OR operation on the first input signal and the second input signal; and
a second NAND gate (Elkin, annotated Fig. 8A, 203) that outputs the second internal signal by performing a NAND operation on the result of performing the first OR operation and the first internal signal.
Regarding claim 4, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 1 above. Elkin further teaches wherein the second logic gate group comprises:
an XNOR gate (Elkin, annotated Fig. 8A, circuitry of element 107 in combination with 804) that outputs, as the first sum signal, a result of performing an XNOR operation on the second internal signal and the third input signal, wherein the XNOR gate comprises a first plurality of transistor groups and a second plurality of transistor groups (Elkin, annotated Fig. 8A, 510 as first transistor group, 518 as second transistor group).
Regarding claim 8, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 1 above. Elkin further teaches wherein the third logic gate group comprises:
an inverter (Elkin, annotated Fig. 8A, 702) that outputs an inverted signal of the third input signal; and
a second OR-AND-Inverter (OAI) gate (Elkin, annotated Fig. 8A, 508 comprising 205 and 206) that outputs the carry signal based on the inverted signal of the third input signal, the first internal signal, and the second internal.
Regarding claim 9, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 8 above. Elkin further teaches wherein the second OAI gate comprises:
a second OR gate (Elkin, annotated Fig. 8A, 205) that outputs a result of performing a second OR operation on the inverted signal of the third input signal and the second internal signal; and
a third negative AND (NAND) gate (Elkin, annotated Fig. 8A, 206) that outputs the carry signal by performing a NAND operation on the result of performing the second OR operation and the first internal signal.
The rejections of claims 10-16 and 23 make reference to the following figure, which is a modified and annotated version of Elkin Fig. 8, hereinafter referred to as annotated Fig. 8B.
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Regarding claim 10, Elkin teaches a 4-2 compressor integrated circuit comprising:
a first adder (Elkin, annotated Fig. 8B, 301) that generates a first internal signal and a second internal signal (Elkin, annotated Fig. 8B, 105 and 106 respectively) with respect to a first input signal and a second input signal (Elkin, annotated Fig. 8B, 101 and 102 respectively) and outputs a first carry bit (Elkin, annotated Fig. 8B, 110) based on the first internal signal, the second internal signal, and a third input signal (Elkin, annotated Fig. 8B, 103); and
a second adder (Elkin, annotated Fig. 8B, 302) that generates a third internal signal and a fourth internal signal (Elkin, annotated Fig. 8B, 115 and 116 respectively) with respect to a fourth input signal and a fifth input signal (Elkin, annotated Fig. 8B, 111 and 112 respectively), outputs a second carry bit (Elkin, annotated Fig. 8B, 120) based on the third internal signal, the fourth internal signal, and an internal sum bit of the first adder (Elkin, annotated Fig. 8B, 108), and outputs a sum bit based on the internal sum bit and the fourth internal signal (Elkin, annotated Fig. 8B, 118),
wherein the first adder is housed in a first region in a layout of the 4-2 compressor integrated circuit and the second adder is housed in a second region in the layout (Elkin, annotated Fig. 8B, adders 301 and 302 constitute first and second regions),
Elkin does not explicitly teach:
wherein the first region and the second region are coupled to each other to have a symmetrical structure, and
wherein, in the symmetrical structure, a first sub-region of the first region that outputs the internal sum bit is arranged adjacent to a second sub-region of the second region that receive the internal sum bit.
However, Lin teaches the common and advantageous practice of arranging pairs of analog circuit modules in a layout to have a symmetrical placement and arranged as close to each other as possible (Lin, I. Introduction, ¶ 1 and Fig. 1). Elkin annotated Fig. 8B, a composite of Fig. 8, depicts the symmetrical and adjacent arrangement as suggested by Lin in at least Fig. 1A, wherein the adder circuits are symmetric about a vertical axis. A first sub-region of the first region (Elkin, annotated Fig. 8B, 303) that outputs the internal sum bit is arranged adjacent to second sub-regions of the second region (Elkin, annotated Fig. 8B, 304) that receive the internal sum bit.
Regarding claim 11, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 10 above. Elkin further teaches:
a first logic gate group (Elkin, annotated Fig. 8B, 305) that outputs the first internal signal and the second internal signal (Elkin, annotated Fig. 8B, 105 and 106) based on the first input signal and the second input signal (Elkin, annotated Fig. 8B, 101 and 102);
a second logic gate group (Elkin, annotated Fig. 8B, 303) that outputs the internal sum bit (Elkin, annotated Fig. 8B, 108) based on the second internal signal and the third input signal (Elkin, annotated Fig. 8B, 105 and 106); and
a third logic gate group (Elkin, annotated Fig. 8B, 307) that outputs the first carry bit (Elkin, annotated Fig. 8B, 110) based on the first internal signal, the second internal signal, and the third input signal (Elkin, annotated Fig. 8B, 105, 106, and 103),
wherein the first logic gate group, the second logic gate group, and the third logic gate group are housed in the first region (Elkin, annotated Fig. 8B, 301).
Regarding claim 12, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 11 above. Elkin further teaches:
a fourth logic gate group (Elkin, annotated Fig. 8B, 308) that outputs the third internal signal and the fourth internal signal (Elkin, annotated Fig. 8B, 115 and 116) based on the fourth input signal and the fifth input signal (Elkin, annotated Fig. 8B, 111 and 112);
a fifth logic gate group (Elkin, annotated Fig. 8B, 304) that outputs the sum bit (Elkin, annotated Fig. 8B, 118) based on the fourth internal signal and the internal sum bit (Elkin, annotated Fig. 8B, 116 and 108); and
a sixth logic gate group (Elkin, annotated Fig. 8B, 119) that outputs the second carry bit (Elkin, annotated Fig. 8B, 120) based on the third internal signal, the fourth internal signal, and the internal sum bit (Elkin, annotated Fig. 8B, 115, 116, and 108),
wherein the fourth logic gate group, the fifth logic gate group, and the sixth logic gate group are housed in the second region (Elkin, annotated Fig. 8B, 302).
Regarding claim 13, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 12 above. Elkin further teaches:
wherein the first region comprises a first negative AND (NAND) sub-region (Elkin, annotated Fig. 8B, 312) and a first OR-AND-Inverter (OAI) sub-region (Elkin, annotated Fig. 8B, 306), wherein the second region comprises a second NAND sub-region (Elkin, annotated Fig. 8B, 313) and a third OAI sub-region (Elkin, annotated Fig. 8B, 309),
wherein the first logic gate group comprises:
a first negative AND (NAND) gate that is housed in the first NAND sub-region (Elkin, annotated Fig. 8B, 201) and outputs the first internal signal (Elkin, annotated Fig. 8B, 105) by performing a NAND operation on the first input signal and the second input signal (Elkin, annotated Fig. 8B, 101 and 102); and
a first OR-AND-Inverter (OAI) gate that is housed in the first OAI sub-region (Elkin, annotated Fig. 8B, 203 and 204 in combination) and outputs, as the second internal signal (Elkin, annotated Fig. 8B, 106), a result of performing an exclusive negative OR (XNOR) operation on the first input signal and the second input signal (Elkin, annotated Fig. 8B, 101 and 102) based on the first internal signal, the first input signal, and the second input signal (Elkin, annotated Fig. 8B, 105, 101, and 102), and wherein the fourth logic gate group comprises:
a fourth NAND gate that is housed in the second NAND sub-region (Elkin, annotated Fig. 8B, 114) and outputs the third internal signal (Elkin, annotated Fig. 8B, 115) by performing a NAND operation on the fourth input signal and the fifth input signal (Elkin, annotated Fig. 8B, 111 and 112); and
a third OAI gate that is housed in the third OAI sub-region (Elkin, annotated Fig. 8B, 208 and 209 in combination) and outputs, as the fourth internal signal (Elkin, annotated Fig. 8B, 116), a result of performing as XNOR operation on the fourth input signal and the fifth input signal (Elkin, annotated Fig. 8B, 111 and 112) based on the third internal signal, the fourth input signal, and the fifth input signal (Elkin, annotated Fig. 8B, 115, 111, and 112).
Regarding claim 14, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 13 above. Elkin further teaches wherein the first OAI gate comprises:
a first OR gate (Elkin, annotated Fig. 8B, 204) that outputs a result of performing a first OR operation on the first input signal and the second input signal (Elkin, annotated Fig. 8B, 101 and 102); and
a second NAND gate (Elkin, annotated Fig. 8B, 203) that outputs the second internal signal (Elkin, annotated Fig. 8B, 106) by performing a NAND operation on the result of performing the first OR operation and the first internal signal (Elkin, annotated Fig. 8B, 204 and 105), and the third OAI gate comprises:
a third OR gate (Elkin, annotated Fig. 8B, 208) that outputs a result of performing a second third OR operation on the fourth input signal and the fifth input signal (Elkin, annotated Fig. 8B, 111 and 112); and
a fifth NAND gate (Elkin, annotated Fig. 8B, 209) that outputs the fourth internal signal (Elkin, annotated Fig. 8B, 116) by performing a NAND operation on the result of performing the second third OR operation and the third internal signal (Elkin, annotated Fig. 8B, 208 and 115).
Regarding claim 15, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 13 above. Elkin further teaches:
wherein the first region (Elkin, annotated Fig. 8B, 301) further comprises a first exclusive negative OR (XNOR) sub-region (Elkin, annotated Fig. 8B, 303), wherein the second logic gate group includes a first exclusive negative OR (XNOR) gate that is housed in the first XNOR sub-region (Elkin, annotated Fig. 8B, 314) and outputs, as the internal sum bit (Elkin, annotated Fig. 8B, 108), a result of performing an XNOR operation on the second internal signal and the third input signal (Elkin, annotated Fig. 8B, 106 and 103), wherein the first exclusive XNOR sub-region is the first sub-region of the first region.
Regarding claim 16, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 13 above. Elkin further teaches:
wherein the first region further comprises a second OAI sub-region (Elkin, annotated Fig. 8B, 315), and wherein the second region further comprises a fourth OAI sub-region (Elkin, annotated Fig. 8B, 316), wherein the third logic gate group comprises:
a first inverter (Elkin, annotated Fig. 8B, 702) that outputs an inverted signal of the third input signal (Elkin, annotated Fig. 8B, 103); and
a second OAI gate (Elkin, annotated Fig. 8B, 307) that outputs the first carry bit (Elkin, annotated Fig. 8B, 110) based on the inverted signal of the third input signal, the first internal signal, and the second internal signal (Elkin, annotated Fig. 8B, 317, 105, and 106),
and the sixth logic gate group comprises:
a second inverter (Elkin, annotated Fig. 8B, 310) that outputs an inverted signal of the internal sum bit (Elkin, annotated Fig. 8B, 108); and
a fourth OAI gate (Elkin, annotated Fig. 8B, 119) that outputs the second carry bit (Elkin, annotated Fig. 8B, 120) based on the inverted signal of the internal sum bit, the third internal signal, and the fourth internal signal (Elkin, annotated Fig. 8B, 318, 115, and 116),
wherein the first inverter and the second OAI gate are housed in the second OAI sub-region (Elkin, annotated Fig. 8B, 315), the second inverter and the fourth OAI gate are housed in the fourth OAI sub-region (Elkin, annotated Fig. 8B, 315), and the fourth OAI sub-region is one of the second sub-regions of the second region (Elkin, annotated Fig. 8B, 316 contained in second region 302).
Regarding claim 23, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 13 above. Elkin further teaches:
wherein the second region further comprises a second XNOR sub-region (Elkin, annotated Fig. 8B, 304), wherein the fifth logic gate group includes a second XNOR gate (Elkin, annotated Fig. 8B, 304 in combination with 319) that outputs, as the sum bit (Elkin, annotated Fig. 8B, 118), a result of performing an XNOR operation on the fourth internal signal and the internal sum bit (Elkin, annotated Fig. 8B, 116 and 108), wherein the second XNOR gate is housed in the second XNOR sub-region (Elkin, annotated Fig. 8B, 304 and 319 contained in 304) and the second XNOR sub-region is one of the second sub-regions of the second region (Elkin, annotated Fig. 8B, 304 contained in 302).
Regarding claim 24, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 4 above. Elkin further teaches:
wherein the XNOR gate comprises a pass gate activated based on at least one of the third input signal and an inverted signal of the third input signal (Elkin, annotated Fig. 8A, 510 as pass gate, 103 as third input signal, 123 as inverted third input signal).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Elkin, in view of Lin, and further in view of Srivastava et al. (US 20190354347 A1), hereinafter Srivastava.
Regarding claim 25, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 4 above. Elkin does not explicitly teach:
wherein the XNOR gate comprises a plurality of transistor groups connected to one of power and ground.
However, Srivastava teaches:
wherein the XNOR gate comprises a plurality of transistor groups connected to one of power and ground (Srivastava, Fig. 4b).
Srivastava is considered to be analogous to the claimed invention because it is in the same field of CMOS adder circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first full adder of Elkin to replace the circuitry for performing an XNOR operation to be the XNOR circuitry as taught by Srivastava. This modification would have been obvious because generating the sum signal by the single XNOR gate of Srivastava eliminates the need for transmission gates which consume extra power and slow operating speed (Srivastava, ¶ [0003], [0005], [0012]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Elkin, in view of Lin, and further in view of Takahashi (US 5,875,124 A).
Regarding claim 26, Elkin in view of Lin teaches the invention substantially as claimed. See the rejection of claim 4 above. Elkin does not teach wherein the XNOR gate comprises:
a first pass gate that is activated when a logic state of the second internal signal is high, and outputs, as the sum signal, a signal having a same logic state as the third input signal when activated; and
a second pass gate that is activated when the logic state of the second internal signal is low, and outputs, as the sum signal, a signal having a logic state inverted from that of the third input signal when activated.
However, Takahashi does teach:
a first pass gate (Takahashi, Fig. 2A element 204) that is activated when a logic state of the second internal signal is high and outputs, as the sum signal, a signal having a same logic state as the third input signal when activated (Takahashi, col. 11 ln. 56-62); and
a second pass gate (Takahashi, Fig. 2A element 202) that is activated when the logic state of the second internal signal is low, and outputs, as the sum signal, a signal having a logic state inverted from that of the third input signal when activated (Takahashi, col. 11 ln. 47-55).
Takahashi is considered to be analogous to the prior art because they are in the same field of adder circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the adder circuit of Elkin to include the second stage XNOR circuit of Takahashi. This modification would have been obvious because the parallel pass gate structure of the XNOR circuit of Takahashi limits the number of pass gates in the signal path, resulting in higher operating speed and reduced circuit area (Takahashi, col. 3 ln. 55-64).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN DAVID WARNER whose telephone number is (703)756-5956. The examiner can normally be reached M-F: 9-5.
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/J.D.W./
Jonathan David WarnerExaminer, Art Unit 2182
(703)756-5956
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182