DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to RCE filed 06 July 2026.
Claims 22 – 39 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 06 July 2026 has been entered.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement (see Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994)).
The disclosure of the prior-filed application, Application No. 63/222,406, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
This application claims priority to provisional application 63/222,406. However, said provisional application only discloses, on a high level, i) load balancing between SSDs based on update count of respective SSD and selecting memory page to migrate between said SSDs based on write count of respective memory page, and ii) exposing said SSDs to system memory using CXL. Therefore, subject matter (in this application) that are not sufficiently disclosed in said provisional application, are not entitled to priority benefit of said provisional application. In particular, said subject matter is as follows.
Subject matter pertaining to partitioning/mapping of physical address space between main memory and storage devices (see spec Fig. 7, page 17 ln 3 – page 18 ln 25, page 21 ln 24 – page 22 ln 19).
Subject matter pertaining to multi-level page table translation (see spec Fig. 8, page 18 ln 26 – page 19 ln 14).
Subject matter pertaining to selection of memory page (for migration) as one with write counts that is ½ (or approx. ½) of difference of update count of source storage (see spec page 21 ln 2-9).
Subject matter pertaining to migration between main memory and storage devices (see spec page 22 ln 20 – page 23 ln 5).
Subject matter pertaining to memory page migration based on response time of storage devices (see spec page 23 ln 14 – page 24 ln 5).
Subject matter pertaining to assigning different uses to portions of storage devices including use of different requests to access said portions assigned to different uses (see spec Fig. 10, page 15 ln 22-27, page 25 ln 1-19).
Any claim(s) that refer to above identified subject matter would not be entitled to priority of provisional application 63/222,406. Limitations, in claims 22 – 39, that refer to said above identified subject matter are not entitled to priority benefit of provisional application 63/222,406.
Applicant is reminded that any allegations (that above subject matter are supported based on knowledge known to one skilled in the art by reading said provisional application) could be relied upon for purposes of prior art rejection.
Claim Interpretation
Claim 28 is interpreted to refer to it is write count that is difference between first update count and second update count wherein said write count is for the memory page (see Applicant’s remarks filed 29 April 2024 page 9-10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22, 28 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20220244877) in view of Lee (US 20190391755).
Regarding claim 22, Chen teaches
A system, comprising:
a processor;
a memory connected to the processor[, the memory accessed using a set of commands];
a first storage device connected to the processor, the first storage device including a first storage portion, the first storage portion including a memory page, [the first storage portion to extend the memory and accessed using the set of commands];
a second storage device connected to the processor, the second storage device including a second storage portion, [the second storage portion to extend the memory and accessed using the set of commands]; and (Chen teaches host device connected to storage arrays (first and second storage devices) (or storage systems (see ¶[19])) (see Fig. 1) wherein said host device comprises processing device (see ¶[20]) that includes processor (processor) which is coupled to memory (memory) (see Fig. 11, ¶[97]). Chen also teaches said storage arrays implement LUNs (first and second storage portions) to store objects (memory page) (see ¶[23]).)
a load balancing daemon (load balancing daemon = Fig. 1 storage cluster wear-leveling service) to:
select the first storage device and the second storage device based at least in part on a first update count of the first storage device and a second update count of the second storage device,
select the memory page based at least in part on the first storage device, the second storage device, a first update count of the first storage device, a second update count of the second storage device, and a write count for the memory page, and
migrate the memory page from the first storage portion of the first storage device to the second storage portion of the second storage device (Chen teaches identifying (select), using storage cluster wear-leveling service 112 (see ¶[51]), wear level imbalance of two storage systems (first and second storage devices) based on cumulative write requests (first and second update counts) of each of said two storage systems (see Fig. 2, ¶[51-53]). Chen further teaches subsequent to identifying said two storage systems, using (by said storage cluster wear-leveling service 112 (see ¶[51])) hot degree information (write count) to select (select) an object (memory page) from one of said two storage systems and migrating (by said storage cluster wear-leveling service 112 (see ¶[51])) said object to remaining one of said two storage systems (see Fig. 2, ¶[55]). Note that said object i) is selected subsequent to (based on) identification of said two storage systems (first and second storage devices) that are selected based on cumulative write request (first and second update counts) of each of said two systems, and ii) using (based on) said hot degree information (write count).)
wherein the first update count includes a first number of times data has been updated on the first storage device,
wherein the second update count includes a second number of times data has been updated on the second storage device, and (Chen teaches that said two storage systems are identified based on cumulative write requests (first and second update counts) of each of said two storage systems (see Fig. 2, ¶[51-53]) wherein said write requests are used by host (see ¶[23]) to store data (data) on said two storage systems (see ¶[19]). Note that storing of said data results in said data being available (updated) on said two storage systems.)
wherein the write count includes a third number of times data has been written to the memory page (Chen teaches that said object (for migration) is selected based on hot degree information (write count) characterizing number of write requests (third number of times) (see ¶[55]) wherein said write requests are used by host (see ¶[23]) to store data (data) (see ¶[19]).)
As noted in claim 22, Chen teaches memory, first storage device (with first storage portion) and second storage device (with second storage portion) but does not appear to explicitly teach accessing said memory and said first and second storage devices in the following manner.
the memory accessed using a set of commands
the first storage device including a first storage portion, the first storage portion including a memory page, the first storage portion to extend the memory and accessed using the set of commands, the first storage device further including a third storage portion accessed using a second set of commands
the second storage device including a second storage portion, the second storage portion to extend the memory and accessed using the set of commands, the second storage device further including a fourth storage portion, the fourth storage portion accessed using the second set of commands
However, Lee teaches
[the] memory accessed using a set of commands
[the] first storage device including a first storage portion, the first storage portion including a memory page, the first storage portion to extend the memory and accessed using the set of commands, the first storage device further including a third storage portion accessed using a second set of commands (It is noted that “to extent the memory and accessed using the set of commands” is statement of intended use, and thus will not limit the scope of the claim (see PTAB decision mailed 17 March 2026 page 8).)
[the] second storage device including a second storage portion, the second storage portion to extend the memory and accessed using the set of commands, the second storage device further including a fourth storage portion, the fourth storage portion accessed using the second set of commands (It is noted that “to extent the memory and accessed using the set of commands” is statement of intended use, and thus will not limit the scope of the claim (see PTAB decision mailed 17 March 2026 page 8).) (Lee teaches storage device with first storage area 110 (third storage portion, fourth storage portion) and second storage area 120 (first storage portion, second storage portion) (see Fig. 1) wherein there are plural of said storage device (first and second storage devices) (see ¶[197]). Lee further teaches i) processor may request (set of commands) access to main memory (memory) using address allocated to said main memory (see ¶[34]), and ii) said first storage area (third and fourth storage portions) is accessed using request (second set of commands) of first access type (see ¶[59]). Lee also teaches said first and second storage areas implemented as non-volatile memory device (see ¶[39]) that includes memory blocks, each includes pages (memory page) (see Fig. 11, ¶[135-136], [140]).) (This mapping is optional due to above statement of intended use. Lee also teaches said second area (first and second storage portions) supplements (extends) said main memory (memory) (see ¶[50]) wherein said second area is accessed using request (set of commands) of second access type that is based on address system of said main memory (see ¶[60]).)
In view of Lee, Chen is modified such that i) said first and second storage partitions supplements (extends) said memory wherein request (based on address system of said memory) is used to access said memory and said first and second storage partitions, and ii) said first and second storage systems, each further includes first storage area (third and fourth portions) that is accessed using request (second set of commands) of first access type.
Chen and Lee are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Chen in the manner described supra because it would allow auxiliary processor to access said second storage area without loading data into said main memory, thus reducing time, resources and power (Lee, ¶[52-53]).
Regarding claim 28, Chen in view of Lee teach the system of claim 22 where Chen also teaches
wherein the write count for the memory page is less than a difference between the first update count and the second update count (Chen teaches identifying wear level imbalance of two storage systems based on cumulative write requests (first and second update counts) of each of said two storage systems (see Fig. 2, ¶[51-53]) wherein upon identifying said two storage systems, using hot degree information (write count) to select an object (memory page) from one of said two storage systems (see Fig. 2, ¶[55]). In exemplary embodiment, wear imbalance is determined between array 1 and array 3 (see ¶[76]) and object 6 (in array 3) is selected (see ¶[77], [79]). In said exemplary embodiment, i) said array 1 has write requests count (second update count) of 160000, ii) said array 3 has write request count (first update count) of 670000 (see Fig. 5) and iii) said object 6 has hot degree (write count) of 759 (see Fig. 7). Note that 759 is less that difference of 670000 and 160000.)
Regarding claim 32, Chen teaches
A method, comprising:
identifying a first storage device by a load balancing daemon running on a processor;
identifying a second storage device by the load balancing daemon running on the processor;
identifying, based at least in part of identifying the first storage device and the second storage device, a memory page stored on the first storage device by the load balancing daemon running on the processor; and
migrating the memory page from the first storage device to the second storage device, (Chen teaches identifying, using storage cluster wear-leveling service 112 (load balancing daemon) (see ¶[51]), wear level imbalance of two storage systems (first and second storage devices) based on cumulative write requests of each of said two storage systems (see Fig. 2, ¶[51-53]). Chen further teaches subsequent to identifying said two storage systems, using (by said storage cluster wear-leveling service 112 (see ¶[51])) hot degree information to select an object (memory page) from one of said two storage systems and migrating (by said storage cluster wear-leveling service 112 (see ¶[51])) said object to remaining one of said two storage systems (see Fig. 2, ¶[55]). Note that said object i) is selected subsequent to (based on) identification of said two storage systems (first and second storage devices) that are selected based on cumulative write request of each of said two systems, and ii) using said hot degree information.)
As noted in claim 32, Chen teaches first and second storage devices but does not appear to explicitly teach accessing said first and second storage devices in the following manner.
wherein the first storage device and the second storage device extend a memory, the memory accessed using a set of commands, the first storage device accessed using the set of commands, and the second storage device accessed using the set of commands,
wherein the first storage device further includes a third storage portion accessed using a second set of commands, and wherein the second storage device further includes a fourth storage portion, the fourth storage portion accessed using the second set of commands
However, Lee teaches
wherein [the] first storage device and [the] second storage device extend a memory, the memory accessed using a set of commands, the first storage device accessed using the set of commands, and the second storage device accessed using the set of commands,
wherein the first storage device further includes a third storage portion accessed using a second set of commands, and wherein the second storage device further includes a fourth storage portion, the fourth storage portion accessed using the second set of commands (Lee teaches storage device with first storage area 110 (third storage portion, fourth storage portion) and second storage area 120 (see Fig. 1) wherein plural of said storage device (first and second storage devices) (see ¶[197]). Lee further teaches i) processor may request (set of commands) access to main memory (memory) using address allocated to said main memory (see ¶[34]), and ii) said first storage area (third and fourth storage portions) is accessed using request (second set of commands) of first access type (see ¶[59]). Lee also teaches said second area supplements (extends) said main memory (memory) (see ¶[50]) wherein said second area is accessed using request (set of commands) of second access type that is based on address system of said main memory (see ¶[60]). In addition, Lee also teaches said first and second storage areas implemented as non-volatile memory device (see ¶[39]) that includes memory blocks, each includes pages (memory page) (see Fig. 11, ¶[135-136], [140]))
In view of Lee, Chen is modified such that i) said first and second storage devices each includes second storage area that supplements (extends) memory wherein request (set of commands) (based on address system of said memory) is used to access said memory and said second storage areas, and ii) said first and second storage systems, each further includes first storage area (third and fourth portions) that is accessed using request (second set of commands) of first access type.
Chen and Lee are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Chen in the manner described supra because it would allow auxiliary processor to access said second storage area without loading data into said main memory, thus reducing time, resources and power (Lee, ¶[52-53]).
Claims 23, 33 – 34 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee, and further in view of Dastidar (US 11074208).
Regarding claim 23, Chen in view of Lee teach the system according to claim 22.
As noted in claim 22, modified Chen teaches a base system that extends memory using first and second storage portions. The claimed invention improves upon said base system by extending said first and second storage portions in the following manner.
wherein the first storage portion and the second storage portion extend the memory via a cache-coherent interconnect protocol
This improvement to said base method is an application of known technique from Dasitidar – using CXL to manage memory pool used to expand host memory. In particular, Dastidar teaches
wherein [the] first storage portion and [the] second storage portion extend [the] memory via a cache-coherent interconnect protocol (Examiner is interpreting cache-coherent interconnect protocol as referring to CXL (see claim 3 originally filed on 26 October 2021).) (Dastidar teaches expanding host memory (memory) to memory expansion devices (see col 2 ln 65 – col 3 ln 14) by assigning memory pools (first/second storage partition), in said memory expansion devices, to be managed by said host (see col 3 ln 58-col 4 ln 4) wherein CXL (cache-coherent protocol) is used to coherently manage said memory pools (see col 4 ln 40-50). Note that CXL is also inherently a cache-coherent system (see col 1 ln 22-34).)
One of ordinary skill in the art would recognize that this known technique of using CXL to manage memory pools used to expand host memory can also be applied to said first and second storage portions of modified Chen, and the result would have been predictable. In this instance, said first and second storage portions (used to extend said memory) is managed using CXL. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Dastidar’s known technique would have yielded i) predictable result of said first and second storage portions (used to extend said memory) is managed using CXL (cache-coherent interconnect protocol), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 33, Chen in view of Lee teach the method according to claim 32.
As noted in claim 32, modified Chen as modified teaches a base method that extends memory using second storage area, respectively, in first and second storage devices. The claimed invention improves upon said base method by using said second storage area to extent said memory in the following manner.
wherein the first storage device and the second storage device extend a memory via a cache-coherent interconnect protocol
This improvement to said base method is an application of known technique from Dasitidar – using CXL to manage memory pool used to expand host memory. In particular, Dastidar teaches
wherein [the] first storage device and [the] second storage device extend [the] memory via a cache-coherent interconnect protocol (Examiner is interpreting cache-coherent interconnect protocol as referring to CXL (see claim 3 originally filed on 26 October 2021).) (Dastidar teaches expanding host memory (memory) to memory expansion devices (see col 2 ln 65 – col 3 ln 14) by assigning memory pools, in said memory expansion devices (first and second storage devices), to be managed by said host (see col 3 ln 58-col 4 ln 4) wherein CXL (cache-coherent protocol) is used to coherently manage said memory pools (see col 4 ln 40-50). Note that CXL is also inherently a cache-coherent system (see col 1 ln 22-34).)
One of ordinary skill in the art would recognize that this known technique of using CXL to manage memory pools used to expand host memory can also be applied to said second storage area of modified Chen, and the result would have been predictable. In this instance, said second storage area (used to extend said memory), respectively in said first and second storage devices, is managed using CXL. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Dastidar’s known technique would have yielded i) predictable result of said second storage area (used to extend said memory), respectively in said first and second storage devices, is managed using CXL (cache-coherent interconnect protocol), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 34, Chen in view of Lee and Dastidar teach the method according to claim 33 where Chen also teaches
identifying the first storage device by the load balancing daemon running on the processor includes determining a first update count of the first storage device; and
identifying the second storage device by the load balancing daemon running on the processor includes determining a second update count of the second storage device, (Chen teaches identifying, using storage cluster wear-leveling service 112 (load balancing daemon) (see ¶[51]), wear level imbalance of two storage systems (first and second storage devices) based on cumulative write requests (first and second update counts) of each of said two storage systems (see Fig. 2, ¶[51-53]).)
wherein the first update count includes a first number of times data has been updated on the first storage device, and
wherein the second update count includes a second number of times data has been updated on the second storage device (Chen teaches that said two storage systems are identified based on cumulative write requests (first and second update counts) of each of said two storage systems (see Fig. 2, ¶[51-53]) wherein said write requests are used by host (see ¶[23]) to store data (data) on said two storage systems (see ¶[19]). Note that storing of said data results in said data being available (updated) on said two storage systems.)
Regarding claim 38, Chen in view of Lee and Dastidar teach the method according to claim 33 where Chen also teaches
identifying, based at least in part on a write count for the memory page, the memory page stored on the first storage device by the load balancing daemon running on the processor includes identifying the memory page stored on the first storage device by the load balancing daemon running on the processor, (Chen further teaches subsequent to identifying two storage systems (first and second storage systems), using (by said storage cluster wear-leveling service 112 (load balancing daemon) (see ¶[51])) hot degree information (write count) to select an object (memory page) from one of said two storage systems and migrating (by said storage cluster wear-leveling service 112 (see ¶[51])) said object to remaining one of said two storage systems (see Fig. 2, ¶[55]).)
the write count including a third number of times data has been written to the memory page (Chen teaches that said object (for migration) is selected based on hot degree information (write count) characterizing number of write requests (third number of times) (see ¶[55]) wherein said write requests are used by host (see ¶[23]) to store data (data) (see ¶[19]).)
Claims 24 – 25, 27 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee and Dastidar, and further in view of Yamamoto (US 20200034067).
Regarding claim 24, Chen in view of Lee and Dastidar teach the system according to claim 23.
As noted in claim 22, modified Chen teaches a base system with cumulative write requests (first and second update counts) for each of two storage systems (first and second storage devices). The claimed invention improves upon said base system by having each of said two storage systems store its own cumulative write requests (see also limitation below).
the first storage device includes a first Host-Managed Device Memory (HDM) to store the first update count
the second storage device includes a second HDM to store the second update count
This improvement to said base system is an application of known technique from Yamamoto – using storage system’s shared memory to store number of writes to said storage system. In particular, Yamamoto teaches
storage device includes HDM to store update count (Examiner is interpreting HDM to refer to memory storing counts (see spec Fig. 6).) (Yamamoto teaches shared memory (HDM) (of storage system (storage device) (see Fig. 1)) storing parity-group-based monitor table (see Fig. 5), wherein said parity-group-based monitor table includes new write I/O counter (update count) (see Fig. 8) that is number of writes to parity group (see ¶[101]) in said storage system (see Fig. 1, ¶[58]).)
One of ordinary skill in the art would recognize that this known technique of using storage system’s own shared memory to store new write I/O counter of number of writes can also be applied to store modified Chen’s cumulative write requests for each of said two storage systems, and the result would have been predictable. In this instance, each of said two storage systems would store, in its own shared memory, its corresponding cumulative write requests. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yamamoto’s known technique would have yielded i) predictable result of each of said two storage systems (first and second storage devices) would store, in its own shared memory (first and second HDMs), its corresponding cumulative write requests (first and second update counts), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 25, Chen in view of Lee, Dastidar and Yamamoto teach the system according to claim 24 where Chen also teaches
wherein the load balancing daemon (load balancing daemon = storage cluster wear-leveling service) includes an access circuit to access the first update count from the first HDM and to access the second update count from the second HDM (Chen teaches obtaining, via usage information collection module 114 in storage cluster wear-leveling service (see Fig. 1, ¶[26]), cumulative write requests (first and second update counts) for each of two storage systems (see ¶[51]) wherein said usage information collection module 114 is implemented as processing device with processor that is FPGA (access circuit) (see ¶[94-95, 97-98]). Note that in claim 4, Chen has already been modified such that said cumulative write requests (first and second update counts) is stored in respective memory (first and second HDMs) of said two storage systems. Therefore, said cumulative write requests is obtained from said respective memory of said two storage systems.)
Regarding claim 27, Chen in view of Lee, Dastidar and Yamamoto teach the system according to claim 24.
As noted in claim 22, modified Chen teaches a base system that includes a write count of a memory page in first storage device. The claimed invention improves upon said base system by storing said write count in the following manner.
the first HDM further stores the write count for the memory page
This improvement to said base system is an application of known technique from Yamamoto – using storage system’s shared memory to also store write counter of page. In particular, Yamamoto teaches
[the] first HDM further stores a write count for [the] memory page (Examiner is interpreting HDM to refer to memory storing counts (see spec Fig. 6).) (Yamamoto teaches shared memory (first HDM) (of storage system (storage device) (see Fig. 1)) storing parity-group-based monitor table (see Fig. 5), wherein said parity-group-based monitor table includes new write I/O counter (update count) (see Fig. 8) (see also claim 4). Yamamoto further teaches that said shared memory also stores page-based monitor table (see Fig. 5) that includes write I/O counter (write count) of page (memory page) (see Fig. 7) wherein said write I/O counter is number of writes (see ¶[93]) pertaining to data (see ¶[49]).)
One of ordinary skill in the art would recognize that this known technique of using storage system’s own shared memory to also store write I/O counter of page can also be applied to store said write counter of modified Chen, and the result would have been predictable. In this instance, said write counter of said memory page is also stored in said first device’s shared memory which stores new write I/O counter. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yamamoto’s known technique would have yielded i) predictable result of said write counter of said memory page also stored in said first device’s shared memory (first HDM) which stores new write I/O counter (update count), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 35, Chen in view of Lee and Dastidar teach the method according to claim 34 where Chen also teaches
determining the first update count of the first storage device includes accessing the first update count from [a first Host-Managed Device Memory (HDM) of] the first storage device; and
determining the second update count of the second storage device includes accessing the second update count from [a second HDM] of the second storage device (Chen teaches obtaining, via usage information collection module 114 in storage cluster wear-leveling service (see Fig. 1, ¶[26]), cumulative write requests (first and second update counts) for each of two storage systems (see ¶[51]))
As noted in claim 35, modified Chen teaches a base method that accesses i) first update count of first storage device and ii) second update count of second storage device. The claimed invention improves upon said base method by storing said first and second update counts (being accessed) in the following manner.
the first update count from a first HDM of the first storage device
the second update count from a second HDM of the second storage device
This improvement to said base method is an application of known technique from Yamamoto – using storage system’s shared memory to store number of writes that is accessed. In particular, Yamamoto teaches
update count in HDM of storage device (Examiner is interpreting HDM to refer to memory storing counts (see spec Fig. 6).) (Yamamoto teaches shared memory (HDM) (of storage system (storage device) (see Fig. 1)) storing parity-group-based monitor table (see Fig. 5), wherein said parity-group-based monitor table includes new write I/O counter (update count) (see Fig. 8) that is number of writes to parity group (see ¶[101]) in said storage system (see Fig. 1, ¶[58]) wherein said new write I/O counter is counted/accessed (see ¶[143]).)
One of ordinary skill in the art would recognize that this known technique of using storage system’s own shared memory to store new write I/O counter that is accessed can also be applied to store modified Chen’s first and second update counts that are accessed, and the result would have been predictable. In this instance, each of said first and second storage devices would store, in its own shared memory, its corresponding update count that is accessed. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yamamoto’s known technique would have yielded i) predictable result of each of said first and second storage devices would store, in its own shared memory (first and second HDMs), its corresponding update count (first and second update counts) that is accessed, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee and Dastidar and Yamamoto, and further in view of Davies (US 20110252210).
Regarding claim 26, Chen in view of Lee, Dastidar and Yamamoto teach the system according to claim 24.
As noted in claim 24, modified Chen teaches a base system where load balancing daemon (which migrates memory page) uses i) first update count is in first HDM of first storage device, and ii) second update count is in second HDM of second storage device. The claimed invention improves upon said base system by resetting said first and second update counts in the following manner.
wherein the load balancing daemon includes a reset circuit to reset the first update count in the first HDM and to reset the second update count in the second HDM
This improvement to said base system is an application of known technique from Davies – storage controller (daemon) (used to move page (see Davies, ¶[8]) includes CPU (reset circuit) (see Davis ¶[38]) that resets master counter of storage component (see Davies ¶[84]).
One of ordinary skill in the art would recognize that this known technique of using storage controller’s CPU to reset a counter of storage can also be applied to reset each of said first and second update counts of said first and second storage devices in modified Chen, and the result would have been predictable. In this instance, said load balancing daemon (which migrates said memory page) would include a CPU that resets each of said first and second update counts of said first and second storage devices. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Davis’s known technique would have yielded i) predictable result of said load balancing daemon (which migrates said memory page) would include a CPU (reset circuit) that resets each of said first and second update counts of said first and second storage devices, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claims 29 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Lee and Yang (US 20210216446).
Regarding claim 29, Yamamoto teaches
A storage device (storage device = Fig 1 storage system 104), comprising:
a storage (storage = Fig. 2 parity group 205A) including a first storage portion (first storage portion = Fig. 2 pool volume 206A), the first storage portion to store a memory page (memory page = Fig. 2 real page 207A)[, the first storage portion accessed using a set of commands]; (Yamamoto teaches storage system 104 with parity group 205A that includes pool volume 206A storing real page 207A (see Fig. 2, ¶[60], [63]).)
a controller (controller = Fig. 1 processor 114) to process at least one of a load request or a store request sent to the storage device; and (Yamamoto teaches processor 114 that processes read requests (load request) and write requests (store request) from host (see ¶[53]).)
[an increment circuit to manage] an update count identifying a first number of times data has been changed in the storage and a write count identifying a second number of times data has been written to the memory page, [wherein the storage extends a memory, the memory accessed using the set of commands] (Yamamoto teaches shared memory stores page-based monitor table and parity-group based monitor table (see Fig. 5, ¶[82]) wherein i) said parity-group based monitor table includes new write I/O counter (update count) that is number of number of writes (which writes data (see ¶[49])) to parity group 205A (see Fig. 8, ¶[101]) and ii) said page-based monitor table includes write I/O counter (write count) that is number of writes of real page 207A (see Fig. 7, ¶[93]). Note that writing of said data results in said data being available (changed) in said parity group 205A.)
As noted in claim 29, Yamamoto teaches storage with first storage portion but does not appear to explicitly teach using said storage in the following manner.
a storage including a first storage portion, the first storage portion to store a memory page, the first storage portion accessed using a set of commands
wherein the storage extends a memory, the memory accessed using the set of commands
wherein the storage further includes a second storage portion accessed using a second set of commands
However, Lee teaches
a storage including a first storage portion, the first storage portion to store a memory page, the first storage portion accessed using a set of commands
wherein the storage extends a memory, the memory accessed using the set of commands
wherein the storage further includes a second storage portion accessed using a second set of commands (Lee teaches storage device (storage) with first storage area 110 (second storage portion) and second storage area 120 (first storage portion) (see Fig. 1) wherein there are plural of said storage device (see ¶[197]). Lee further teaches i) processor may request (set of commands) access to main memory (memory) using address allocated to said main memory (see ¶[34]), and ii) said first storage area (second storage portion) is accessed using request (second set of commands) of first access type (see ¶[59]). Lee also teaches said second area (first storage portion) supplements (extends) said main memory (memory) (see ¶[50]) wherein said second area is accessed using request (set of commands) of second access type that is based on address system of said main memory (see ¶[60]). In addition, Lee teaches said first and second storage areas implemented as non-volatile memory device (see ¶[39]) that includes memory blocks, each includes pages (memory page) (see Fig. 11, ¶[135-136], [140]).)
In view of Lee, Yamamoto is modified such that i) said first storage portion (with memory page) supplements (extends) memory wherein request (set of commands) (based on address system of said memory) is used to access said memory and said first storage portion, and ii) said storage further includes first storage area (second storage portion) that is accessed using request (second set of commands) of first access type.
Yamamoto and Lee are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Yamamoto in the manner described supra because it would allow auxiliary processor to access said second storage area without loading data into said main memory, thus reducing time, resources and power (Lee, ¶[52-53]).
As noted in claim 29, modified Yamamoto a base device that includes controller, update count and write count. The claimed invention improves upon said base device by having said update and write counts managed by increment circuit in FTL within said controller.
This improvement to said base device is an application of known technique from Yang – controller (controller) includes FTL (translation layer) (see Yang Fig. 1) that increments count based on write command (see Yang ¶[54], Yang claim 17) wherein said FTL is driven by processor (circuit) (see Yang ¶[32]). Note that said FTL includes increment function (increment) that is driven by said processor (circuit). Examiner is interpreting increment circuit to refer to increment logic in FTL (see spec page 15 ln 1-2) that is performed by circuit (see spec page 32 ln 6-8).
One of ordinary skill in the art would recognize that this known technique of using processor to drive FTL (in controller) to increment count can also be applied to increment update and write counts of modified Yamamoto, and the result would have been predictable. In this instance, said update and write counts would be incremented by FTL (in said controller) driven by processor. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yang’s known technique would have yielded i) predictable result of said update and write counts being incremented by FTL (translation layer) (in said controller) driven by processor (increment circuit), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 31, Yamamoto in view of Lee and Yang teach the storage device according to claim 29 where Yamamoto also teaches
a Host-Managed Device Memory (HDM) to store the update count and the write count (Examiner is interpreting HDM to refer to memory storing counts (see spec Fig. 6).) (Yamamoto teaches shared memory (HDM) (in storage system 104 (see Fig. 1)) includes page-based monitor table and parity-group based monitor table (see Fig. 5) wherein i) said parity-group based monitor table includes new write I/O counter (update count) and ii) said page-based monitor table includes write I/O counter (write count) that is number of writes of real page 207A (see Fig. 7, ¶[93]).)
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Lee and Yang, and further in view of Dasditar.
Regarding claim 30, Yamamoto in view of Lee and Yang teach the storage device according to claim 29.
As noted in claim 29, modified Yamamoto a base device which is a storage device. The claimed invention improves upon said base device by having said storage device support cache-coherent interconnect protocol.
This improvement to said base device is an application of known technique from Dastidar – using CXL manage memory pool of memory expansion device. In particular, Dastidar teaches
wherein [the] storage device supports a cache-coherent interconnect protocol (Examiner is interpreting cache-coherent interconnect protocol as referring to CXL (see claim 23).) (Dastidar teaches using CXL (cache-coherent protocol) is to coherently manage memory pool, of respective memory expansion device (storage device), (see col 4 ln 40-50) assigned to host for management (see col 3 ln 58-col 4 ln 4). Note that CXL is also inherently a cache-coherent system (see col 1 ln 22-34). Note that said respective expansion device is managed (supported) by CXL via said memory pool within said respective expansion device.)
One of ordinary skill in the art would recognize that this known technique of using CXL to manage memory pool of memory expansion device can also be applied to manage said storage device of modified Yamamoto, and the result would have been predictable. In this instance, CXL is used to manage pool of said storage device. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Dastidar’s known technique would have yielded i) predictable result of CXL (cache-coherent interconnect protocol) used to manage (support) memory pool of said storage device, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claims 36 – 37 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee and Dastidar, and further in view of Davies.
Regarding claim 36, Chen in view of Lee and Dastidar teach the method according to claim 34.
As noted in claim 34, modified Chen teaches a base method where load balancing daemon migrates based on first and second update counts of first and second storage devices. The claimed invention improves upon said base method by resetting said first and second update counts in the following manner.
resetting the first update count of the first storage device by the load balancing daemon; and
resetting the second update count of the second storage device by the load balancing daemon
This improvement to said base method is an application of known technique from Davies – storage controller (daemon) (used to move page (see Davies, ¶[8]) includes CPU (see Davis ¶[38]) that resets master counter of storage component (see Davies ¶[84]).
One of ordinary skill in the art would recognize that this known technique of using controller to reset counter of storage can also be applied to reset said first and second update counts of said first and second storage devices of modified Chen, and the result would have been predictable. In this instance, said load balancing daemon (which migrates memory page) is used to reset said first and second update counts of said first and second storage devices. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Davies’ known technique would have yielded i) predictable result of said load balancing daemon (which migrates memory page) is used to reset said first and second update counts of said first and second storage devices, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 37, Chen in view of Lee and Dastidar teach the method according to claim 34 where Chen also teaches
a write count associated with the memory page on the first storage device, the write count including a third number of times data has been written to the memory page (Chen teaches using (by storage cluster wear-leveling service 112 (see ¶[51])) hot degree information (write count) to select an object (memory page) from one (first storage device) of two storage systems (first and second storage devices) and migrating (by said storage cluster wear-leveling service 112 (see ¶[51])) said object to remaining one of said two storage systems (see Fig. 2, ¶[55]). Chen further teaches that said object (for migration) is selected based on hot degree information (write count) characterizing number of write requests (third number of times) (see ¶[55]) wherein said write requests are used by host (see ¶[23]) to store data (data) (see ¶[19]).)
As noted in claim 34, modified Chen teaches a base method where load balancing daemon migrates memory page associated with write count. The claimed invention improves upon said base method by resetting said write count in the following manner.
resetting, by the load balancing daemon, a write count associated with the memory page on the first storage device
This improvement to said base method is an application of known technique from Davies – storage controller (daemon) (used to move page (see Davies, ¶[8]) includes CPU (see Davis ¶[38]) that resets I/O counter (write count) of page after migration (see Davies claim 6).
One of ordinary skill in the art would recognize that this known technique of using controller to reset counter after page migration can also be applied to reset said write count of memory page that is migrated in modified Chen, and the result would have been predictable. In this instance, said load balancing daemon (which migrates memory page) is used to reset said write count of said memory page that is migrated. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Davies’ known technique would have yielded i) predictable result of said load balancing daemon (which migrates memory page) is used to reset said write count of said memory page that is migrated, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee and Dastidar, and further in view of Karamcheti (US 20100325383).
Regarding claim 39, Chen in view of Lee and Dastidar the method according to claim 33.
As noted in claim 32, modified Chen teaches a base method of migrating memory page from first storage device to second storage device. The claimed invention improves upon said base method by updating page table based on migrating said memory page (see also limitation below).
migrating the memory page from the first storage device to the second storage device includes updating a page table based at least in part on migration of the page to the second storage device
This improvement to said base method is an application of known technique from Karamcheti – updating page table map upon moving of data to another page. In particular, Karamcheti teaches
migrating [the] memory page from [the] first storage device to [the] second storage device includes updating a page table based at least in part on migration of the page to the second storage device (Karamcheti teaches updating frame number in page table map (page table) upon moving of information in DRAM memory page (first storage device) to flash memory page (second storage device).)
One of ordinary skill in the art would recognize that this known technique of updating a page table upon migration of a memory page also be applied to migration of said memory page in modified Chen, and the result would have been predictable. In this instance, a page table would be updated upon migration of said memory page. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Karamcheti’s known technique would have yielded i) predictable result of a page table being updated upon migration of said memory page, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Response to Remarks
Applicant’s remarks, with respect to the prior art rejection, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly identified prior art Lee.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139
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