DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on September 15th, 2025 has been entered and claims 1-20 are pending. Applicant’s amendments to the Specification have overcome every objection (i.e., drawings and informalities) and 35 U.S.C 101 rejection(s) previously set forth in the Non-Final Office Action mailed on May 16th, 2025. Claims 2 and 14 have been withdrawn from consideration.
Response to Arguments
Applicant's arguments filed September 15th, 2025 have been fully considered but they are not persuasive.
Applicant has argued that Baum does not teach the node-specific granularity for error detection. However, Baum discloses, Col 24, lines 29-31, “the PE is the most basic compute element of the NN processor. The neurons of the ANN are implemented in the PE, essentially in the L1 memory”…Col 18, lines 24-29, “The subcluster, in turn, comprises the most basic units, namely the processing elements (PEs) 76 which are composed of a multiply and accumulate (MAC) circuit and local memory. It is the PE hierarchical level that contains a set of neuron entities found in a typical neural network.” Therefore, the nodes reside within the local memory and MAC (multiply and accumulate) circuit of the PE, error detection mechanisms under the broadest reasonable interpretation would be implemented at this specific, low hierarchical level, hence, ‘node-specific granularity’ is met.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-6, 9-10, 13, 15, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baum et al. (US12248367B2) in view of Borlick et al. (US11119851B2).
Regarding claim 1
Baum teaches:
A method comprising: performing error detection via one or more sets of parallel data paths for each layer of a plurality of layers of a neural network stored in a memory, (Col 16, lines 28-38,“In another embodiment, the NN processor is capable of implementing multiple ANNs in parallel [parallel], where each ANN has one or more network layers. The NN processor is adapted to simultaneously process one or more input data streams associated with the ANNs. Since the architecture of the NN device resembles the structure of an ANN, multiple ANNs can be viewed as a single wide ANN. Note that when deploying multiple ANNs, given enough resources, the mapper in the external tool chain is operative to map available resources while the NN manager governs event triggers”… Col 4, lines 38-51, “a method of end to end failure detection for use in a neural network processor, the method comprising providing a plurality of redundant hardware resources in the neural network processor (i.e., wherein providing redundant hardware resources under the broadest reasonable interpretation (BRI) is interpreted as ‘parallel data paths’), allocating a main computational path from the plurality of redundant hardware resources, the main computational path to be protected from end to end failures, allocating one or more redundant computational paths from the plurality of redundant hardware resources, the one or more redundant computational paths operative to protect the main computational path from end to end failures, calculating cyclic redundancy code (CRC) checksums on tensor stream data output from the main computational path and the one or more redundant computational paths, and detecting an error if the calculated CRC checksums do not match”…Col 61, lines 17-37, “A diagram illustrating a first example cluster interlayer failure detection scheme is shown in FIG. 60. The circuit, generally referenced 1320, shows the data flow within a cluster over several layers. Data in layer L−1 is processed by the processing elements (PEs) 1321 and L2 memory [stored in a memory] 1323 in the subsclusters (SCs) 1322. The data is fed to the APUs 1324 which is operative to generate output data from the layer L−1 that is to be input to the subsequent layer L. In operation, the output data from one layer is stored in L3 memory 1328 which is then streamed to the next layer. To protect the data while stored in L3 memory, a CRC checksum is generated over each data tensor via CRC engine 1326 in the APU. A CRC checksum 1330 is generated and stored along with its data tensor 1331 in L3 memory 1328. In layer L, the data tensor and corresponding CRC are read from L3 memory and input to the input aligner (IA) circuit 1325. A CRC engine 1327 in the IA calculates the CRC on the data tensor and verifies it matches the CRC 1330 read from the L3 memory. If it does not match, an error flag is raised (i.e. interrupt generated) which may be fatal or non-fatal.” [error detection for each layer of a plurality of layers].
wherein the plurality of layers comprises a first layer having a plurality of nodes, and wherein performing error detection comprises performing error detection for each of the plurality of nodes (Col 15, lines 42-47)” the processing element (PE) 76 with its own dedicated internal Layer 1 or L1 memory 78 in which individual neurons are implemented. A plurality of N PEs 76 along with dedicated Layer 2 or L2 memory 74 make up the next hierarchical level termed a subcluster 70” further in (Col 74-75, lines 54-67 and 1-3) “A high level block diagram illustrating an example NN intermediate results safety mechanism is shown in FIG. 84. The example subcluster 1750 comprises a plurality of processing elements (PEs) 1752, PE #0 to PE #63, each PE having associated L1 memory 1754, multiplexer 1756, CRC engine 1785, L2 memory 1762 incorporating blocks of stored NN intermediate results 1765, and LCU 1768. In one embodiment, a running first CRC checksum is calculated over all the NN intermediate results generated by a single subcluster from calculations conducted on a single output row with all its input features and to store the CRC checksum in L2 memory with the NN intermediate results. When reading the NN intermediate results from L2 memory, a second running CRC checksum is calculated over the NN intermediate results read from memory and compared to the first CRC checksum. If a mismatch is detected, an error flag 1760 is raised” [error detection at each of the plurality of nodes].
Baum does not explicitly teach:
and retraining the first layer of the neural network based on the error detection.
Borlick teaches:
and retraining the first layer of the neural network based on the error detection. (Col 11, lines 25-29) “machine learning module 120 to retrain the machine learning module 120 to produce a desired output value, such as a higher or lower output value depending on whether an error has been detected (block 610 in FIG. 6) or not detected” [retraining based on the error detection].
the retraining comprising updating one or more weights associated with the first layer that are stored in the memory in association with the neural network (Col 7, lines 19-21, “the machine learning module 120 may comprise an artificial neural network [neural network] programs trained using back propagation to adjust weights [updating one or more weights] and biases at nodes (i.e., wherein under the broadest reasonable interpretation (BRI) back prop include first layer)”)
Baum and Borlick are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Borlick it would have been obvious for a person of ordinary skill in the art to apply the teachings of Borlick to Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors (Borlick Col 6, lines 19-24 “The machine learning module may continually be retrained to improve the predictive accuracy of determining whether the storage device is experiencing errors using a current state of operational parameters and feedback on actual experienced errors or lack of errors.”)
Regarding claim 3
Baum in view of Borlick teaches the method of claim 1, wherein Borlick further teaches:
retraining the first layer in response to determining that a number of errors detected at the plurality of nodes exceeds a threshold (Col 11, lines 25-30) “machine learning module 120 to retrain the machine learning module 120… whether an error has been detected (block 610 in FIG. 6) or not detected a threshold number of times (from block 620 in FIG. 6)” [retraining based on the error detection once a threshold is met].
The motivation for claim 3 is the same as the motivation for claim 1.
Regarding claim 5
Baum in view of Borlick teaches the method of claim 1, wherein Baum further teaches:
wherein performing error detection comprises: at each of the plurality of nodes, calculating a node operand value via a first path and calculating a redundant value at a second path operating in parallel to the first path (Col 58, lines 8-22) “the target neural network and desired redundancy, the compiler determines a main computation path and one or more redundant computation paths for one or more layers from the available hardware resources. The available hardware resources in the NN processor are configured to create the main and redundant tensor data flow paths in the clusters 1147. The two different paths go to two different output stream managers. The CRC generator in each stream manager of a protected path calculates a CRC for every block (i.e. row) of tensor data that is output. The CRCs enter the mux and are compared in accordance with the table that indicates whether which stream managers are redundantly allocated. The CRC compare must pass and if not, an error flag (i.e. fatal-interrupt) is raised.” [calculating a node operand value via a first path and calculating a redundant value at a second path operating in parallel to the first path].
The motivation for claim 5 is the same as the motivation for claim 1.
Regarding claim 6 and analogous claim 18
Baum in view of Borlick teaches the method of claim 1, wherein Baum further teaches:
wherein performing error detection comprises: computing a residue value at each of the plurality of nodes (Col 73, lines 34-38) “each subcluster has its own corresponding CRC engine. The CRC engine is operative to calculate a CRC checksum over the weights retrieved from the L2 memory. A CRC checksum is calculated for each block of weights.” [discloses the use of a cyclic redundancy code (CRC) checksum during the error detection] under the broadest reasonable interpretation (BRI), a “residue value” is related to CRC checksum. The specification states, paragraph [0029] In other embodiments, the residue values 340 and 341 are stored at the analog memory cells of the memory 104 and are protected by error detection codes to reduce false positives (resulting from an erroneous residue but error-free operand) during error detection.
Baum and Borlick are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Borlick it would have been obvious for a person of ordinary skill in the art to use CRC checksum which results in residue values to apply it with the teachings of Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors (Borlick Col 6, lines 19-24 “The machine learning module may continually be retrained to improve the predictive accuracy of determining whether the storage device is experiencing errors using a current state of operational parameters and feedback on actual experienced errors or lack of errors.”)
Regarding claim 9
Baum teaches:
A method, comprising: for a first layer of a plurality of layers of a neural network stored in memory, detecting errors via one or more sets of parallel data paths at each node of a plurality of nodes of the first layer; and signaling an error based on a number of detected errors at the plurality of nodes of the first layer exceeding a threshold stored in the memory in association with the neural network. (Col 16, lines 28-38,“In another embodiment, the NN processor is capable of implementing multiple ANNs in parallel [parallel], where each ANN has one or more network layers. The NN processor is adapted to simultaneously process one or more input data streams associated with the ANNs. Since the architecture of the NN device resembles the structure of an ANN, multiple ANNs can be viewed as a single wide ANN. Note that when deploying multiple ANNs, given enough resources, the mapper in the external tool chain is operative to map available resources while the NN manager governs event triggers”…Col 73, lines 34-41) “each subcluster has its own corresponding CRC engine. The CRC engine is operative to calculate a CRC checksum over the weights retrieved from the L2 memory [stored in memory]. A CRC checksum is calculated for each block of weights. Once the CRC checksum calculation is complete, it is compared to the precalculated checksum read from memory. If a mismatch is detected, the CRC engine generates an error flag [signaling] 1718” (discloses a neural network having clusters and subclusters that is monitored and errors are detected).
Baum does not explicitly teach:
exceeding a threshold stored in the memory in association with the neural network.
Borlick teaches:
exceeding a threshold stored in the memory in association with the neural network. (Col 11, lines 25-30) “machine learning module 120 to retrain the machine learning module 120… whether an error has been detected (block 610 in FIG. 6) or not detected a threshold number of times (from block 620 in FIG. 6) (i.e., wherein the number of errors detected reaches a threshold is interpreted as a value set as a threshold, hence ‘stored’)”
Regarding claim 10
Baum in view of Borlick teaches the method of claim 9, wherein Baum further teaches:
for a second layer of the plurality of layers of a neural network, detecting errors at nodes of the second layer; and signaling the error based on a number of detected errors at the second layer. (Col 74-75, lines 54) “A high level block diagram illustrating an example NN intermediate results safety mechanism is shown in FIG. 84. The example subcluster 1750 comprises a plurality of processing elements (PEs) 1752, PE #0 to PE #63, each PE having associated L1 memory 1754, multiplexer 1756, CRC engine 1785, L2 memory 1762 incorporating blocks of stored NN intermediate results 1765, and LCU 1768. In one embodiment, a running first CRC checksum is calculated over all the NN intermediate results generated by a single subcluster from calculations conducted on a single output row with all its input features and to store the CRC checksum in L2 memory with the NN intermediate results. When reading the NN intermediate results from L2 memory, a second running CRC checksum is calculated over the NN intermediate results read from memory and compared to the first CRC checksum. If a mismatch is detected, an error flag 1760 is raised” [discloses detecting errors at nodes of the second layer; signaling the error based on a number of detected errors at the second layer].
Regarding claim 13
Baum teaches:
a memory configured to store data representing a neural network; an error detection circuit coupled to the memory and configured to perform error detection for each layer of a plurality of layers of the neural network via one or more sets of parallel data paths, (Col 16, lines 28-38,“In another embodiment, the NN processor is capable of implementing multiple ANNs in parallel [parallel], where each ANN has one or more network layers. The NN processor is adapted to simultaneously process one or more input data streams associated with the ANNs. Since the architecture of the NN device resembles the structure of an ANN, multiple ANNs can be viewed as a single wide ANN. Note that when deploying multiple ANNs, given enough resources, the mapper in the external tool chain is operative to map available resources while the NN manager governs event triggers”… Col 4, lines 38-51, “a method of end to end failure detection for use in a neural network processor, the method comprising providing a plurality of redundant hardware resources in the neural network processor (i.e., wherein providing redundant hardware resources under the broadest reasonable interpretation (BRI) is interpreted as ‘parallel data paths’), allocating a main computational path from the plurality of redundant hardware resources, the main computational path to be protected from end to end failures, allocating one or more redundant computational paths from the plurality of redundant hardware resources, the one or more redundant computational paths operative to protect the main computational path from end to end failures, calculating cyclic redundancy code (CRC) checksums on tensor stream data output from the main computational path and the one or more redundant computational paths, and detecting an error if the calculated CRC checksums do not match”…Col 61, lines 17-37, “A diagram illustrating a first example cluster interlayer failure detection scheme is shown in FIG. 60. The circuit, generally referenced 1320, shows the data flow within a cluster over several layers. Data in layer L−1 is processed by the processing elements (PEs) 1321 and L2 memory [stored in a memory] 1323 in the subsclusters (SCs) 1322. The data is fed to the APUs 1324 which is operative to generate output data from the layer L−1 that is to be input to the subsequent layer L. In operation, the output data from one layer is stored in L3 memory 1328 which is then streamed to the next layer. To protect the data while stored in L3 memory, a CRC checksum is generated over each data tensor via CRC engine 1326 in the APU. A CRC checksum 1330 is generated and stored along with its data tensor 1331 in L3 memory 1328. In layer L, the data tensor and corresponding CRC are read from L3 memory and input to the input aligner (IA) circuit 1325. A CRC engine 1327 in the IA calculates the CRC on the data tensor and verifies it matches the CRC 1330 read from the L3 memory. If it does not match, an error flag is raised (i.e. interrupt generated) which may be fatal or non-fatal.”
wherein the plurality of layers comprises a first layer having a plurality of nodes, and wherein to perform error detection for the first layer comprises performing the error detection for each of the plurality of nodes; and (Col 15, lines 42-47)” the processing element (PE) 76 with its own dedicated internal Layer 1 or L1 memory 78 in which individual neurons are implemented. A plurality of N PEs 76 along with dedicated Layer 2 or L2 memory 74 make up the next hierarchical level termed a subcluster 70” further in (Col 74-75, lines 54-67 and 1-3) “A high level block diagram illustrating an example NN intermediate results safety mechanism is shown in FIG. 84. The example subcluster 1750 comprises a plurality of processing elements (PEs) 1752, PE #0 to PE #63, each PE having associated L1 memory 1754, multiplexer 1756, CRC engine 1785, L2 memory 1762 incorporating blocks of stored NN intermediate results 1765, and LCU 1768. In one embodiment, a running first CRC checksum is calculated over all the NN intermediate results generated by a single subcluster from calculations conducted on a single output row with all its input features and to store the CRC checksum in L2 memory with the NN intermediate results. When reading the NN intermediate results from L2 memory, a second running CRC checksum is calculated over the NN intermediate results read from memory and compared to the first CRC checksum. If a mismatch is detected, an error flag 1760 is raised”
Baum does not explicitly teach:
a processor comprising neural network training circuitry coupled to the error detection circuit and the memory, the neural network training circuitry configured to retrain at least one layer of the neural network based on the error detection
Borlick teaches:
a processor comprising neural network training circuitry coupled to the error detection circuit and the memory, the neural network training circuitry configured to retrain at least one layer of the neural network based on the error detection (Col 6, lines 32, “A computing system 100 accesses data in storage devices 102 in a storage array 104. The computing system 100 includes a processor [a processor] 106 and a memory [memory] 108, including a cache 110 to cache data for the storage array 104. The processor 106 may comprise one or more central processing units (CPUs) or a group of multiple cores on a single CPU. The cache 110 buffers data requested by processes within the computing system”… (Col 11, lines 25-29) “machine learning module 120 to retrain the machine learning module 120 to produce a desired output value, such as a higher or lower output value depending on whether an error has been detected (block 610 in FIG. 6) or not detected” [retrain at least one layer of the neural network based on the error detection].)
Baum and Borlick are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Borlick it would have been obvious for a person of ordinary skill in the art to apply the teachings of Borlick to Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors (Borlick Col 6, lines 19-24 “The machine learning module may continually be retrained to improve the predictive accuracy of determining whether the storage device is experiencing errors using a current state of operational parameters and feedback on actual experienced errors or lack of errors.”)
Regarding claim 15
Baum, as modified by Borlick, teaches the apparatus of claim 13.
Baum does not explicitly teach:
wherein the neural network training circuitry is to: retrain the first layer in response to determining that a number of errors detected at the plurality of nodes exceeds a threshold
Borlick further teaches:
wherein the neural network training circuitry is to: retrain the first layer in response to determining that a number of errors detected at the plurality of nodes exceeds a threshold (Col 11, lines 25-30) “machine learning module 120 to retrain the machine learning module 120… whether an error has been detected (block 610 in FIG. 6) or not detected a threshold number of times (from block 620 in FIG. 6)” [retraining based on the error detection once a threshold is met]”…Col 13, lines 43, “electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention (i.e, wherein training circuitry under the broadest reasonable interpretation can include program instructions for retraining)”)
The motivation for claim 15 is the same as the motivation for claim 13.
Regarding claim 17
Baum, as modified by Borlick, teaches the apparatus of claim 13.
Baum further teaches:
at each of the plurality of nodes, calculating a node operand value via a first path of a first set of parallel data paths and calculating an error value at a second path of the first set of parallel data paths (Col 58, lines 8-22) “the target neural network and desired redundancy, the compiler determines a main computation path and one or more redundant computation paths (i.e., wherein the redundant path is interpreted as a second path of the set of parallel paths) for one or more layers from the available hardware resources. The available hardware resources in the NN processor are configured to create the main and redundant tensor data flow paths in the clusters 1147. The two different paths go to two different output stream managers. The CRC generator in each stream manager of a protected path calculates a CRC for every block (i.e. row) of tensor data that is output. The CRCs enter the mux and are compared in accordance with the table that indicates whether which stream managers are redundantly allocated. The CRC compare must pass and if not, an error flag (i.e., wherein the error flag is interpreted as an error value) (i.e. fatal-interrupt) is raised.” [calculating a node operand value via a first path of a first set of parallel data paths and calculating an error value at a second path of the first set of parallel data paths].
Baum does not explicitly teach:
wherein the error detection circuit is to perform error detection by:
Borlick further teaches:
wherein the error detection circuit is to perform error detection by: Col 13, lines 43, “electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention (i.e, wherein training circuitry under the broadest reasonable interpretation can include program instructions for error detection)”
The motivation for claim 17 is the same as the motivation for claim 13.
Claim(s) 4, 7-8, 16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baum, as modified by Borlick in view of Azarian et al. Non-Patent Literature ("Learned Threshold Pruning").
Regarding claim 4 and analogous claim 16
Baum in view of Borlick teaches the method of claim 1.
Baum in view of Borlick does not explicitly teach:
wherein the threshold is a trainable value by the neural network.
Azarian teaches:
wherein the threshold is a trainable value by the neural network. (Pg. 2, ¶2, lines 14-17) “Our proposed method uses…layer-wise thresholds trainable, allowing the training procedure to find optimal thresholds alongside the layer weights during finetuning” [discloses threshold is a trainable value].
Azarian and Baum are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Azarian it would have been obvious for a person of ordinary skill in the art to apply a trainable threshold to the teachings of Borlick to Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors (Azarian Pg.1, ¶2, lines 3-5, “With the increasing demand for deploying DNNs on resource-constrained edge devices, it has become even more critical to reduce the memory footprint of neural networks and also to achieve power-efficient inference on these devices.”)
Regarding claim 7 and analogous claim 19
Baum in view of Borlick teaches the method of claim 1.
Baum in view of Borlick does not explicitly teach:
wherein the residue value is based upon a trainable residue factor.
Azarian further teaches:
wherein the residue value is based upon a trainable residue factor (Pg. 2, ¶2, lines 14-17) “Our proposed method uses…layer-wise thresholds trainable, allowing the training procedure to find optimal thresholds alongside the layer weights during finetuning” [discloses per layer trainable threshold value].
The motivation for claim 7 is the same as the motivation for claim 4.
Regarding claim 8 and analogous claim 20
Baum in view of Borlick teaches the method of claim 1.
Baum in view of Borlick does not explicitly teach:
wherein a residue factor for the first layer is different than a residue factor for a second layer of the plurality of layers
Azarian further teaches:
wherein a residue factor for the first layer is different than a residue factor for a second layer of the plurality of layers (Pg.2, ¶2, lines 1-2) “Our proposed method uses separate pruning thresholds for every layer.”
Azarian and Baum are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Azarian it would have been obvious for a person of ordinary skill in the art to apply the teachings of Azarian to Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baum, as modified by Borlick and Azarian, further in view of Kang et al. (KR102134339B1).
Regarding claim 11
Baum in view of Borlick teaches the method of claim 9.
Baum as modified by Borlick, does not explicitly teach:
wherein detecting errors at the first layer comprises: generating, at a node of the first layer, an operand via a first path of a first set of parallel data paths; generating, at the node of the first layer, an error value via an error detection path of the first set of parallel data paths; and detecting an error at the node of the first layer based on the operand and the error value.
Kang teaches:
wherein detecting errors at the first layer comprises: generating, at a node of the first layer, an operand via a first path; (paragraph [0026]) The multi-layer perceptron is calculated by multiplying the input value input to n artificial neurons and the weight represented by each artificial neuron, and delivering the result derived to the activation function to adjust and output the value by the activation function [an operand]. generating, at the node of the first layer, an error value; (paragraph [0030]) The computing system verifies errors that may occur when an operation is performed using the computation core of the GPU by performing the same operation of neurons adjacent to the operation of 0 and comparing the values. In a multi-layer perceptron structure, a node set not to perform an operation according to a dropout performs the same operation of an adjacent node [an error value]. and detecting an error at the node of the first layer based on the operand and the error value (paragraph [0021-0022]) The graphic processing unit 200 performs a calculation defined according to the multi-layer perceptron structure in an inactive calculation core block to which the dropout is applied among multiple calculation cores, and outputs a second result value. The central processing unit 100 is connected to the graphic processing unit 200 and compares the first result value and the second result value to detect an error-producing operation core among the operation cores included in the graphic processing unit [detecting an error based on the operand and the error value].
Kang and Baum are both related to the same field of endeavor (i.e., error detection). In view of the teachings of Kang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kang to Baum before the effective filing date of the claimed invention in order to improve the accuracy and efficiency of a neural network’s system for detecting errors (Kang, paragraph [0015], “The computing system detects errors that may occur in the learning process of the artificial neural network using the GPU, can identify the cause of malfunctions and learning time delays that may occur in the artificial neural network according to the error, and builds a highly reliable artificial neural network.”)
Regarding claim 12
Baum, as modified by Borlick, Azarian, and Kang teaches the method of claim 11, wherein Baum teaches:
wherein the error value comprises a residue of the operand (Col 73, lines 34-38) “each subcluster has its own corresponding CRC engine. The CRC engine is operative to calculate a CRC checksum over the weights retrieved from the L2 memory. A CRC checksum is calculated for each block of weights.” [discloses the use of a cyclic redundancy code (CRC) checksum during the error detection] under the broadest reasonable interpretation (BRI), a “residue value” is related to CRC checksum. The specification states, paragraph [0029] In other embodiments, the residue values 340 and 341 are stored at the analog memory cells of the memory 104 and are protected by error detection codes to reduce false positives (resulting from an erroneous residue but error-free operand) during error detection.
The motivation for claim 12 is the same as the motivation for claim 11.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMINA MORENO BENOURAIDA/Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129
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