DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Prior Art Rejections
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
Applicant asserts Elmer teaches away from claimed circuit, citing paragraph [0067] and that a POSITA would not be motivated to split Elmer’s shared multiplier into separate circuits because doing so would defeat Elmer’s express design goal.
Examiner respectfully disagrees. Applicant’s evidence for the rationale that Elmer teaches away is not consistent with the rationale for modification, as the modification is not creating two separate multiplier circuits of Elmer’s shared multiplier but characterizing two separate circuitry components of Elmer’s shared multiplier (the integer multiplier 1002 and floating point multiplier 1004). A POSITA would be motivated to distinguish the shared multiplier into at least an integer multiply core and floating point multiply core based on Elmer’s disclosure [0064]-[0070]. Furthermore, Elmer would not teach away as Applicant asserted because “the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed”. See MPEP 2143.01(I). Applicant’s cited passage of Elmer discloses the shared multiplier instead of separate multipliers, but does not discredit using separate multipliers.
Applicant asserts Kintali is directed to software code generation tools ([0072]) and not hardware circuits, wherein even if combined, Kintali’s algorithmic component 318 is a single unified component.
Examiner respectfully disagrees. Kintali paragraph [0237] notes the logic disclosed may be hardware-based or a combination of hardware-based and software-based and discusses configuring for ASIC in [0133]. Additionally, Kintali’s algorithmic component 318 is described comprising distinguishable elements ([0085]). Therefore, it would be reasonable for a POSITA to apply the elements of algorithmic component 318 of Kintali to modify the hardware components of Elmer’s shared multiplier and characterize parts of the integer multiplier and/or floating point multiplier.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer et al. (US 20210157549 A1, hereinafter “Elmer”) in view of Kintali et al. (US 20170351493 A1, hereinafter “Kintali”)
As per claim 1, Elmer teaches An integrated circuit comprising: a MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to perform concatenated multiply and accumulate operations, wherein each multiplier- accumulator circuit of the plurality of multiplier-accumulator circuits of the MAC pipeline includes (Elmer: Fig. 1, [0037], systolic array corresponding to MAC pipeline and processing element corresponding to multiplier-accumulator circuit):
a multiplier circuit array, including a plurality of multiplier circuits, to: (i) receive first data and filter weight data, (ii) multiply the first data and the filter weight data and generate product data and (iii) output the product data, wherein the plurality of multiplier circuits includes (Elmer: Fig. 10A element 208, [0063] – [0066], the integer multiplier and floating-point multiplier corresponding to circuits within the multiplier circuit array):
a first multiplier circuit connected to an output bus (Elmer: Fig. 10A element 251, 255; wherein the MUX product corresponds to an output bus), the first multiplier circuit having a multiply core, to perform a first portion of a floating-point multiplication operation by summing a first portion of the first data and a first portion of the filter weight data to generate a first field (Elmer: Fig. 10A element 1004, 1008 [0066]; The Examiner interprets element 1008 to correspond to the multiply core of the first multiplier circuit), wherein the first portion of the first data and the first portion of the filter weight data are exponent fields, and the first field is an exponent field of the product data (Elmer: Fig. 10A element 1008; [0069]),
and a second multiplier circuit connected to the output bus (Elmer: Fig. 10A element 250, 255; wherein the MUX product corresponds to an output bus), the second multiplier circuit having a multiply core, to perform a second portion of the floating-point multiplication operation by multiplying a second portion of the first data and a second portion of the filter weight data to generate a second field (Elmer: Fig. 10A element 1002, [0065]), wherein the second portion of the first data and the second portion of the filter weight data are fraction fields (Elmer: Fig. 10A element 1002; [0066]; it is known that floating-point data types contain a fraction field), wherein the product data includes data which is representative of the first field and the (Elmer: Fig. 10A element 251, [0063]);
and an accumulator circuit, coupled to the multiplier circuit array of the associated multiplier-accumulator circuit via the output bus (Elmer: Fig. 10A element 255), to (i) receive the product data from the associated multiplier circuit array, and (ii) add the product data and second data to generate sum data (Elmer: Fig 10A element 1014, [0077], input partial sum corresponding to second data);
However, while Elmer discloses a shared multiplier with floating-point circuitry and integer circuitry (Elmer: Fig. 10A element 208), and the multipliers can be separate [0038]. Elmer does not explicitly disclose how the circuitry may be connected, nor how their cores may be separate. Thus, Elmer does not teach wherein the second multiplier circuit is configured to output the second field to the first multiplier circuit via an interconnection bus, and the first multiplier circuit is configured to receive the second field from the second multiplier circuit via the interconnection bus and modify the received second field to generate a modified second field of the product data and adjust the first field based on the modified second field, wherein the modified second field is a fraction field of the product data, wherein the first multiplier circuit assembles the product data from the first field generated from the first portion of the floating-point multiplication operation and the modified second field generated from the second portion of the floating-point multiplication operation, wherein the product data includes data which is representative of the first field and the modified second field; and wherein the multiply core of the first multiplier circuit and the multiply core of the second multiplier circuit are separate and different multiply cores.
Kintali teaches wherein the second multiplier circuit is configured to output the second field to the first multiplier circuit via an interconnection bus, and the first multiplier circuit is configured to receive the second field from the second multiplier circuit via the interconnection bus and modify the received second field to generate a modified second field of the product data and adjust the first field based on the modified second field (Kintali: Fig. 3 elements 332, 334; [0085]-[0086]; wherein multiply element 332 corresponds to the second multiplier circuit, and thus the connection of element 332 to element 334 corresponds to the interconnection bus, where all the sub-elements of element 318 aside from element 332 corresponds to the floating-point multiplier circuit), wherein the first multiplier circuit assembles the product data from the first field generated from the first portion of the floating-point multiplication operation and the modified second field generated from the second portion of the floating-point multiplication operation (Kintali: Fig. 3 element 348; [0086], wherein the exponent sum is adjusted based on the normalized product of the magnitudes), wherein the product data includes data which is representative of the first field and the modified second field (Kintali: elements 352, 340; [0085]-[0086]); and wherein the multiply core of the first multiplier circuit and the multiply core of the second multiplier circuit are separate and different multiply cores (Kintali: Fig. 3 elements 332, 334; wherein element 332 is a distinct multiply element).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the shared multiplier of Elmer with the algorithmic component of Kintali; wherein the multiply element 332 of Kintali corresponds to the integer and/or shared part of multiplier 1006 of Elmer, and the remaining algorithmic component elements of Kintali correspond to the non-shared floating point multiplier circuitry of Elmer. One would have been motivated to combine these references because both references disclose floating-point multipliers that comprise integer arithmetic circuitry, and combining prior art elements according to known methods to yield predictable results (an example of circuitry performing floating-point multiplication in the shared multiplier of Elmer).
As per claim 18, Elmer teaches An integrated circuit comprising: a MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to perform concatenated multiply and accumulate operations, wherein each multiplier- accumulator circuit of the plurality of multiplier-accumulator circuits of the MAC pipeline (Elmer: Fig. 1, [0037], systolic array corresponding to MAC pipeline and processing element corresponding to multiplier-accumulator circuit) includes:
a multiplier circuit array, including a plurality of multiplier circuits, to: (i) receive first data and filter weight data, (ii) multiply the first data and the filter weight data and generate product data and (iii) output the product data (Elmer: Fig. 10A element 208, [0063] – [0066], the integer multiplier and floating-point multiplier corresponding to circuits within the multiplier circuit array), wherein the plurality of multiplier circuits includes: a floating point type multiplier circuit connected to an output bus (Elmer: Fig. 10A element 251, 255; wherein the MUX product corresponds to an output bus), the floating point type multiplier circuit having an AxA multiply core (Elmer: Fig. 10A element 1004, [0066]), to perform a first portion of a floating-point multiplication operation by summing an exponent field of the first data and an exponent field of the filter weight data to generate an exponent field of the product data (Elmer: Fig. 10A element 1008, [0069]), and an integer type multiplier circuit connected to the output bus (Elmer: Fig. 10A element 250, 255; wherein the MUX product corresponds to an output bus), the integer type multiplier circuit having a BxB multiply core, to perform a second portion of the floating-point multiplication operation by multiplying a fraction field of the first data and a fraction field of the filter weight data to generate a fraction field (Elmer: Fig. 10A element 1002, [0065]), wherein the product data includes data which is representative of the exponent field and the (Elmer: Fig. 10A element 251, [0063]);
and an accumulator circuit, coupled to the multiplier circuit array of the associated multiplier-accumulator circuit via the output bus (Elmer: Fig. 10A element 255), to (i) receive the product data from the associated multiplier circuit array and (ii) add the product data and second data to generate sum data; and wherein A and B are positive integers representing the number of bits in each operand (Elmer: Fig 10A element 1014, [0077], input partial sum corresponding to second data).
However, while Elmer discloses a shared multiplier with floating-point circuitry and integer circuitry (Elmer: Fig. 10A element 208), Elmer does not explicitly disclose how the circuitry may be connected. Thus, Elmer does not teach wherein the integer type multiplier circuit is configured to output the fraction field to the floating point type multiplier circuit via an interconnection bus, and the floating point type multiplier circuit is configured to receive the fraction field from the integer type multiplier circuit via the interconnection bus and modify the received fraction field to generate a modified fraction field of the product data and adjust the exponent field of the product data based on the modified fraction field, wherein the floating-point type multiplier circuit assembles the product data from the exponent field generated from the first portion of the floating-point multiplication operation and the modified fraction field generated from the second portion of the floating-point multiplication operation, wherein the product data includes data which is representative of the exponent field and the modified fraction field.
Kintali teaches wherein the integer type multiplier circuit is configured to output the fraction field to the floating point type multiplier circuit via an interconnection bus, and the floating point type multiplier circuit is configured to receive the fraction field from the integer type multiplier circuit via the interconnection bus and modify the received fraction field to generate a modified fraction field of the product data and adjust the exponent field of the product data based on the modified fraction field (Kintali: Fig. 3 elements 332, 334, 348; [0085]-[0086]; wherein multiply element 332 corresponds to the second multiplier circuit, and thus the connection of element 332 to element 334 corresponds to the interconnection bus, where all the sub-elements of element 318 aside from element 332 corresponds to the floating-point multiplier circuit), wherein the floating-point type multiplier circuit assembles the product data from the exponent field generated from the first portion of the floating-point multiplication operation and the modified fraction field generated from the second portion of the floating-point multiplication operation (Kintali: Fig. 3 element 348; [0086], wherein the exponent sum is adjusted based on the normalized product of the magnitudes), wherein the product data includes data which is representative of the exponent field and the modified fraction field (Kintali: elements 340, 352; [0085]-[0086]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the shared multiplier of Elmer with the combined multiplier of Kintali. For at least the same reasons as discussed above in claim 1.
As per claim 19, Elmer/Kintali further teaches The integrated circuit of claim 18 wherein: A is greater than B (Elmer: [0065] - [0066], of note the multiplier producing 16-bit floating point product and 8 or 9-bit integer product).
Claims 2-4, 7-8, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer/Kintali in further view of Kaul et al. (US 20180315399 A1, hereinafter “Kaul”).
As per claim 2, Elmer/Kintali further teaches The integrated circuit of claim 1 wherein: the multiply core of first multiplier circuit is a floating point type (Elmer: [0064]);
However, while Elmer discloses processing elements comprising a floating-point multiplier and integer multiplier (Elmer: [0038]), Elmer does not explicitly disclose the multipliers carrying out fixed-point arithmetic. Thus, Elmer/Kintali does not teach and the multiply core of the second multiplier circuit is a fixed point type.
Kaul teaches and the multiply core of the second multiplier circuit is a fixed point type (Kaul: [0205]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the integer multiplier of Elmer with the fixed-point mode of Kaul. One would have been motivated to combine these references because both references disclose multiplier circuitry for multiple data formats, and combining prior art elements according to known methods to yield predictable results (explicit circuitry capable of fixed-point or floating-point multiplication).
As per claim 3, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 2 wherein: the fixed point type multiply core of the second multiplier circuit is an integer type (Elmer: [0064]).
As per claim 4, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 3 wherein: the multiply core of the second multiplier circuit is integrated into the first multiplier circuit (Elmer: Fig. 10A element 1006, [0067]).
As per claim 7, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 6 wherein: the interconnection bus is a point-to-point bus (Kintali: Fig. 3 elements 332, 334; the data transfer from element 332 to 334 corresponds to the interconnection bus, and is a direct point-to-point interconnection).
As per claim 8, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 6 wherein the first multiplier circuit of each multiplier circuit array of each multiplier-accumulator circuit of the MAC pipeline further includes: rounding circuitry to receive the second field from the second multiplier circuit and output a rounded second field wherein the rounded second field is the second field of the product data (Kintali: Fig. 3 element 336; [0085]).
As per claim 21, the claim is directed to an integrated circuit that implements the same or similar features as the integrated circuit of claim 7, and is therefore rejected for at least the same reasons therein.
As per claim 22, the claim is directed to an integrated circuit that implements the same or similar features as the integrated circuit of claim 8, and are therefore rejected for at least the same reasons therein.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Elmer/Kintali in view of Danysh et al. (US 2019196785 A1, hereinafter “Danysh”).
As per claim 20, Elmer/Kintali further teaches The integrated circuit of claim 18.
However, while Elmer/Kintali discloses exemplary multiplier sizes for discussion, Elmer/Kintali does not explicitly teach wherein: B is greater than A.
Danysh teaches wherein: B is greater than A (Danysh: Fig. 2 element 232 and 263, [0026], [0040] Of note the integer multiplier is 32x32 and the floating-point multiplier is 21x21.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplier size of Elmer with the multipliers of Danysh. One would have been motivated to combine these references because both references disclose multiplier circuitry for integer and floating-point, and Danysh improves upon Elmer by teaching a method of multiplying large bit-width floating-point values that reduces cost and size (Danysh: [0015]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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