DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/13/2026 has been entered.
Response to Arguments
Prior Art Rejections
Applicant’s arguments, filed 1/13/2026, with respect to the rejections of claims 1, 18 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer et al. (US 20210157549 A1, hereinafter “Elmer”) in view of Kintali et al. (US 20170351493 A1, hereinafter “Kintali”)
As per claim 1, Elmer teaches An integrated circuit comprising: a MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to perform concatenated multiply and accumulate operations, wherein each multiplier- accumulator circuit of the plurality of multiplier-accumulator circuits of the MAC pipeline includes (Elmer: Fig. 1, [0037], systolic array corresponding to MAC pipeline and processing element corresponding to multiplier-accumulator circuit):
a multiplier circuit array, including a plurality of multiplier circuits, to: (i) receive first data and filter weight data, (ii) multiply the first data and the filter weight data and generate product data and (iii) output the product data, wherein the plurality of multiplier circuits includes (Elmer: Fig. 10A element 208, [0063] – [0066], the integer multiplier and floating-point multiplier corresponding to circuits within the multiplier circuit array):
a first multiplier circuit connected to an output bus (Elmer: Fig. 10A element 251, 255; wherein the MUX product corresponds to an output bus), the first multiplier circuit having a multiply core, to sum a first portion of the first data and a first portion of the filter weight data to generate a first field (Elmer: Fig. 10A element 1004, 1008 [0066]; The Examiner interprets element 1008 to correspond to the multiply core of the first multiplier circuit), wherein the first portion of the first data and the first portion of the filter weight data are exponent fields, and the first field is an exponent field of the product data (Elmer: Fig. 10A element 1008; [0069]),
and a second multiplier circuit connected to the output bus (Elmer: Fig. 10A element 250, 255; wherein the MUX product corresponds to an output bus), the second multiplier circuit having a multiply core, to multiply a second portion of the first data and a second portion of the filter weight data to generate a second field (Elmer: Fig. 10A element 1002, [0065]), wherein the second portion of the first data and the second portion of the filter weight data are fraction fields (Elmer: Fig. 10A element 1002; [0066]; it is known that floating-point data types contain a fraction field), wherein the product data includes data which is representative of the first field and the (Elmer: Fig. 10A element 251, [0063]);
and an accumulator circuit, coupled to the multiplier circuit array of the associated multiplier-accumulator circuit via the output bus (Elmer: Fig. 10A element 255), to (i) receive the product data from the associated multiplier circuit array, and (ii) add the product data and second data to generate sum data (Elmer: Fig 10A element 1014, [0077], input partial sum corresponding to second data);
However, while Elmer discloses a shared multiplier with floating-point circuitry and integer circuitry (Elmer: Fig. 10A element 208), and the multipliers can be separate [0038]. Elmer does not explicitly disclose how the circuitry may be connected, nor how their cores may be separate. Thus, Elmer does not teach wherein the second multiplier circuit is configured to output the second field to the first multiplier circuit via an interconnection bus, and the first multiplier circuit is configured to receive the second field from the second multiplier circuit via the interconnection bus and modify the received second field to generate a modified second field of the product data and adjust the first field based on the modified second field, wherein the modified second field is a fraction field of the product data, wherein the product data includes data which is representative of the first field and the modified second field; and wherein the multiply core of the first multiplier circuit and the multiply core of the second multiplier circuit are separate and different multiply cores.
Kintali teaches wherein the second multiplier circuit is configured to output the second field to the first multiplier circuit via an interconnection bus, and the first multiplier circuit is configured to receive the second field from the second multiplier circuit via the interconnection bus and modify the received second field to generate a modified second field of the product data and adjust the first field based on the modified second field (Kintali: Fig. 3 elements 332, 334, 348; [0085]-[0086]; wherein multiply element 332 corresponds to the second multiplier circuit, and thus the connection of element 332 to element 334 corresponds to the interconnection bus, where all the sub-elements of element 318 aside from element 332 corresponds to the floating-point multiplier circuit), wherein the product data includes data which is representative of the first field and the modified second field (Kintali: elements 352, 340; [0085]-[0086]); and wherein the multiply core of the first multiplier circuit and the multiply core of the second multiplier circuit are separate and different multiply cores (Kintali: Fig. 3 elements 332, 334; wherein element 332 is a distinct multiply element).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the shared multiplier of Elmer with the algorithmic component of Kintali; wherein the multiply element 332 of Kintali corresponds to the shared part of multiplier 1006 of Elmer, and the remaining algorithmic component elements of Kintali correspond to the non-shared floating point multiplier circuitry of Elmer. One would have been motivated to combine these references because both references disclose floating-point multipliers that comprise integer arithmetic circuitry, and combining prior art elements according to known methods to yield predictable results (an example of circuitry performing floating-point multiplication in the shared multiplier of Elmer).
As per claim 18, Elmer teaches An integrated circuit comprising: a MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to perform concatenated multiply and accumulate operations, wherein each multiplier- accumulator circuit of the plurality of multiplier-accumulator circuits of the MAC pipeline (Elmer: Fig. 1, [0037], systolic array corresponding to MAC pipeline and processing element corresponding to multiplier-accumulator circuit) includes:
a multiplier circuit array, including a plurality of multiplier circuits, to: (i) receive first data and filter weight data, (ii) multiply the first data and the filter weight data and generate product data and (iii) output the product data (Elmer: Fig. 10A element 208, [0063] – [0066], the integer multiplier and floating-point multiplier corresponding to circuits within the multiplier circuit array), wherein the plurality of multiplier circuits includes: a floating point type multiplier circuit connected to an output bus (Elmer: Fig. 10A element 251, 255; wherein the MUX product corresponds to an output bus), the floating point type multiplier circuit having an AxA multiply core (Elmer: Fig. 10A element 1004, [0066]), to sum an exponent field of the first data and an exponent field of the filter weight data to generate an exponent field of the product data (Elmer: Fig. 10A element 1008, [0069]), and an integer type multiplier circuit connected to the output bus (Elmer: Fig. 10A element 250, 255; wherein the MUX product corresponds to an output bus), the integer type multiplier circuit having a BxB multiply core, to multiply a fraction field of the first data and a fraction field of the filter weight data to generate a fraction field (Elmer: Fig. 10A element 1002, [0065]), wherein the product data includes data which is representative of the exponent field and the (Elmer: Fig. 10A element 251, [0063]);
and an accumulator circuit, coupled to the multiplier circuit array of the associated multiplier-accumulator circuit via the output bus (Elmer: Fig. 10A element 255), to (i) receive the product data from the associated multiplier circuit array and (ii) add the product data and second data to generate sum data; and wherein A and B are positive integers representing the number of bits in each operand (Elmer: Fig 10A element 1014, [0077], input partial sum corresponding to second data).
However, while Elmer discloses a shared multiplier with floating-point circuitry and integer circuitry (Elmer: Fig. 10A element 208), Elmer does not explicitly disclose how the circuitry may be connected. Thus, Elmer does not teach wherein the integer type multiplier circuit is configured to output the fraction field to the floating point type multiplier circuit via an interconnection bus, and the floating point type multiplier circuit is configured to receive the fraction field from the integer type multiplier circuit via the interconnection bus and modify the received fraction field to generate a modified fraction field of the product data and adjust the exponent field of the product data based on the modified fraction field, wherein the product data includes data which is representative of the exponent field and the modified fraction field.
Kintali teaches wherein the integer type multiplier circuit is configured to output the fraction field to the floating point type multiplier circuit via an interconnection bus, and the floating point type multiplier circuit is configured to receive the fraction field from the integer type multiplier circuit via the interconnection bus and modify the received fraction field to generate a modified fraction field of the product data and adjust the exponent field of the product data based on the modified fraction field (Kintali: Fig. 3 elements 332, 334, 348; [0085]-[0086]; wherein multiply element 332 corresponds to the second multiplier circuit, and thus the connection of element 332 to element 334 corresponds to the interconnection bus, where all the sub-elements of element 318 aside from element 332 corresponds to the floating-point multiplier circuit), wherein the product data includes data which is representative of the exponent field and the modified fraction field (Kintali: elements 340, 352; [0085]-[0086]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the shared multiplier of Elmer with the combined multiplier of Kintali. For at least the same reasons as discussed above in claim 1.
As per claim 19, Elmer/Kintali further teaches The integrated circuit of claim 18 wherein: A is greater than B (Elmer: [0065] - [0066], of note the multiplier producing 16-bit floating point product and 8 or 9-bit integer product).
Claims 2-4, 7-8, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer/Kintali in further view of Kaul et al. (US 20180315399 A1, hereinafter “Kaul”).
As per claim 2, Elmer/Kintali further teaches The integrated circuit of claim 1 wherein: the multiply core of first multiplier circuit is a floating point type (Elmer: [0064]);
However, while Elmer discloses processing elements comprising a floating-point multiplier and integer multiplier (Elmer: [0038]), Elmer does not explicitly disclose the multipliers carrying out fixed-point arithmetic. Thus, Elmer/Kintali does not teach and the multiply core of the second multiplier circuit is a fixed point type.
Kaul teaches and the multiply core of the second multiplier circuit is a fixed point type (Kaul: [0205]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the integer multiplier of Elmer with the fixed-point mode of Kaul. One would have been motivated to combine these references because both references disclose multiplier circuitry for multiple data formats, and combining prior art elements according to known methods to yield predictable results (explicit circuitry capable of fixed-point or floating-point multiplication).
As per claim 3, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 2 wherein: the fixed point type multiply core of the second multiplier circuit is an integer type (Elmer: [0064]).
As per claim 4, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 3 wherein: the multiply core of the second multiplier circuit is integrated into the first multiplier circuit (Elmer: Fig. 10A element 1006, [0067]).
As per claim 7, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 6 wherein: the interconnection bus is a point-to-point bus (Kintali: Fig. 3 elements 332, 334; the data transfer from element 332 to 334 corresponds to the interconnection bus, and is a direct point-to-point interconnection).
As per claim 8, Elmer/Kintali/Kaul further teaches The integrated circuit of claim 6 wherein the first multiplier circuit of each multiplier circuit array of each multiplier-accumulator circuit of the MAC pipeline further includes: rounding circuitry to receive the second field from the second multiplier circuit and output a rounded second field wherein the rounded second field is the second field of the product data (Kintali: Fig. 3 element 336; [0085]).
As per claim 21, the claim is directed to an integrated circuit that implements the same or similar features as the integrated circuit of claim 7, and is therefore rejected for at least the same reasons therein.
As per claim 22, the claim is directed to an integrated circuit that implements the same or similar features as the integrated circuit of claim 8, and are therefore rejected for at least the same reasons therein.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Elmer/Kintali in view of Danysh et al. (US 2019196785 A1, hereinafter “Danysh”).
As per claim 20, Elmer/Kintali further teaches The integrated circuit of claim 18.
However, while Elmer/Kintali discloses exemplary multiplier sizes for discussion, Elmer/Kintali does not explicitly teach wherein: B is greater than A.
Danysh teaches wherein: B is greater than A (Danysh: Fig. 2 element 232 and 263, [0026], [0040] Of note the integer multiplier is 32x32 and the floating-point multiplier is 21x21.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplier size of Elmer with the multipliers of Danysh. One would have been motivated to combine these references because both references disclose multiplier circuitry for integer and floating-point, and Danysh improves upon Elmer by teaching a method of multiplying large bit-width floating-point values that reduces cost and size (Danysh: [0015]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182