DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-11, 13, 25, and 27 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ochi (US 2024/0146179).
Regarding claims 10 and 13, fig. 1, 4, and 5 of Ochi discloses a non-transitory computer readable medium that stores instructions that, when executed by a processor, cause the processor to: instruct a control signal generator[20] to provide a first cycle [e.g. first cycle of fig. 5 when Vgs of TARGET ARM transitions from Vgoff to Vgon] of a control signal [output of 20- Vgs comprising Vgon and Vgoff] to a transistor, in which the control signal transitions from a first state [when Vgoff] to a second state [when Vgon] at a first time within the first cycle, the transistor is disabled responsive to the control signal having the first state, and the transistor is enabled responsive to the control signal having the second state; receive a detection signal [output of 3] indicating whether the transistor conducts a current during the transition or when the control signal is in the first state [3b detects VGS and 3c detects IDS]; determine a second time at which the control signal transitions from the first state to the second state within a second cycle [e.g. first cycle of fig. 5 when Vgs of TARGET ARM transitions from Vgoff to Vgon] of the control signal responsive to the detection signal [output of 3 feeds back to 20, which generates the control signal]; and instruct the control signal generator to provide the second cycle of the control signal to a the transistor.
Regarding claim 11, fig. 1, 4, and 5 of Ochi discloses storing instructions that, when executed by the processor, cause the processor to: generate the detection signal indicating that the transistor conducts a current during the transition or when the control signal is in the first state responsive to a voltage across the transistor being below a threshold (40b of fig. 4 where Vdsref is the threshold) and the control signal is in the first state; and generate the detection signal indicating that the transistor does not conduct a current during the transition or when the control signal is in the first state responsive to the voltage being above the threshold and the control signal is in the first state.
Regarding claim 25, fig. 1, 4, and 5 of Ochi discloses wherein the system is part of a power converter having power outputs, and the transistor is coupled between the power outputs.
Regarding claims 1-4, and 9, these claims are merely methods to operate the circuit having structure recited in claims 10, 11, 13, and 25. Since Ochi above teaches the structure, the methods to operate such a circuit are similarly disclosed.
Regarding claim 27, fig. 1, 4, and 5 of Ochi discloses wherein the detection signal indicates whether a third quadrant conduction within the first cycle of the control cycle is detected (when VDS and IDS are negative as detected by 3).
Allowable Subject Matter
Claims 6-8, 12, 14-16, 21-24, and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIBIN CHEN/Primary Examiner, Art Unit 2896
Prosecution Insights