Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Due to a restriction requirement, Claims 8-13 have been withdrawn. Thus, in this application, Claims 1-7 and 14-20 are pending.
Examiner's Note
The Examiner respectfully requests of the Applicant in preparing responses, to fully consider the entirety of the reference(s) as potentially teaching all or part of the claimed invention. It is noted, REFERENCES ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN. “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art, including non-preferred embodiments (see MPEP 2123). The Examiner has cited particular locations in the reference(s) as applied to the claim(s) above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim(s), typically other passages and figures will apply as well.
The Examiner further notes that when reading the preamble in the context of the entire claim, any preamble recitation is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
Response to Arguments
Applicant’s arguments, see REMARKS page 6 filed 12/9th/2025, regarding the objection to claims 3, and 16 have been considered and they are persuasive. Therefore, the objection to claims 3 and 16 has been withdrawn.
Applicant’s arguments, see REMARKS page 6-8 filed 12/9th/2025, regarding the 35 USC § 101 rejection of claims 1-7, and 14-20 have been considered and they are not persuasive.
Applicant argument #1
Even assuming, arguendo, that amended claim 1 recites an abstract idea under Prong 1 of Step 2A, Applicant respectfully asserts that any such abstract idea is integrated into a practical application under Prong 2 of Step 2A. For example, amended claim 1 is directed to a particular application of a machine learning model to an edge computing device, which is an application that requires concrete technical improvements in machine learning technology, such as the quantized version of the MLM, recited in claim 1. As described in paragraphs [0062]-[0066] of the originally filed specification, edge computing devices have significantly less data storage and processing capabilities than standard machine learning application, requiring the claims quantization to achieve the same or similar performance with the reduced resources.
Examiner Response #1
The examiner respectfully disagrees. The claim does not recite how the invention quantizes the MLM nor does it recite any benefit of the quantization of the MLM, therefore, the quantization of the MLM does not appear to integrate the abstract idea into a practical application. Furthermore, while the disclosure [0062]-[0066] of the originally filed specification states that edge computing devices have significantly less data storage and processing capabilities than standard machine learning application, requiring the claims quantization to achieve the same or similar performance with the reduced resources, there is no improvement to the functioning of a computer nor to any other technology. At best, the claimed combination amounts to an improvement to the abstract idea of computing … a first output of a first neuron layer of the MLM, computing … a second output of a second neuron layer of the MLM, or computing … a third output of a third neuron layer of the MLM rather than to an improvement on the functioning of a computer or to any other technology. See MPEP 2106.05(a). Thus, even when considering the elements in combination, the claim as a whole does not integrate the recited exception into a practical application.
Applicant’s arguments, see REMARKS page 9 filed 12/9th/2025, regarding the 35 USC § 103 rejection of claims 1-7, and 14-20 have been considered and they are moot in light of the new rejection necessitated by the amendment.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 and 14-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claimed invention is directed to an abstract idea without significantly more. The claims recite mental processes and mathematical concepts. The judicial exception is not integrated into a practical application because the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Step 1 for all Claims:
Claims 1-7 are directed towards a process, and claims 14-20 are directed to a machine. Therefore, claims 1-7, 14-20 are directed to one of the four statutory categories of invention, i.e., process, machine, manufacture, or composition of matter.
Regarding Claim 1:
Step 2A Prong 1:
computing … a first output of a first neuron layer of the MLM (MPEP 2106.04(a)(2)(I) A claim that recites a mathematical calculation will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation or an act of calculating using mathematical methods to determine a variable or number);
computing … a second output of a second neuron layer of the MLM (MPEP 2106.04(a)(2)(I) A claim that recites a mathematical calculation will be considered as falling within the "mathematical concepts" grouping);
computing … a third output of a third neuron layer of the MLM (MPEP 2106.04(a)(2)(I) A claim that recites a mathematical calculation will be considered as falling within the "mathematical concepts" grouping);
Step 2A Prong 2:
A method to run a machine-learning model (MLM) (MPEP 2106.05(f) computer implementation which are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component);
by a processing device of an edge computing device (ECD) (MPEP 2106.05(f) computer implementation which are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component);
storing, by the processing device of the ECD, the first output in a first plurality of memory locations (MPEP 2106.05(g) where storing data in memory is considered insignificant extra-solution activity);
by a processing device of the ECD (MPEP 2106.05(f) computer implementation which are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component);
storing, by the processing device of the ECD, the second output in a second plurality of memory locations (MPEP 2106.05(g) where storing data in memory is considered insignificant extra-solution activity);
storing, by the processing device of the ECD, the third output in the first plurality of memory locations (MPEP 2106.05(g) where storing data in memory is considered insignificant extra-solution activity).
wherein the at least one of the first, second, or third neuron layers is a quantized version of the MLM This is a field of use limitation which amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (MPEP § 2106.05(h)). As explained by the Supreme Court, a claim directed to a judicial exception cannot be made eligible "simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use." Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application.
Step 2B:
A method to run a machine-learning model (MLM) (MPEP 2106.05(f) computer implementation which are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component);
by a processing device of an edge computing device (ECD) (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(II)(iv) “Storing and retrieving information in memory”);
storing, by the processing device of the ECD, the first output in a first plurality of memory locations (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(II)(iv) “Storing and retrieving information in memory”).
by a processing device of the ECD (MPEP 2106.05(f) computer implementation which are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component);
storing, by the processing device of the ECD, the second output in a second plurality of memory locations (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(II)(iv) “Storing and retrieving information in memory”);
storing, by the processing device of the ECD, the third output in the first plurality of memory locations (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(II)(iv) “Storing and retrieving information in memory”).
wherein the at least one of the first, second, or third neuron layers is a quantized version of the MLM This is a field of use limitation which amounts to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (MPEP § 2106.05(h)). As explained by the Supreme Court, a claim directed to a judicial exception cannot be made eligible "simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use." Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application.
The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 2:
Step 2A Prong 1:
Refer to Claim 1.
Step 2A Prong 2:
The method of claim 1, wherein an input into the second neuron layer of the MLM comprises the first output and an input into the third neuron layer of the MLM comprises the second output (MPEP 2106.05(g) where storing data in memory is considered insignificant extra-solution activity).
Step 2B:
The method of claim 1, wherein an input into the second neuron layer of the MLM comprises the first output and an input into the third neuron layer of the MLM comprises the second output (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(d)(II)(ii) “Performing repetitive calculations”). The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 3:
Step 2A Prong 1:
Refer to Claim 1.
Step 2A Prong 2:
The method of claim 1, wherein the first plurality of memory locations are in a first memory buffer and the second plurality of memory locations is in a second memory buffer different from the first memory buffer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).
Step 2B:
The method of claim 1, wherein the first plurality of memory locations are in a first memory buffer and the second plurality of memory locations are in a second memory buffer different from the first memory buffer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 4:
Step 2A Prong 1:
Refer to Claims 1 and 3.
Step 2A Prong 2:
The method of claim 3, wherein a size of the first memory buffer is sufficient to store an output of any one of odd-numbered neuron layers of the MLM, the odd- numbered neuron layers of the MLM comprising the first neuron layer and the third neuron layer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).
Step 2B:
The method of claim 3, wherein a size of the first memory buffer is sufficient to store an output of any one of odd-numbered neuron layers of the MLM, the odd- numbered neuron layers of the MLM comprising the first neuron layer and the third neuron (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims). The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 5:
Step 2A Prong 1:
Refer to Claims 1 and 3.
Step 2A Prong 2:
The method of claim 3, wherein a size of the second memory buffer is sufficient to store an output of any one of even-numbered neuron layers of the MLM, the even-numbered neuron layers of the MLM comprising the second neuron layer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).
Step 2B:
The method of claim 3, wherein a size of the second memory buffer is sufficient to store an output of any one of even-numbered neuron layers of the MLM, the even-numbered neuron layers of the MLM comprising the second neuron layer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims). The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 6:
Step 2A Prong 1:
Refer to Claim 1.
Step 2A Prong 2:
The method of claim 1, wherein the first plurality of memory locations and the second plurality of memory locations are in a same memory buffer (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).
Step 2B:
The method of claim 1, wherein the first plurality of memory locations and the second plurality of memory locations are in a same memory buffer (MPEP 2106.05(d) well-understood, routine, conventional activities previously known to the industry, which is recited at a high level of generality, are not eligible. MPEP 2106.05(d)(II)(iv) “Storing and retrieving information in memory”). The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding Claim 7:
Step 2A Prong 1:
Refer to Claims 1 and 6.
Step 2A Prong 2:
The method of claim 6, wherein the same memory buffer is a cache buffer located on a processor chip of the processing device (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims).
Step 2B:
The method of claim 6, wherein the same memory buffer is a cache buffer located on a processor chip of the processing device (MPEP 2106.05(h) the limitation merely confines the use of an abstract idea to a particular technological environment and thus fails to add an inventive concept to the claims). The claim does not recite any additional elements, taken alone or in combination, that integrate the judicial exception into a practical application.
Regarding claims 14-20:
Claims 14-20 are the system claims corresponding to the method claims 1-7 respectively. Therefore, claims 14-20 are rejected under 35 USC § 101 based upon the same rationale as claims 1-7 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 14-15 are rejected under 35 U.S.C. 103 as being anticipated by DUNNE et al., referred to as DUNNE (US20200272899A1) in view of YANG et al., referred to as YANG (Deploy Large-Scale Deep Neural Networks in Resource Constrained IoT Devices with Local Quantization Region).
Regarding Claim 1:
DUNNE teaches computing, by a processing device of an edge computing device (ECD, a first output of a first neuron layer of the a MLM ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device. The examiner further notes that it is known for someone of ordinary skill in the art that running a deep neural network on an edge device requires computing a first output of a first neuron layer of the DNN).
storing, by the processing device of the ECD, the first output in a first plurality of memory locations ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device and storing the generated activations of its neurons (neuron output) including a first neuron activation in the edge device memory).
computing, by the processing device of the ECD, a second output of a second neuron layer of the MLM ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device. The examiner further notes that it is known for someone of ordinary skill in the art that running a deep neural network on an edge device requires computing a second output of a second neuron layer of the DNN).
storing, by the processing device of the ECD, the second output in a second plurality of memory locations ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device and storing the generated activations of its neurons (neuron output) including a second neuron activation in the edge device memory).
computing, by the processing device of the ECD, a third output of a third neuron layer of the MLM ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device. The examiner further notes that it is known for someone of ordinary skill in the art that running a deep neural network on an edge device requires computing a third output of a third neuron layer of the DNN).
storing, by the processing device of the ECD, the third output in the first plurality of memory locations ([0006] In some aspects, the methods may include the edge device receiving the trained neural network, collecting the dataset from sensors of the edge device, applying the collected dataset as inputs to the received neural network to generate activations and the overall inference result, storing at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result in a memory of the edge device, and sending the neural network information that includes at least a portion of at least one or more of the collected dataset, the generated activations, or the overall inference result to the centralized site/device. The examiner notes that DUNNE [Fig. 5] teaches deploying a deep neural network to an edge device and storing the generated activations of its neurons (neuron output) including a third neuron activation in the edge device memory).
However, DUNNE is not relied upon to explicitly teach wherein the at least one of the first, second, or third neuron layers is a quantized version of the MLM.
On the other hand, YANG teaches wherein the at least one of the first, second, or third neuron layers is a quantized version of the MLM ([Page 3, equation 6] Each layer’s quantization function shares one scaling factor, various from layer to layer. The examiner notes that DUNNE and YANG are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein the at least one of the first, second, or third neuron layers is a quantized version of the MLM as taught by YANG [Page 3, equation 6] in order to retain the model’s accuracy and reduce computational complexity [Page 1, abstract]).
Regarding Claim 2:
DUNNE teaches wherein an input into the second neuron layer of the MLM comprises the first output and an input into the third neuron layer of the MLM comprises the second output [0034] The term "AI model" may be used herein to refer to wide variety of information structures that may be used by a computing device to perform a computation or evaluate a specific condition, feature, factor, dataset, or behavior on a device. Examples of AI models include network models, neural network models, inference models, neuron models, classifiers, random forest models, spiking neural network (SNN) models, convolutional neural network (CNN) models, recurrent neural network (RNN) models, deep neural network (DNN) models, generative network models, and genetic algorithm models. In some embodiments, an AI model may include an architectural definition ( e.g., the neural network architecture, etc.) and one or more weights (e.g., neural network weights, etc.). The examiner notes that DUNNE teaches using RNNs, CNNs, or DNNs, all of which feed the output of a neural network’s layer as input to the next layer of the neural network).
Claims 14-15 are the system claim corresponding to the method claims 1-2 respectively. Therefore, claims 14-15 are rejected under 35 USC § 103 based upon the same rationale as claims 1-2.
Claims 3-7, 16-20 are rejected under 35 U.S.C. 103 as being anticipated by DUNNE et al., referred to as DUNNE (US20200272899A1) in view of YANG et al., referred to as YANG (Deploy Large-Scale Deep Neural Networks in Resource Constrained IoT Devices with Local Quantization Region), further in view of MILLS et al., referred to as MILLS (US20210241079A1).
Regarding Claim 3:
DUNNE teaches The method of claim 1, however, DUNNE is not relied upon to explicitly teach wherein the first plurality of memory locations is in a first memory buffer and the second plurality of memory locations are in a second memory buffer different from the first memory buffer.
On the other hand, MILLS teaches wherein the first plurality of memory locations is in a first memory buffer and the second plurality of memory locations are in a second memory buffer different from the first memory buffer ([0069] For example, neural engines 314, planar engine 340 (which generated data in a previous operation cycle), and system memory 230 may generate or transmit different datasets that are saved in different memory locations of data processor circuit 318. The examiner notes that DUNNE and MILLS are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein the first plurality of memory locations is in a first memory buffer and the second plurality of memory locations are in a second memory buffer different from the first memory buffer as taught by MILLS [0069] to allow for the segmentation of larger datasets into different work units [0069]).
Regarding Claim 4:
DUNNE teaches The method of claim 3, however, DUNNE is not relied upon to explicitly teach wherein a size of the first memory buffer is sufficient to store an output of any one of odd-numbered neuron layers of the MLM, the odd- numbered neuron layers of the MLM comprising the first neuron layer and the third neuron layer.
On the other hand, MILLS teaches wherein a size of the first memory buffer is sufficient to store an output of any one of odd-numbered neuron layers of the MLM, the odd- numbered neuron layers of the MLM comprising the first neuron layer and the third neuron layer ([0052] In one embodiment, buffer 334 is embodied as a non-transitory memory that can be accessed by neural engines 314 and planar engine 340. Buffer 334 may store input data 322A through 322N for feeding to corresponding neural engines 314A through 314N or planar engine 340, as well as output data 328A through 328N from each of neural engines 314A through 314N or planar engine 340 for feeding back into one or more neural engines 314 or planar engine 340, or sending to a target circuit (e.g., system memory 230). Buffer 334 may also store input data 342 and output data 344 of planar engine 340 and allow the exchange of data between neural engine 314 and planar engine 340. For example, one or more output data 328A through 328N of neural engines 314 are used as the input 342 to planar engine 340. Likewise, the output 344 of planar engine 340 may be used as the input data 322A through 322N of neural engines 314. The inputs of neural engines 314 or planar engine 340 may be any data stored in buffer 334. For example, in various operating cycles, the source datasets from which one of the engines fetches as inputs may be different. The input of an engine may be an output of the same engine in previous cycles, outputs of different engines, or any other suitable source datasets stored in buffer 334. Also, a dataset in buffer 334 may be divided and sent to different engines for different operations in the next operating cycle. Two datasets in buffer 334 may also be joined for the next operation. The examiner notes that DUNNE and MILLS are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein a size of the first memory buffer is sufficient to store an output of any one of odd-numbered neuron layers of the MLM, the odd- numbered neuron layers of the MLM comprising the first neuron layer and the third neuron layer as taught by MILLS [0052] for feeding input data to corresponding neural engines [0052]).
Regarding Claim 5:
DUNNE teaches The method of claim 3, however, DUNNE is not relied upon to explicitly teach wherein a size of the second memory buffer is sufficient to store an output of any one of even-numbered neuron layers of the MLM, the even-numbered neuron layers of the MLM comprising the second neuron layer.
On the other hand, MILLS teaches wherein a size of the second memory buffer is sufficient to store an output of any one of even-numbered neuron layers of the MLM, the even-numbered neuron layers of the MLM comprising the second neuron layer ([0052] In one embodiment, buffer 334 is embodied as a non-transitory memory that can be accessed by neural engines 314 and planar engine 340. Buffer 334 may store input data 322A through 322N for feeding to corresponding neural engines 314A through 314N or planar engine 340, as well as output data 328A through 328N from each of neural engines 314A through 314N or planar engine 340 for feeding back into one or more neural engines 314 or planar engine 340, or sending to a target circuit (e.g., system memory 230). Buffer 334 may also store input data 342 and output data 344 of planar engine 340 and allow the exchange of data between neural engine 314 and planar engine 340. For example, one or more output data 328A through 328N of neural engines 314 are used as the input 342 to planar engine 340. Likewise, the output 344 of planar engine 340 may be used as the input data 322A through 322N of neural engines 314. The inputs of neural engines 314 or planar engine 340 may be any data stored in buffer 334. For example, in various operating cycles, the source datasets from which one of the engines fetches as inputs may be different. The input of an engine may be an output of the same engine in previous cycles, outputs of different engines, or any other suitable source datasets stored in buffer 334. Also, a dataset in buffer 334 may be divided and sent to different engines for different operations in the next operating cycle. Two datasets in buffer 334 may also be joined for the next operation. The examiner notes that DUNNE and MILLS are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein a size of the second memory buffer is sufficient to store an output of any one of even-numbered neuron layers of the MLM, the even-numbered neuron layers of the MLM comprising the second neuron layer as taught by MILLS [0052] for feeding input data to corresponding neural engines [0052]).
Regarding Claim 6:
DUNNE teaches The method of claim 1, however, DUNNE is not relied upon to explicitly teach wherein the first plurality of memory locations and the second plurality of memory locations are in a same memory buffer.
On the other hand, MILLS teaches wherein the first plurality of memory locations and the second plurality of memory locations are in a same memory buffer ([0052] In one embodiment, buffer 334 is embodied as a non-transitory memory that can be accessed by neural engines 314 and planar engine 340. Buffer 334 may store input data 322A through 322N for feeding to corresponding neural engines 314A through 314N or planar engine 340, as well as output data 328A through 328N from each of neural engines 314A through 314N or planar engine 340 for feeding back into one or more neural engines 314 or planar engine 340, or sending to a target circuit (e.g., system memory 230). Buffer 334 may also store input data 342 and output data 344 of planar engine 340 and allow the exchange of data between neural engine 314 and planar engine 340. For example, one or more output data 328A through 328N of neural engines 314 are used as the input 342 to planar engine 340. Likewise, the output 344 of planar engine 340 may be used as the input data 322A through 322N of neural engines 314. The inputs of neural engines 314 or planar engine 340 may be any data stored in buffer 334. For example, in various operating cycles, the source datasets from which one of the engines fetches as inputs may be different. The input of an engine may be an output of the same engine in previous cycles, outputs of different engines, or any other suitable source datasets stored in buffer 334. Also, a dataset in buffer 334 may be divided and sent to different engines for different operations in the next operating cycle. Two datasets in buffer 334 may also be joined for the next operation. The examiner notes that DUNNE and MILLS are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein the first plurality of memory locations and the second plurality of memory locations are in a same memory buffer as taught by MILLS [0052] for feeding input data to corresponding neural engines [0052]).
Regarding Claim 7:
DUNNE teaches The method of claim 6, however, DUNNE is not relied upon to explicitly teach wherein the same memory buffer is a cache buffer located on a processor chip of the processing device.
On the other hand, MILLS teaches wherein the same memory buffer is a cache buffer located on a processor chip of the processing device ([0051] Data processor circuit 318 manages data traffic and task performance of neural processor circuit 218. Data processor circuit 318 may include a flow control circuit 332 and a buffer 334. Buffer 334 is temporary storage for storing data associated with operations of neural processor circuit 218 and planar engine 340, such as input data that is transmitted from system memory 230 (e.g., data from a machine learning model) and other data that is generated within neural processor circuit 218 or planar engine 340. The data stored in data processor circuit 318 may include different subsets that are sent to various downstream components, such as neural engines 314 and planar engine 340. The examiner notes that DUNNE and MILLS are both directed to machine learning and both are reasonably analogous to the claimed invention.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified DUNNE’s machine learning model to incorporate wherein the same memory buffer is a cache buffer located on a processor chip of the processing device as taught by MILLS [0051] for feeding input data to corresponding neural engines [0052]).
Regarding claims 16-20:
Claims 16-20 are the system claims corresponding to the method claims 3-7 respectively. Therefore, claims 16-20 are rejected under 35 USC § 103 based upon the same rationale as claims 3-7 respectively.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
DE BROUWER (US20200293887A1)
“DE BROUWER teaches a federated learning model system for health care applications. The system for federated learning comprises multiple edge devices of end users, one or more federated learner update repository, and one or more cloud”
ZHANG (A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks)
“ZHANG teaches an efficient block-floating-point (BFP) arithmetic for large scale CNN models”
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/SHAMCY ALGHAZZY/Examiner, Art Unit 2128
/OMAR F FERNANDEZ RIVAS/Supervisory Patent Examiner, Art Unit 2128
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