Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendment filed on September 2, 2025.
Claims 1 – 3, 5, 7, 11, 15 16, and 20 have been amended.
Claims 4, 8 and 17 have been cancelled.
The rejections from the prior correspondence that are not restated herein are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/26/2025 has been entered.
Response to Arguments
With respect to 101:
Applicant argues:
Claims 1-20 stand rejected under 35 U.S.C. § 101 for allegedly being directed to non-statutory subject matter.
Applicant respectfully submits that limitations of the amended claim 1 cannot be performed in the human mind or using pen and paper. Amended claim 1 is directed to a practical application of improving memory operations of an edge computing device performing machine learning model computations with limited processing and/or memory resources. The amended claim 1 is similar to claims in Enfish, LLC v. Microsoft
Corp., 822 F.3d 1327, 118 USPQ2d 1684 (Fed. Cir. 2016) which were directed to specific improvements in how computers carry out one of their functions of storage and retrieval of data. Enfish, 822 F.3d at 1335-36. Like claims in Enfsh, the amended claim 1 is directed to an improvement of the ways memory devices handle integer data formats that are used in machine learning operations. Importantly, the instant claims are not directed to independently abstract ideas that exist outside computing devices that perform such operations.
Therefore, Applicant respectfully submits that amended claim 1 is not directed to an abstract idea. Independent claims 11 and 15 recite similar limitations. Therefore, for at least these reasons, the aforementioned independent claims should be deemed patent eligible.
Examiner’s Answer: Applicant argues that the claims provide an improvement to the ways a computer carries out a function.
The claim recites an identifying step, a rescaling step, and a processing step which can all be practically performed in the human mind but are recited as being performed by computing components. The courts, however, do not distinguish between claims that recite a mental process performed by humans and claims that recite mental processes. The inventive concept appears to be rooted in the abstract idea itself. Per MPEP 2106.05, I.: An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself." and per MPEP 2106.05(a) "It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.". The additional elements recited in the claims have been identified as Mere Instructions to Apply an Exception (MPEP 2106.05(f)) and Insignificant Extra Solution Activity (MPEP 2106.05(g)), as stated within this office action.
The courts have ruled that invoking the use of computers to perform an abstract idea and appending insignificant extra solution activity to the judicial exception do not integrate the judicial exception into a practical application. The additional elements identified as insignificant extra solution activity have been further analyzed to determine if the elements amount to significantly more than the judicial exception. The elements were determined to be performing computer functionality that has been found by the courts as well understood, routine, and conventional computer functions when claimed in a merely generic manner. It appears that the claimed invention is using generic computing components functioning in their normal capacity to enable the execution of a mental process. MPEP 2106.05(a), II.: "it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology." The claim recites an identifying step, a rescaling step, and a processing step which can all be practically performed in the human mind but are recited as being performed by computing components.
Accordingly, the recited judicial exceptions are not integrated into a practical application and the rejections under 35 U.S.C. 101 have been maintained, as stated in the rejection of this action.
With respect to 103:
Applicant’s arguments filed on September 2, 2025 have been fully considered but are moot because the arguments allege that only the newly added limitations are not taught by the prior art of record. It should be noted that a new prior art refence to Milletari combined with Khailany teaches the newly added limitations as shown in the rejections below.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed
to an abstract idea without significantly more. The following sections follow the 2019 PEG guidelines for analyzing subject matter eligibility.
The analysis below of the claims’ subject matter eligibility follows the 2019 Revised
Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50-57 (January 7, 2019) (“2019 PEG”)
and the 2024 Guidance Update on Patent Subject Matter Eligibility, Including on Artificial
Intelligence, 89 Fed. Reg. 58128-58138 (July 17, 2024) (“2024 AI SME Update”).
When considering subject matter eligibility under 35 U.S.C. 101, it must be determined
whether the claim is directed to one of the four statutory categories of invention, i.e., process,
machine, manufacture, or composition of matter (Step 1). If the claim does fall within one of the
statutory categories, the second step in the analysis is to determine whether the claim is directed
to a judicial exception (Step 2A). The Step 2A analysis is broken into two prongs. In the first
prong (Step 2A, Prong 1), it is determined whether or not the claims recite a judicial exception
(e.g., mathematical concepts, mental processes, certain methods of organizing human activity). If
it is determined in Step 2A, Prong 1 that the claims recite a judicial exception, the analysis
proceeds to the second prong (Step 2A, Prong 2), where it is determined whether or not the
claims integrate the judicial exception into a practical application. If it is determined at step 2A,
Prong 2 that the claims do not integrate the judicial exception into a practical application, the
analysis proceeds to determining whether the claim is a patent-eligible application of the
exception (Step 2B). If an abstract idea is present in the claim, any element or combination of
elements in the claim must be sufficient to ensure that the claim integrates the judicial exception
into a practical application, or else amounts to significantly more than the abstract idea itself.
Claim 1
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Step 2A Prong 1:
identifying a standard deviation of values stored in the first memory device (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; (Mathematical Concepts: are defined as mathematical relationships, mathematical formulas or equations, or mathematical calculations.)
processing, the first rescaled input data to obtain a first intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
obtaining, using the first intermediate data, a first classification of the first input data. (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
a first memory device configured to a store data in a floating point format, (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a second memory device configured to store data in an N-bit integer number format, and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a third memory device configured to store data in an M-bit integer number format wherein M is greater than N, the method comprising: (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
storing, in the first memory device, first input data into the MLM; (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
storing the first rescaled input data in the second memory device; (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, using a first neuron layer of the MLM (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing the first intermediate data in the third memory device and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
a first memory device configured to a store data in a floating point format, (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a second memory device configured to store data in an N-bit integer number format, and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a third memory device configured to store data in an M-bit integer number format wherein M is greater than N, the method comprising: (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
storing, in the first memory device, first input data into the MLM; (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
storing the first rescaled input data in the second memory device; (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, using a first neuron layer of the MLM (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing the first intermediate data in the third memory device and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
As an ordered whole, the claim is directed to method of converting and storing data, this is nothing more than using machine learning models to data processing. Nothing in the
claim provides significantly more than this. As such, the claim is not patent eligible.
Claim 2 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
wherein the first range of values comprises at least one of a minimum values of the first input data or a maximum value of the first input data. (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
The claim does not recite any additional limitations. Therefore, there are no additional elements to integrate the abstract ideas into a practical applications. (Merely asserting that a judicial exception is to be carried out on a generic computer (i.e., “data collecting or processing” of base claim 1) cannot meaningfully integrate the judicial exceptions into a practical application. See MPEP § 2106.05(f))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Mere instructions to apply an exception (i.e., “data collecting or processing” of base claim 1) cannot provide an inventive concept. The claim is not patent eligible.
Claim 3 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
wherein rescaling the first rescaled input data comprises imparting an offset to the first input data. (Mathematical Concepts: are defined as mathematical relationships, mathematical formulas or equations, or mathematical calculations.)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
The claim does not recite any additional limitations. Therefore, there are no additional elements to integrate the abstract ideas into a practical applications. (Merely asserting that a judicial exception is to be carried out on a generic computer (i.e., “data collecting or processing” of base claim 1) cannot meaningfully integrate the judicial exceptions into a practical application. See MPEP § 2106.05(f))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Mere instructions to apply an exception (i.e., “data collecting or processing” of base claim 1) cannot provide an inventive concept. The claim is not patent eligible.
Claim 5 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
wherein the N-bit integer number format comprises one or more of an 8-bit integer format or a 16-bit integer format. (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
The claim does not recite any additional limitations. Therefore, there are no additional elements to integrate the abstract ideas into a practical applications. (Merely asserting that a judicial exception is to be carried out on a generic computer (i.e., “data collecting or processing” of base claim 1) cannot meaningfully integrate the judicial exceptions into a practical application. See MPEP § 2106.05(f))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Mere instructions to apply an exception (i.e., “data collecting or processing” of base claim 1) cannot provide an inventive concept. The claim is not patent eligible.
Claim 6 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated. Please see the analysis of claim 1 above. Regarding the method steps recited in claim 1, these steps cover mental processes based on data processing and scaling.
Therefore, claim 6 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM. (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM. (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
Claim 7 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
identifying a third range of values associated with the first intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
identifying a fourth range of values associated with an integer number format of the first intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
obtaining a second rescaled input data by rescaling the first intermediate data based on a mapping of the third range of clause to the fourth range of values; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein obtaining the first classification of the first input data comprises: (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
processing the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtaining, using the second intermediate data, the first classification of the first input data (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein obtaining the first classification of the first input data comprises: (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
processing the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtaining, using the second intermediate data, the first classification of the first input data (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 9 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated. Please see the analysis of claim 1 above. Regarding the method steps recited in claim 1, these steps cover mental processes based on data processing and scaling.
Therefore, claim 9 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein the first input data comprises a digital representation of a sound. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein the first input data comprises a digital representation of a sound. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
The courts have found that generally linking the use of the judicial exceptions to a
particular technological environment or field of use does not qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 10 incorporates the rejections of claim 1.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
identifying a third range of values associated with the second input data (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
obtaining a second rescaled input data by rescaling the second input data based on a mapping of the third range of values to the second range of values (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
obtaining a second input data into the MLM; (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
processing the second rescaled input data using a first neuron layer of the MLM to obtain a second intermediate data (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtaining, using the first intermediate data, a second inference output of the MLM, the first inference output comprising a second classification of the second input data. (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
obtaining a second input data into the MLM; (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
processing the second rescaled input data using a first neuron layer of the MLM to obtain a second intermediate data (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtaining, using the first intermediate data, a second inference output of the MLM, the first inference output comprising a second classification of the second input data. (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 11
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Step 2A Prong 1:
processing the plurality of the input data to obtain a plurality of respective classifications of the input data, (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
identifying a standard deviation of values stored in the first memory device (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
rescaling the corresponding input data based on a mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
processing, using the rescaled input data, an inference output comprising a classification of the corresponding input data, (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
a first memory device supporting storage of data in a floating point format, (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a second memory device supporting storage of data in an N-bit integer number format, and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a third memory device supporting storage of data in an M-bit integer number format, wherein M is greater than N, (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
obtaining a plurality of sets of input data in a floating point format into the MLM, the MLM comprising parameters stored in the N-bit number format; and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
wherein processing of each of the plurality of the input data comprises: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing a corresponding input in the first memory device; (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
storing the rescaled input data in the second memory device and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
wherein obtaining the inference output comprises: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing intermediate data, obtained by processing by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, the rescaled input data in the third memory device. (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
a first memory device supporting storage of data in a floating point format, (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a second memory device supporting storage of data in an N-bit integer number format, and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a third memory device supporting storage of data in an M-bit integer number format, wherein M is greater than N, (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
obtaining a plurality of sets of input data in a floating point format into the MLM, the MLM comprising parameters stored in the N-bit number format; and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
processing the plurality of the input data to obtain a plurality of respective classifications of the input data, wherein processing of each of the plurality of the input data comprises: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing a corresponding input in the first memory device; (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
storing the rescaled input data in the second memory device and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
processing, using the rescaled input data, an inference output comprising a classification of the corresponding input data, wherein obtaining the inference output comprises: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
storing intermediate data, obtained by processing by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, the rescaled input data in the third memory device. (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
The courts have found that generally linking the use of the judicial exceptions to a
particular technological environment or field of use does not qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
As an ordered whole, the claim is directed to method of converting and storing data, this is nothing more than using machine learning models to data processing. Nothing in the
claim provides significantly more than this. As such, the claim is not patent eligible.
Claim 12 incorporates the rejections of claim 11.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 11 are incorporated. Please see the analysis of claim 11 above. Regarding the method steps recited in claim 11, these steps cover mental processes based on data processing and scaling.
Therefore, claim 12 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein the parameters stored in the N-bit integer number format comprise weights of a first neuron layer of the MLM. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein the parameters stored in the N-bit integer number format comprise weights of a first neuron layer of the MLM. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
The courts have found that generally linking the use of the judicial exceptions to a
particular technological environment or field of use does not qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 13 incorporates the rejections of claim 11.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 11 are incorporated. Please see the analysis of claim 11 above. Regarding the method steps recited in claim 11, these steps cover mental processes based on data processing and scaling.
Therefore, claim 13 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein each of the plurality of the input data is in a floating-point number format. (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein each of the plurality of the input data is in a floating-point number format. (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 14 incorporates the rejections of claim 11.
Step 1: The claim recites a method, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 11 are incorporated. Please see the analysis of claim 11 above. Regarding the method steps recited in claim 11, these steps cover mental processes based on data processing and scaling.
Therefore, claim 14 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein each of the plurality of the input data comprises a digital representation of a sound. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein each of the plurality of the input data comprises a digital representation of a sound. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
The courts have found that generally linking the use of the judicial exceptions to a
particular technological environment or field of use does not qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 15
Step 1: The claim recites a system, which is one of the four statutory categories of eligible matter.
Step 2A Prong 1:
identify a standard deviation of values stored in the first memory device; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
rescaling the input data based on a mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
perform arithmetic operations on N-bit inputs and generate M-bit outputs (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
process, the rescaled input data to obtain a first intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
obtain, using the intermediate data, a classification of the first input data. (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
a first memory device configured to store data in a floating point format, (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
a second memory device configured to store data in an N-bit integer number format, and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a third memory device configured to store data in an M-bit integer number format, wherein M is greater than N; and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
a processing device configured to communicatively coupled to the memory subsystem, the processing device to: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
store, in the first memory device, input data into a machine learning model (MLM); (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
store the rescaled input in the second memory device (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
by the processing device, using a first neuron layer of the MLM (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
store the rescaled input data in the third memory device; and (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
a first memory device configured to store data in a floating point format, (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
a second memory device configured to store data in an N-bit integer number format, and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a third memory device configured to store data in an M-bit integer number format, wherein M is greater than N; and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
a processing device configured to communicatively coupled to the memory subsystem, the processing device to: (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
store, in the first memory device, input data into a machine learning model (MLM); (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
store the rescaled input in the second memory device (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
by the processing device, using a first neuron layer of the MLM (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
store the rescaled input data in the third memory device; and (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
As an ordered whole, the claim is directed to system of converting and storing data, this is nothing more than using machine learning models to data processing. Nothing in the
claim provides significantly more than this. As such, the claim is not patent eligible.
Claim 16 incorporates the rejections of claim 15.
Step 1: The claim recites a system, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 15 are incorporated. Please see the analysis of claim 15 above. Regarding the system steps recited in claim 15, these steps cover mental processes based on data processing and scaling.
Therefore, claim 16 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein to obtain the rescaled input data, the processing device is further to impart an offset to the input data. (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein to obtain the rescaled input data, the processing device is further to impart an offset to the input data. (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
Claim 18 incorporates the rejections of claim 15.
Step 1: The claim recites a system, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 1 are incorporated.
wherein the N-bit integer number format comprises one or more of an 8-bit integer format or a 16-bit integer format. (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
The claim does not recite any additional limitations. Therefore, there are no additional elements to integrate the abstract ideas into a practical applications. (Merely asserting that a judicial exception is to be carried out on a generic computer (i.e., “data collecting or processing” of base claim 1) cannot meaningfully integrate the judicial exceptions into a practical application. See MPEP § 2106.05(f))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Mere instructions to apply an exception (i.e., “data collecting or processing” of base claim 1) cannot provide an inventive concept. The claim is not patent eligible.
Claim 19 incorporates the rejections of claim 15.
Step 1: The claim recites a system, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 15 are incorporated. Please see the analysis of claim 15 above. Regarding the method steps recited in claim 15, these steps cover mental processes based on data processing and scaling.
Therefore, claim 19 is directed to an abstract idea – Mental Processes (i.e., can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM. (Field of use and technological environment, it does no more than generally link a judicial exception to a particular technological environment. MPEP § 2106.05(h))
The courts have found that generally linking the use of the judicial exceptions to a
particular technological environment or field of use does not qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim 20 incorporates the rejections of claim 15.
Step 1: The claim recites a system, which is one of the four statutory categories of eligible matter.
Steps 2A Prong 1: The judicial exceptions of claim 15 are incorporated.
identify a third range of values associated with intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
identify a fourth range of values associated with an integer number format of the intermediate data; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
obtain a second rescaled input data by rescaling the intermediate data based on a mapping of the third range of values to the fourth range of values; (Mental Processes: Can be performed in the human mind, or by a human using a pen and paper, making observations, evaluations and judgments as claimed)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application. In particular, the claim recites these additional elements:
wherein to obtain the inference output of the MLM, the processing device is to: (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
process the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtain, using the second intermediate data, the classification of the input data. (Mere data gathering, Insignificant extra solution activity in MPEP § 2106.05(g))
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
wherein to obtain the inference output of the MLM, the processing device is to: (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
process the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and (Mere instructions to apply an exception as it recites only the idea of a solution or outcome as discussed in MPEP § 2106.05(f))
obtain, using the second intermediate data, the classification of the input data. (receiving or transmitting data, using components and functions claimed at a high level of generality have been determined by the courts as being well-understood, routine, and conventional activities in the field of computer functions (See MPEP § 2106.05(d)(II)(i))
The courts have found that adding the words "apply it" (or an equivalent) with the
judicial exception, or mere instructions to implement an abstract idea on a computer does not
qualify as “significantly more”. (See MPEP § 2106.05(I)(A))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 11 – 13, 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Milletari (US 11804050 B1) in view of Khailany (US 20220067512 A1)
Regarding claim 1, Milletari teaches A method to operate a memory system of an edge computing device (ECD) deploying a trained machine learning model (MLM) the memory system comprising: (C58:L26 – 61): computer system 1800 includes, without limitation, a main memory 1804 [memory system of an edge computing device (ECD)] and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1804 which may take form of random access memory (“RAM”). …In at least one embodiment, one or more of client devices 502 [edge computing device (ECD)], … methods described herein [A method to operate] may be implemented at least partially on one or more computer system 1800 of FIG. 18. (C21:L22 – 27): contribution determiner 130 may determine a contribution score for training node 102A and/or a client corresponding to client device 502A [edge computing device (ECD)] based on a contribution from training node 102A to collaboratively training machine learning model(s) 108. [a trained machine learning model (MLM)]
a first memory device configured to store data in a floating point format (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C55:L40 – 43): In at least one embodiment, register file 1606 may store different types of data in various registers including, without limitation, integer registers, floating point registers [store data in a floating point format], status registers, and instruction pointer register.
a second memory device configured to store data in an N-bit integer number format, and (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device [a second memory device], and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C101:L4 – 9): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially using one or more of execution logic 3400. (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. [store data in an N-bit integer number format]
a third memory device configured to store data in an M-bit integer number format, wherein M is greater than N, the method comprising: (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device, and the one or more circuits are of a third edge device. [a third memory device] (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C86:L49 – 54): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on one or more processor 2800. (C85:L54 – 58): In at least one embodiment, memory load/store operations may be executed by AGUS 2812, 2814. In at least one embodiment, fast ALU 2816, fast ALU 2818, and slow ALU 2820 may perform integer operations on 64-bit data operands. [store data in an M-bit integer number format, wherein M is greater than N]
storing, in the first memory device, first input data into the MLM; (C6:L62 – 1): In at least one embodiment code and/or data storage 201 stores weight parameters and/or input/output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input/output data and/or weight parameters during training and/or inferencing using aspects of one or more embodiments.
identifying a standard deviation of values stored in the first memory device (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C16:L53 – 57): In at least one embodiment, a maxima point(s), or a cutoff(s) for contribution scores, may be correspond to one or more standard deviations [identifying a standard deviation] or percentiles from a maximum value of a model of parameter values from training nodes 102. [values stored in the first memory device]
the (C87:L67 – 2): In at least one embodiment, neuromorphic processor 3000 may receive one or more inputs from sources external to neuromorphic processor 3000. (C12:L48 – 51): In at least one embodiment, portions of machine learning models 106 may be grouped into sets using unsupervised grouping or clustering of model portions (e.g., based on neuron activations). (C75:L29 – 33): In at least one embodiment, intermediate data produced [obtain a first intermediate data] by one or more of clusters 2514A-2514N may be stored in buffers to allow intermediate data to be transmitted between clusters 2514A-2514N for further processing.
storing the first intermediate data in the third memory device; and (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device, and the one or more circuits are of a third edge device. [a third memory device] (C75:L29 – 33): In at least one embodiment, intermediate data produced by one or more of clusters 2514A-2514N may be stored in buffers to allow intermediate data to be transmitted between clusters 2514A-2514N for further processing. [storing the first intermediate data] (C76:L27 – 31): In at least one embodiment, each cluster 2514A-2514N can communicate with memory interface 2518 through memory crossbar 2516 to read from or write to various external memory devices. [storing the third memory device]
Milletari does not teach rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; storing the first rescaled input data in the second memory device processing, by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, obtaining, using the first intermediate data, a first classification of the first input data.
Khailany teaches rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; (0028 - 29): A convolution operator 102 applies K kernels (C×R×S) of a weight tensor 103 to an input activation tensor 101 (C×H×W) to produce an output activation tensor 104. Quantization scales high-precision values of a particular range [a first range of values] to lower-precision values of a different range. [second range of] where s is the scale factor and Q(a, b) is the function that quantizes a to a b-bit integer.[values supported by the second memory device] (0053): In an embodiment the first multi-dimensional [first range of values] parameter input tensor comprises first inputs [the first input data] that are weights and a second multi-dimensional parameter input tensor comprises second inputs that are input activations. (0038): As a result, a calibration process is used to select the a used in Equation 1 for quantizing weights and activations. While a can be set to the maximum absolute value of the distribution (called max calibration) [a predetermined number of the identified standard deviations], it is often beneficial to omit outlier values in favor of additional precision for inlier values.
storing the first rescaled input data in the (0166): A client device can include resources such as a processor 528 and memory 562 for generating a request and processing results [storing the first rescaled input data] or a response, as well as at least one data storage element 552 for storing data for machine learning application 526.
processing, by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs, (0166): A client device can include resources such as a processor [processing, by a processing device of the ECD] 528 and memory 562 for generating a request and processing results or a response, as well as at least one data storage element 552 for storing data for machine learning application 526. (0051): A multiplier 127, multiplies the vector dot-product value by the scale product factor to increase the number of bits [perform arithmetic operations on N-bit inputs] representing the vector dot-product value, producing a scaled vector dot-product value. In an embodiment, increasing M and/or N may increase the precision of the output activations. [generate M-bit outputs]
obtaining, using the first intermediate data, a first classification of the first input data. (0166): This request can include, for example, input data to be processed using a neural network to obtain one or more inferences [obtaining, using the first intermediate data] or other output values, classifications, [obtaining, a first classification of the first input data.] or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. (0006): The reduced precision vectors [first intermediate data] of parameters are processed by a layer of the neural network model to produce output values [obtaining, using the first intermediate data] (Examiner notes: the values used to produce the output values as claimed intermediate)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari and Khailany before them, to include Khailany’s classifying input data and obtaining intermediate data which would allow Milletari’s method to use classified data along with intermediate data. One would have been motivated to make such a combination in order to increase the accuracy of the model including bit precision, as suggested by Khailany (US 20220067512 A1) (0051)
Regarding claim 2, Milletari teach the method of claim 1.
Milletari does not teach wherein the first range of values comprises at least one of a minimum value of the first input data or a maximum value of the first input data.
Khailany teaches wherein the first range of values comprises at least one of a minimum value of the first input data or a maximum value of the first input data. (0036): An N-bit signed two's complement integer quantization maps real values x∈|x.sub.min, [minimum value of the first input data] x.sub.max| [maximum value of the first input data] to values x.sub.q∈[−2.sup.N-1, 2.sup.N-1−1].
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari and Khailany before them, to include Khailany’s classifying input data and obtaining intermediate data which would allow Milletari’s method to use classified data along with intermediate data. One would have been motivated to make such a combination in order to increase the accuracy of the model including bit precision, as suggested by Khailany (US 20220067512 A1) (0051)
Regarding claim 5, Milletari and Khailany teach the method of claim 1. Milletari further teaches wherein the N-bit integer number format comprises one or more of an 8-bit integer format or a 16-bit integer format (C100:L39 – 42): In at least one embodiment FPU(s) 3434 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations
Regarding claim 6, Milletari and Khailany teach the method of claim 1. Milletari further teaches wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. (C100:L65 – 3): In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory [a format used to store weights of the first neuron layer of the MLM] and/or registers (shown or not shown) that configure ALUs of execution logic 3400 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.
Regarding claim 11, Milleteri teaches A method to operate a memory system of an edge computing device (ECD) deploying a trained machine learning model (MLM) the memory system comprising: (C58:L26 – 61): computer system 1800 includes, without limitation, a main memory 1804 [memory system of an edge computing device (ECD)] and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1804 which may take form of random access memory (“RAM”). …In at least one embodiment, one or more of client devices 502 [edge computing device (ECD)], … methods described herein [A method to operate] may be implemented at least partially on one or more computer system 1800 of FIG. 18. (C21:L22 – 27): contribution determiner 130 may determine a contribution score for training node 102A and/or a client corresponding to client device 502A [edge computing device (ECD)] based on a contribution from training node 102A to collaboratively training machine learning model(s) 108. [a trained machine learning model (MLM)]
a first memory device supporting storage of data in a floating point format, (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C55:L40 – 43): In at least one embodiment, register file 1606 may store different types of data in various registers including, without limitation, integer registers, floating point registers [storage of data in a floating point format], status registers, and instruction pointer register.
a second memory device supporting storage of data in an N-bit integer number format, and (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device [a second memory device], and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C101:L4 – 9): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially using one or more of execution logic 3400. (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. [storage of data in an N-bit integer number format]
a third memory device supporting storage of data in an M-bit integer number format, wherein M is greater than N, the method comprising: (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device, and the one or more circuits are of a third edge device. [a third memory device] (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C86:L49 – 54): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on one or more processor 2800. (C85:L54 – 58): In at least one embodiment, memory load/store operations may be executed by AGUS 2812, 2814. In at least one embodiment, fast ALU 2816, fast ALU 2818, and slow ALU 2820 may perform integer operations on 64-bit data operands. [storage of data in an M-bit integer number format, wherein M is greater than N]
obtaining a plurality of sets of input data in a floating point format into the MLM, the MLM comprising parameters stored in the N-bit integer number format; and (C109:L20 – 23): In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices [obtaining a plurality of sets of input data in a floating point format into the MLM] and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. [the MLM comprising parameters stored in the N-bit integer number format]
storing a corresponding input data in the first memory device; (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C55:L40 – 43): In at least one embodiment, register file 1606 may store different types of data in various registers [storing a corresponding input data] including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.
identifying a standard deviation of values stored in the first memory device (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C16:L53 – 57): In at least one embodiment, a maxima point(s), or a cutoff(s) for contribution scores, may be correspond to one or more standard deviations [identifying a standard deviation] or percentiles from a maximum value of a model of parameter values from training nodes 102. [values stored in the first memory device]
storing intermediate data, (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device, and the one or more circuits are of a third edge device. [a third memory device] (C75:L29 – 33): In at least one embodiment, intermediate data produced by one or more of clusters 2514A-2514N may be stored in buffers to allow intermediate data to be transmitted between clusters 2514A-2514N for further processing. [storing the first intermediate data] (C76:L27 – 31): In at least one embodiment, each cluster 2514A-2514N can communicate with memory interface 2518 through memory crossbar 2516 to read from or write to various external memory devices. [storing the third memory device]
Milletari does not teach processing the plurality of the input data to obtain a plurality of respective classifications of the input data, wherein processing of each of the plurality of the input data comprises: rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; storing the first rescaled input data in the second memory device, processing, using the rescaled input data, an inference output comprising a classification of the corresponding input data, wherein obtaining the inference output comprises: obtained by processing by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs
processing the plurality of the input data to obtain a plurality of respective classifications of the input data, wherein processing of each of the plurality of the input data comprises: (0166): This request can include, for example, input data to be processed [processing the plurality of the input data] using a neural network to obtain one or more inferences or other output values, classifications [obtain a plurality of respective classifications of the input data], or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well.
rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; (0028 - 29): A convolution operator 102 applies K kernels (C×R×S) of a weight tensor 103 to an input activation tensor 101 (C×H×W) to produce an output activation tensor 104. Quantization scales high-precision values of a particular range [a first range of values] to lower-precision values of a different range. [second range of] where s is the scale factor and Q(a, b) is the function that quantizes a to a b-bit integer.[values supported by the second memory device] (0053): In an embodiment the first multi-dimensional [first range of values] parameter input tensor comprises first inputs [the first input data] that are weights and a second multi-dimensional parameter input tensor comprises second inputs that are input activations. (0038): As a result, a calibration process is used to select the a used in Equation 1 for quantizing weights and activations. While a can be set to the maximum absolute value of the distribution (called max calibration) [a predetermined number of the identified standard deviations], it is often beneficial to omit outlier values in favor of additional precision for inlier values.
storing the first rescaled input data in the (0166): A client device can include resources such as a processor 528 and memory 562 for generating a request and processing results [storing the first rescaled input data] or a response, as well as at least one data storage element 552 for storing data for machine learning application 526.
processing, using the rescaled input data, an inference output comprising a classification of the corresponding input data, wherein obtaining the inference output comprises: (0094): At step 340, the neural network processes the first multi-dimensional input tensor and a second multi-dimensional input tensor [using the rescaled input data] to produce a multi-dimensional output tensor, where the neural network model is configured by the quantized parameters to perform a task. In an embodiment, the task is at least one of segmentation and/or classification. [an inference output comprising a classification of the corresponding input data]
obtained by processing by a processing device of the ECD configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs (0166): A client device can include resources such as a processor [processing, by a processing device of the ECD] 528 and memory 562 for generating a request and processing results or a response, as well as at least one data storage element 552 for storing data for machine learning application 526. (0051): A multiplier 127, multiplies the vector dot-product value by the scale product factor to increase the number of bits [perform arithmetic operations on N-bit inputs] representing the vector dot-product value, producing a scaled vector dot-product value. In an embodiment, increasing M and/or N may increase the precision of the output activations. [generate M-bit outputs]
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari and Khailany before them, to include Khailany’s classifying input data and obtaining intermediate data which would allow Milletari’s method to use classified data along with intermediate data. One would have been motivated to make such a combination in order to increase the accuracy of the model including bit precision, as suggested by Khailany (US 20220067512 A1) (0051)
Regarding claim 12, Milletari and Khailany teach the method of claim 11. Milletari further teaches wherein the parameters stored in the N-bit integer number format comprise weights of a first neuron layer of the MLM. (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. (C100:L65 – 3): In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory [the parameters stored in the N-bit integer number format comprise weights] and/or registers (shown or not shown) that configure ALUs of execution logic 3400 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.
Regarding claim 13, Milletari and Khailany teach the method of claim 11. Milletari further teaches wherein each of the plurality of the input data is in a floating-point number format. (C109:L20 – 23): In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices.
Regarding claim 15, Milletari teaches a first memory device configured to store data in a floating point format (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C55:L40 – 43): In at least one embodiment, register file 1606 may store different types of data in various registers including, without limitation, integer registers, floating point registers [store data in a floating point format], status registers, and instruction pointer register.
a second memory device configured to store data in an N-bit integer number format, and (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device [a second memory device], and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C101:L4 – 9): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially using one or more of execution logic 3400. (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. [store data in an N-bit integer number format]
a third memory device configured to store data in an M-bit integer number format, wherein M is greater than N; and (Claim 13): wherein the first processor is of a first edge device, the second processor is of a second edge device, and the one or more circuits are of a third edge device. [a third memory device] (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C86:L49 – 54): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on one or more processor 2800. (C85:L54 – 58): In at least one embodiment, memory load/store operations may be executed by AGUS 2812, 2814. In at least one embodiment, fast ALU 2816, fast ALU 2818, and slow ALU 2820 may perform integer operations on 64-bit data operands. [store data in an M-bit integer number format, wherein M is greater than N]
store, in the first memory device, input data into a machine learning model (MLM); (C6:L62 – 1): In at least one embodiment code and/or data storage 201 stores weight parameters and/or input/output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input/output data and/or weight parameters during training and/or inferencing using aspects of one or more embodiments.
identifying a standard deviation of values stored in the first memory device (Claim 13): wherein the first processor is of a first edge device [a first memory device], the second processor is of a second edge device, and the one or more circuits are of a third edge device. (C19:L51 – 52): In at least one embodiment, one or more client devices 502 correspond to an edge device (C56:L63 – 67): In at least one embodiment, one or more of client devices 502, aggregation server(s) 504, training nodes 102, training aggregator 104, parameter reviewer(s) 1102, and/or review aggregator(s) 1110 and/or methods described herein may be implemented at least partially on system 1600 of FIG. 16. (C16:L53 – 57): In at least one embodiment, a maxima point(s), or a cutoff(s) for contribution scores, may be correspond to one or more standard deviations [identifying a standard deviation] or percentiles from a maximum value of a model of parameter values from training nodes 102. [values stored in the first memory device]
process, by the processing device, the (C87:L67 – 2): In at least one embodiment, neuromorphic processor 3000 may receive one or more inputs from sources external to neuromorphic processor 3000. (C12:L48 – 51): In at least one embodiment, portions of machine learning models 106 may be grouped into sets using unsupervised grouping or clustering of model portions (e.g., based on neuron activations). (C75:L29 – 33): In at least one embodiment, intermediate data produced [obtain a first intermediate data] by one or more of clusters 2514A-2514N may be stored in buffers to allow intermediate data to be transmitted between clusters 2514A-2514N for further processing.
Khailany teaches a processing device configured to perform arithmetic operations on N-bit inputs and generate M-bit outputs and communicatively coupled to the memory subsystem, the processing device to:
rescaling the first input data based on mapping from a first range of values associated with a predetermined number of the identified standard deviations to a second range of values supported by the second memory device; (0028 - 29): A convolution operator 102 applies K kernels (C×R×S) of a weight tensor 103 to an input activation tensor 101 (C×H×W) to produce an output activation tensor 104. Quantization scales high-precision values of a particular range [a first range of values] to lower-precision values of a different range. [second range of] where s is the scale factor and Q(a, b) is the function that quantizes a to a b-bit integer.[values supported by the second memory device] (0053): In an embodiment the first multi-dimensional [first range of values] parameter input tensor comprises first inputs [the first input data] that are weights and a second multi-dimensional parameter input tensor comprises second inputs that are input activations. (0038): As a result, a calibration process is used to select the a used in Equation 1 for quantizing weights and activations. While a can be set to the maximum absolute value of the distribution (called max calibration) [a predetermined number of the identified standard deviations], it is often beneficial to omit outlier values in favor of additional precision for inlier values.
store the first rescaled input data in the (0166): A client device can include resources such as a processor 528 and memory 562 for generating a request and processing results [store the first rescaled input data] or a response, as well as at least one data storage element 552 for storing data for machine learning application 526.
storing the first rescaled input data in the (0166): A client device can include resources such as a processor 528 and memory 562 for generating a request and processing results [storing the first rescaled input data] or a response, as well as at least one data storage element 552 for storing data for machine learning application 526.
obtain, using the intermediate data, a classification of the first input data. (0166): This request can include, for example, input data to be processed using a neural network to obtain one or more inferences [obtaining, using the intermediate data] or other output values, classifications, [obtain, a classification of the first input data.] or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. (0006): The reduced precision vectors [intermediate data] of parameters are processed by a layer of the neural network model to produce output values [obtaining, using the intermediate data] (Examiner notes: the values used to produce the output values as claimed intermediate)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari and Khailany before them, to include Khailany’s classifying input data and obtaining intermediate data which would allow Milletari’s method to use classified data along with intermediate data. One would have been motivated to make such a combination in order to increase the accuracy of the model including bit precision, as suggested by Khailany (US 20220067512 A1) (0051)
Regarding claim 18, Milletari and Khailany teach the system of claim 15. Milletari further teaches wherein the N-bit integer number format comprises one or more of an 8-bit integer format or a 16-bit integer format (C100:L39 – 42): In at least one embodiment FPU(s) 3434 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations
Regarding claim 19, Milletari and Khailany teach the system of claim 15. Milletari further teaches wherein the N-bit integer number format is a format used to store weights of the first neuron layer of the MLM. (C100:L6 – 15): In at least one embodiment, graphics execution unit 3408 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3422 of graphics execution unit thread 3408 can dispatch instructions to one of send unit 3430, branch unit 3442, or SIMD FPU(s) 3434 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3424, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit [wherein the N-bit integer number format] data elements. (C100:L65 – 3): In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory [is a format used to store weights of the first neuron layer of the MLM] and/or registers (shown or not shown) that configure ALUs of execution logic 3400 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Milletari (US 11804050 B1) in view of Khailany (US 20220067512 A1) further in view of Zhao (US 20220237336 A1)
Regarding claim 3, Milletari teach the method of claim 1.
Milletari and Khailany do not teach wherein rescaling the first rescaled input data comprises imparting an offset to the first input data.
Zhao teaches wherein rescaling the first rescaled input data comprises imparting an offset to the first input data. (0190): Exemplary registers that may be initialized by a hypervisor are shown in Table 1. (Examiner’s notes: Table 1 states the application of an Interrupt Vector Table Entry Offset, this offset would be applied to the incoming instructions in claim 1 thus imparting an offset to the input data.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Zhao before them, to include Zhao’s offsetting of data which would allow Milletari and Khailany’s method to improve the training process. One would have been motivated to make such a combination in order to verify the correctness and completion of the provided data, as suggested by Zhao (US 20220237336 A1) (0385)
Regarding claim 16, Milletari teach the system of claim 15.
Milletari and Khailany do not teach wherein obtain the rescaled input data, the processing device is further to impart an offset to the input data.
Zhao teaches wherein obtain the rescaled input data, the processing device is further to impart an offset to the input data. (0190): Exemplary registers that may be initialized by a hypervisor are shown in Table 1. (Examiner’s notes: Table 1 states the application of an Interrupt Vector Table Entry Offset, this offset would be applied to the incoming instructions in claim 1 thus imparting an offset to the input data.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Zhao before them, to include Zhao’s offsetting of data which would allow Milletari and Khailany’s system to improve the training process. One would have been motivated to make such a combination in order to verify the correctness and completion of the provided data, as suggested by Zhao (US 20220237336 A1) (0385)
Claims 7, 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Milletari (US 11804050 B1) in view of Khailany (US 20220067512 A1) further in view of Georgescu (US 20150238148 A1) formerly referred to as “Siemens” in the Final Rejection mailed out on 6/30/2025
Regarding claim 7, Milletari teach the method of claim 1.
Milletari does not teach wherein obtaining the first classification of the first input data comprises: identifying a third range of values associated with the first intermediate data; identifying a fourth range of values associated with an integer number format of the first intermediate data; obtaining a second rescaled input data by rescaling the first intermediate data based on a mapping of the third range of values to the fourth range of values; processing the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and obtaining, using the second intermediate data, the first classification of the first input data.
Khailany teaches wherein obtaining the first classification of the first input data comprises: identifying a (0166): This request can include, for example, input data to be processed using a neural network to obtain one or more inferences or other output values, classifications, [obtaining, a first classification of the first input data.] or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. (0160): Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, detect emotions, identify recommendations, recognize and translate speech, and generally infer new information. [identifying a
identifying a (0053): In an embodiment the first multi-dimensional parameter input tensor [identifying a comprises first inputs that are input activations [associated with an integer number format of the first intermediate data;] and a second multi-dimensional parameter input tensor comprises second inputs that are weights.
obtaining a second rescaled input data by rescaling the first intermediate data based on a mapping of the (0029): Quantization scales high-precision values [rescaling the first intermediate data based on a mapping of the of a particular range to lower-precision values of a different range. [obtaining a second rescaled input data]
processing the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and (0053): In an embodiment the first multi-dimensional parameter input tensor comprises first inputs that are weights and a second multi-dimensional parameter input tensor [second neuron layer of the MLM to obtain a second intermediate data] comprises second inputs that are input activations. [processing the second rescaled input data]
obtaining, using the second intermediate data, the first classification of the first input data. (0094): the neural network processes the first multi-dimensional input tensor and a second multi-dimensional input tensor to produce a multi-dimensional output tensor, where the neural network model is configured by the quantized parameters to perform a task. In an embodiment, the task is at least one of segmentation and/or classification.
Milletari and Khailany do not teach a third and fourth range of values
Georgescu teaches third range of values associated with the first intermediate data, identifying a fourth range of values associated with an integer number format of the first intermediate data and mapping of the third range of values to the fourth range of values (0028): At step 112, the method proceeds to the next marginal search space and then returns to step 106 and repeats steps 106, 108, and 110. In particular, when the method returns to step 106, the hypotheses in the previous search space [third range of values associated with the first intermediate data] are evaluated using the deep neural network trained for the previous search space to determine candidates in the previous search space, and training samples (hypotheses) for the next search space are generated [third range of values associated with the first intermediate data, identifying a fourth … the third range of values to the fourth range of values] by augmenting the candidates in the previous search space with additional parameters for the next search space. [mapping of the third range of values to the fourth range of values]
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Georgescu before them, to include Georgescu’s multiple ranges in a neural network which would allow Milletari and Khailany’s method to neural network quantization. One would have been motivated to make such a combination in order to account for a plurality of ranges beyond two, as suggested by Georgescu (US 20150238148 A1) (0034)
Regarding claim 10, Milletari teach the method of claim 1.
Milletari does not teach obtaining a second input data into the MLM; identifying a third range of values associated with the second input data; obtaining a second rescaled input data by rescaling the second input data based on a mapping of the third range of values to the second range of values; processing the second rescaled input data using a first neuron layer of the MLM to obtain a second intermediate data; and obtaining, using the first intermediate data, a second inference output of the MLM, the first inference output comprising a second classification of the second input data.
Khailany teaches obtaining a second input data into the MLM; (0053): In an embodiment the first multi-dimensional parameter input tensor comprises first inputs that are weights and a second multi-dimensional parameter input tensor comprises second inputs [obtaining a second input data into the MLM] that are input activations.
identifying a (0053): In an embodiment the first multi-dimensional parameter input tensor comprises first inputs that are weights and a second multi-dimensional parameter input tensor comprises [identifying a second inputs [associated with the second input data] that are input activations.
obtaining a second rescaled input data by rescaling the second input data based on a mapping of the (0071): Returning to FIG. 2B, at step 240, for each vector of parameters, a precision of each parameter in the vector of parameters is reduced according to a corresponding scale factor to generate a reduced precision [rescaling the second input data based on a mapping of the third range of values to the second range of values] (e.g., quantized) vector of parameters. [obtaining a second rescaled input data]
processing the second rescaled input data using a first neuron layer of the MLM to obtain a second intermediate data; and (0071): At step 245, the reduced precision vectors [processing the second rescaled input data using a first neuron layer of the MLM to obtain a second intermediate data] of parameters are processed by a layer of the neural network model to produce output values. [MLM to obtain a second intermediate data] (Examiner’s note: the value used to produce the output values as claimed intermediate data)
obtaining, using the first intermediate data, a second inference output of the MLM, the first inference output comprising a second classification of the second input data. (0166): This request can include, for example, input data to be processed using a neural network to obtain one or more inferences [obtaining, using the first intermediate data, a second inference output of the MLM] or other output values, classifications, [the first inference output comprising a second classification of the second input data] or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. (0071): In an embodiment, the parameter quantization unit 215 reduces the precision of each parameter in the vector according to the corresponding scale factor provided by the vector max unit 205. At step 245, the reduced precision vectors of parameters are processed [processing the second rescaled input data using a first neuron layer] by a layer of the neural network model [MLM to obtain a second intermediate data] to produce output values. In an embodiment, the output values are output activations. [obtaining, using the first intermediate data;] Examiner’s note: the value used to produce the output values as claimed intermediate data
Milletari and Khailany do not teach a third range of values
Georgescu teaches identifying a third range of values associated with the second input data and mapping of the third range of values to the second range of values (0034): As described above in step 106, hypotheses are generated in the current search space. For the first search space, the hypotheses are generated directly from the current range [identifying a third range of values associated with the second input data], and for the other search spaces, the hypotheses are generated from the current hypotheses set augments with additional parameters [mapping of the third range of values to the second range of values] which are sampled from the current corresponding range.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Georgescu before them, to include Georgescu’s multiple ranges in a neural network which would allow Milletari and Khailany’s method to neural network quantization. One would have been motivated to make such a combination in order to account for a plurality of ranges beyond two, as suggested by Georgescu (US 20150238148 A1) (0034)
Regarding claim 20, Milletari teach the system of claim 15.
Milletari does not teach wherein to obtain the output of the MLM, the processing device is to: identify a third range of values associated with the intermediate data; identify a fourth range of values associated with an integer number format of the intermediate data; obtain a second rescaled input data by rescaling the intermediate data based on a mapping of the third range of values to the fourth range of values; process the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and obtain, using the second intermediate data, the first classification of the input data.
Khailany teaches wherein to obtain the output of the MLM, the processing device is to: identify a (0166): This request can include, for example, input data to be processed using a neural network to obtain one or more inferences or other output values, classifications, or predictions, or for at least one embodiment, input data can be received by interface layer 508 and directed to inference module 518, although a different system or service can be used as well. (0160): Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, detect emotions, identify recommendations, recognize and translate speech, and generally infer new information. [identify a
identify a (0053): In an embodiment the first multi-dimensional parameter input tensor [identify a comprises first inputs that are input activations [associated with an integer number format of the intermediate data;] and a second multi-dimensional parameter input tensor comprises second inputs that are weights.
obtain a second rescaled input data by rescaling the intermediate data based on a mapping of the (0029): Quantization scales high-precision values [rescaling the first intermediate data based on a mapping of the of a particular range to lower-precision values of a different range. [obtain a second rescaled input data]
process the second rescaled input data using a second neuron layer of the MLM to obtain a second intermediate data; and (0053): In an embodiment the first multi-dimensional parameter input tensor comprises first inputs that are weights and a second multi-dimensional parameter input tensor [second neuron layer of the MLM to obtain a second intermediate data] comprises second inputs that are input activations. [processing the second rescaled input data]
obtain, using the second intermediate data, the classification of the input data. (0094): the neural network processes the first multi-dimensional input tensor and a second multi-dimensional input tensor to produce a multi-dimensional output tensor, where the neural network model is configured by the quantized parameters to perform a task. In an embodiment, the task is at least one of segmentation and/or classification.
Milletari and Khailany do not teach a third and fourth range of values
Georgescu teaches third range of values associated with the first intermediate data, identifying a fourth range of values associated with an integer number format of the first intermediate data and mapping of the third range of values to the fourth range of values (0028): At step 112, the method proceeds to the next marginal search space and then returns to step 106 and repeats steps 106, 108, and 110. In particular, when the method returns to step 106, the hypotheses in the previous search space [third range of values associated with the first intermediate data] are evaluated using the deep neural network trained for the previous search space to determine candidates in the previous search space, and training samples (hypotheses) for the next search space are generated [third range of values associated with the first intermediate data, identifying a fourth … the third range of values to the fourth range of values] by augmenting the candidates in the previous search space with additional parameters for the next search space. [mapping of the third range of values to the fourth range of values]
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Georgescu before them, to include Georgescu’s multiple ranges in a neural network which would allow Milletari and Khailany’s method to neural network quantization. One would have been motivated to make such a combination in order to account for a plurality of ranges beyond two, as suggested by Georgescu (US 20150238148 A1) (0034)
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Milletari (US 11804050 B1) in view of Khailany (US 20220067512 A1) further in view of Zanbaghi (US 20170047939 A1) formerly referred to as “Cirrus” in the Final Rejection mailed out on 6/30/2025
Regarding claim 9, Milletari and Khailany teach the method of claim 1.
Milletari and Khailany do not teach wherein the first input data comprises a digital representation of a sound.
Zanbaghi teaches a digital representation of a sound. (0052): When a microphone is coupled to the first input and the second input, this digital signal is a digital representation of sounds in an environment around the microphone.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Zanbaghi before them, to include Zanbaghi digital representation of sound which would allow Milletari and Khailany’s method to process and output sound. One would have been motivated to make such a combination in order to improve the digital representation of sound, as suggested by Zanbaghi (US 20170047939 A1) (0052)
Regarding claim 14, Milletari and Khailany teach the method of claim 11.
Milletari and Khailany do not teach wherein each of the plurality of the input data comprises a digital representation of a sound.
Zanbaghi teaches a digital representation of a sound. (0052): When a microphone is coupled to the first input and the second input, this digital signal is a digital representation of sounds in an environment around the microphone.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Milletari, Khailany and Zanbaghi before them, to include Zanbaghi digital representation of sound which would allow Milletari and Khailany’s method to process and output sound. One would have been motivated to make such a combination in order to improve the digital representation of sound, as suggested by Zanbaghi (US 20170047939 A1) (0052)
Conclusion
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/K.A.T./Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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