DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submissions filed on 5/24/2026 and 6/23/2026 have been entered.
Claims 1, 7 and 10 have been amended. Claims 1, 4-7 and 10-13 have been examined.
Response to Arguments/Amendments
The prior claim objections and rejections under 35 USC § 112 have been withdrawn in view of the claim amendments.
Applicant's arguments filed 5/24/2026 and 6/23/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that Saito’s non-synapse power control is not clearly usable with Hayata’s n inputs (see bottom of p.11 filed 5/24/2026), the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). With respect to the teaching of Saito, one of ordinary skill in the art would instantly recognize the benefit of saving power while preserving the ability to adapt to circuit changes (see Saito, col. 1, lines 34-40). Such power saving benefits would apply to any circuit architecture, including synaptic circuits. Also, such power saving benefits would only increase with increasing circuit elements. As such, one of ordinary skill would have good reason to explore and combine the teaching of Saito.
At the bottom of p. 11 through the top of p. 12 filed 5/24/2026, Applicant argues that Hayata provides no indication of a time required for voltage application and as such would be unable to apply the power reduction of Saito which requires time measurements. As noted above, the test for obviousness is what the combined teachings of the references would have suggested to those of ordinary skill in the art. One of ordinary skill in the art would be motivated to explore the time required for application of voltage, especially if Saito’s teaching would enable power reduction and savings. Applicant’s argument is not persuasive.
Applicant’s remaining arguments, see pp. 12-13, filed 5/24/2026, with respect to the rejection(s) of claim(s) 1, 4-7 and 10-13 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of U.S. Patent Application Publication 20200026494 by Langhammer et al.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 20200202925 by Hayata et al. ("Hayata") in view of U.S. Patent 5675282 to Saito ("Saito") and U.S. Patent Application Publication 20200026494 by Langhammer et al. (“Langhammer”).
In regard to claim 1, Hayata discloses:
1. An apparatus of analog-neuron comprising a synapse circuit to perform arithmetic processing of multiplying by a weight value, an input signal that arrives at an input terminal, the apparatus comprising: See Hayata, Fig. 5, depicting an apparatus.
a synapse output holding circuit configured to hold an output signal of the synapse circuit; and See Hayata, Fig. 5, element 27 and ¶ 0065, “The output results of computation circuits 26 are stored in output holding circuit 27.”
Hayata does not expressly disclose the following limitations but they are taught by Saito:
a power control circuit to control whether to supply power at least to the synapse circuit or stop supplying of power in response to whether an input signal has arrived at the input terminal or has been lost. See Saito, col. 3, lines 41-50, “In preferred embodiments, when the clock signal CK is provided to the main circuit 12, the main circuit 12 is in an activation mode (i.e., a normal operating mode) and performs its predetermined operation, such as an arithmetic operation or the like. When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.” Also see Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
wherein the power control circuit comprises:
an input signal detection circuit configured to detect whether an input signal has arrived at the input terminal or has been lost, and See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag FI which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag FI, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
a power control internal circuit configured to control whether power is supplied at least to the synapse circuit or power supply is stopped in accordance with a detection result of the input signal detection means. See Saito col. 3 lines 41-50 as cited above. Also col. 3, lines 45-50, e.g. “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode. In alternative embodiments, the main circuit 12 may be placed in the sleep mode by completely suspending the supply of the clock signal CK to the main circuit 12.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s synapse circuit in order to save power and flexibly adapt to circuit changes as suggested by Saito (see at least col. 1, lines 34-40).
Hayata also discloses:
wherein a comparator to digitize the output signal of the synapse circuit is connected between the output side of the synapse circuit and the synapse output holding circuit, and See Hayata, Fig. 5 element 26 and ¶ 0044, “For example, computation circuit 26 causes a sense amplification circuit to compare the magnitude of two bit lines 23 and outputs binary data of (0, 1), to achieve a computation operation of a step function. Moreover, there is also a method in which an A/D conversion circuit converts a current value flowing in bit line 23 to a digital signal.” Also ¶ 0062, “Each of eight computation circuits 26 compares currents of positive-side bit line 23A and negative-side bit line 23B, and outputs (0, 1).”
Hayata does not expressly disclose: wherein the power control circuit controls whether to supply power to the synapse circuit and the comparator or to stop the supplying of power in response to whether an input signal has arrived at the input terminal or has been lost. This is taught by Saito. See Saito col. 3 lines 41-50 as cited above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to flexibly adapt to changes and save power as suggested by Saito (see at least col. 1, lines 34-40).
Hayata does not expressly disclose: at the timing of the input signal arriving at the input terminal, the synapse circuit receives the weight value from a weight value supply control circuit. This is taught by Langhammer. See Langhammer ¶ 0040, “To ensure that both dot product operands arrive at the same time, the delays introduced by registers 303 along each row and by registers 305 along each column should be matched.” Also see Fig. 2 elements 202 and 204 depicting load control circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Langhammer’s signal timing with the computations of Hayata and Saito in order to ensure that appropriate operands are available for computation as essentially suggested by Langhammer.
In regard to claim 4, Hayata and Saito also teach:
4. The apparatus of analog-neuron according to claim 1, wherein the input signal detection circuit includes:
a change detection circuit to detect presence or absence of a change in the signal level input to the input terminal, a timer to count a predetermined time required for an operation performed by the synapse circuit after the change detection circuit detects no change in the signal level, and See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
an instruction circuit to instruct to stop power supply to the synapse circuit and the comparator when time counting by the timer is completed, and wherein, upon receiving an instruction signal from the instruction circuit, the power control internal circuit stops supplying power to the synapse circuit and the comparator. See Saito, col. 3, lines 45-47, “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.”
In regard to claim 5, Hayata and Saito also teach:
5. The apparatus of analog-neuron according to claim 3, wherein the synapse output holding circuit includes a logic memory circuit to store the output signal of the comparator, and See Hayata, ¶ 0044, “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
wherein the power control internal circuit supplies power to the logic memory circuit when receiving an instruction signal from the instruction circuit. See Saito col. 3 lines 41-50 as cited above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to save power as suggested by Saito (see at least col. 1, lines 34-40).
In regard to claim 7, Hayata discloses:
7. A control method for an apparatus of analog-neuron, See Hayata, at least ¶ 0055, “a computation operation of a neural network.”
the apparatus of analog-neuron comprising a synapse circuit that receives a weight value from a weight value supply control unit … See Hayata, Fig. 5 depicting a synapse circuit with weight coefficients stored in memory array 20.
Hayata does not expressly disclose: … in sync with a timing when an input signal arrives at an input terminal … This is taught by Langhammer. See Langhammer ¶ 0040, “To ensure that both dot product operands arrive at the same time, the delays introduced by registers 303 along each row and by registers 305 along each column should be matched.” Also see Fig. 2 elements 202 and 204 depicting load control circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Langhammer’s signal timing with the computations of Hayata and Saito in order to ensure that appropriate operands are available for computation as essentially suggested by Langhammer.
Hayata does not expressly disclose the following limitations taught by Saito:
wherein the controlling includes:
detecting presence or absence of a change in a level of signals input to the input terminal; counting a predetermined time required for performing arithmetic processing of multiplying by the synapse circuit from when detecting presence or absence of the change in the level of signals input to the input terminal; See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
instructing to stop power supply to the synapse circuit and the comparator when the predetermined time has been counted; and stopping the supply of power to the synapse circuit and the comparator when a stop power supply instruction is received. See Saito, col. 3, lines 45-47, “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s synapse circuit in order to save power and flexibly adapt to circuit changes as suggested by Saito (see at least col. 1, lines 34-40).
All further limitations of claim 7 have been addressed in the above rejection of claim 1.
In regard to claim 10, Hayata and Saito also teach:
10. The control method for the apparatus of analog-neuron according to claim 7, comprising:
digitizing the output signal of the synapse circuit by using the comparator; See Hayata, Fig. 5 element 26 and ¶ 0062, “Each of eight computation circuits 26 compares currents of positive-side bit line 23A and negative-side bit line 23B, and outputs (0, 1).”
storing the output signal obtained by the digitizing step in a logic memory circuit logic; and See Hayata, ¶ 0044, “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
Hayata does not expressly disclose:
supplying power to the logic memory circuit when a power supply instruction signal is received, and continuing to supply power to the logic memory circuit, even after the power supply has been stopped to the synapse circuit. This is taught by Saito. See Figs. 2 and 3 along with col. 3 lines 41-50 and col. 4, lines 2-6, “the switch circuit 21 provides the supply voltage VDD to main circuit 12, and during the sleep mode, the switch circuit 21 suspends the application of the supply voltage VDD to the main circuit, Removing the supply voltage VDD completely shuts off the main circuit 12.” Note that power must continue to be supplied to at least circuit 16/21 which controls the power to circuit 12. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to save power and flexibly adapt to circuit changes as suggested by Saito (see at least col. 1, lines 34-40).
In regard to claim 12:
Parent claim 4 is addressed above. All further limitations of claim 12 have been addressed in the above rejection of claim 5.
Claims 6, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hayata in view of Saito and Langhammer as applied above, and further in view of U.S. Patent 6515528 to Tohsche ("Tohsche").
In regard to claim 6, Hayata also discloses:
6. The apparatus of analog-neuron according to claim 5, wherein the logic memory circuit includes: a latch circuit to latch an output signal of the comparator, and See Hayata ¶ 0044 “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
Hayata does not expressly disclose:
a switch circuit having a first switch and a second switch connected in series between a first voltage and a second voltage and having an output terminal at an output point of the first switch and the second switch, the switch circuit functions to open and close the first switch and the second switch in accordance with a logic value stored in the latch circuit. However, this is taught by Tohsche. See Fig. 1, depicting output driver 4 with switches 19 and 20 in connection with latch 3. See col. 3, lines 54-65, “The input of this inverter circuit is connected to the node between transistors 12 and 14 where the negated output signal value Q arises, so that the output signal Q is emitted by inverter circuit 4 from an output which is decoupled from the internal nodes of the slave latch 3.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tohsche’s switch circuit with Hayata’s latch in order to give a power consumption which is as low as possible and a switching speed which is as high as possible, as suggested by Tohsche (see col. 2, lines 24-38).
In regard to claim 11:
Hayata does not expressly disclose:
… wherein the method further comprises opening and closing the first switch and the second switch in accordance with the logical value held in the latch circuit. However, this is taught by Tohsche. See Fig. 1, depicting output driver 4 with switches 19 and 20 in connection with latch 3. See col. 3, lines 54-65, “The input of this inverter circuit is connected to the node between transistors 12 and 14 where the negated output signal value Q arises, so that the output signal Q is emitted by inverter circuit 4 from an output which is decoupled from the internal nodes of the slave latch 3.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tohsche’s switch circuit with Hayata’s latch in order to give a power consumption which is as low as possible and a switching speed which is as high as possible, as suggested by Tohsche (see col. 2, lines 24-38).
All further limitations of claim 11 have been addressed in the above rejection of claim 6.
In regard to claim 13:
Parent claim 5 is addressed above. All further limitations of claim 12 have been addressed in the above rejection of claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 10175947 to Marukame et al. teaches control circuits and signal timing. See col. 11, lines 47-52, “The selector 112 selects any one of N word addresses at the time of performing the arithmetic operation. Upon reception of M input signals, the arithmetic unit 20 performs the product-sum operation (multiply accumulate operation) of the M input signals and the M coefficients at the selected word address by analog processing.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James D Rutten whose telephone number is (571)272-3703. The examiner can normally be reached M-F 9:00-5:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B Zhen can be reached at (571)272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James D. Rutten/Primary Examiner, Art Unit 2121
Prosecution Insights