DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-7 and 10-12 have been amended. Claims 2-3 and 8-9 have been canceled. Claims 1, 4-7 and 10-13 have been examined.
Response to Arguments
The prior claim objections and rejections under 35 USC § 112 have been withdrawn in view of the claim amendments.
Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive.
On p. 12 of the 12/1/2025 remarks, Applicant argues that cited art of record Hayata “does not digitize an analog output resulting from the synapse circuit weighting the input signal,” and “does not control the power supply depending on whether an input signal has arrived at the input terminal.” In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “an analog output resulting from the synapse circuit weighting the input signal”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
On p. 13 of the remarks, Applicant argues that cited art of record Saito fails to disclose or suggest “a power control circuit that controls whether to supply power to the synapse circuit and the comparator or to stop the supplying of power.” In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As provided in the rejection below, Hayata is relied upon to disclose a neuron/synapse circuit which includes synapses 21 and comparators 26. Saito is relied upon to teach circuit power control. The rejection relies upon the combination of both Hayata and Saito to teach the claimed limitations, and notes that Saito teaches that controlling power in a circuit allows for power saving and flexible adaptation. The rejection is not based upon Saito alone, but instead relies upon the teaching of both references in combination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended claim 10 includes “a put power supply instruction.” Related description was found in Applicant’s as-filed specification in paragraphs 0026-0027 on pp. 11-12. However, no description was found regarding a “put power supply instruction.” This term is not recognized as a special term of the art and no reference to this specific instruction was found in Applicant’s disclosure. For the purpose of further examination, the limitation will be interpreted in view of paragraphs 0026-0027 and in view of the prior claim language as “when a signal is received.”
Claim 11 is rejected as carrying the limitations of rejected parent claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 20200202925 by Hayata et al. ("Hayata") in view of U.S. Patent 5675282 to Saito ("Saito").
In regard to claim 1, Hayata discloses:
1. An apparatus of analog-neuron comprising a synapse circuit to perform arithmetic processing of multiplying by a weight value, an input signal that arrives at an input terminal, the apparatus comprising: See Hayata, Fig. 5, depicting an apparatus.
a synapse output holding circuit configured to hold an output signal of the synapse circuit; and See Hayata, Fig. 5, element 27 and ¶ 0065, “The output results of computation circuits 26 are stored in output holding circuit 27.”
Hayata does not expressly disclose the following limitations but they are taught by Saito:
a power control circuit to control whether to supply power at least to the synapse circuit or stop supplying of power in response to whether an input signal has arrived at the input terminal or has been lost. See Saito, col. 3, lines 41-50, “In preferred embodiments, when the clock signal CK is provided to the main circuit 12, the main circuit 12 is in an activation mode (i.e., a normal operating mode) and performs its predetermined operation, such as an arithmetic operation or the like. When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.” Also see Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
wherein the power control circuit comprises:
an input signal detection circuit configured to detect whether an input signal has arrived at the input terminal or has been lost, and See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag FI which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag FI, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
a power control internal circuit configured to control whether power is supplied at least to the synapse circuit or power supply is stopped in accordance with a detection result of the input signal detection means. See Saito col. 3 lines 41-50 as cited above. Also col. 3, lines 45-50, e.g. “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode. In alternative embodiments, the main circuit 12 may be placed in the sleep mode by completely suspending the supply of the clock signal CK to the main circuit 12.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s synapse circuit in order to save power and flexibly adapt to circuit changes as suggested by Saito (see at least col. 1, lines 34-40).
Hayata also discloses:
wherein a comparator to digitize the output signal of the synapse circuit is connected between the output side of the synapse circuit and the synapse output holding circuit, and See Hayata, Fig. 5 element 26 and ¶ 0044, “For example, computation circuit 26 causes a sense amplification circuit to compare the magnitude of two bit lines 23 and outputs binary data of (0, 1), to achieve a computation operation of a step function. Moreover, there is also a method in which an A/D conversion circuit converts a current value flowing in bit line 23 to a digital signal.” Also ¶ 0062, “Each of eight computation circuits 26 compares currents of positive-side bit line 23A and negative-side bit line 23B, and outputs (0, 1).”
Hayata does not expressly disclose: wherein the power control circuit controls whether to supply power to the synapse circuit and the comparator or to stop the supplying of power in response to whether an input signal has arrived at the input terminal or has been lost. This is taught by Saito. See Saito col. 3 lines 41-50 as cited above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to flexibly adapt to changes and save power as suggested by Saito (see at least col. 1, lines 34-40).
In regard to claim 4, Hayata and Saito also teach:
4. The apparatus of analog-neuron according to claim 1, wherein the input signal detection circuit includes:
a change detection circuit to detect presence or absence of a change in the signal level input to the input terminal, a timer to count a predetermined time required for an operation performed by the synapse circuit after the change detection circuit detects no change in the signal level, and See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
an instruction circuit to instruct to stop power supply to the synapse circuit and the comparator when time counting by the timer is completed, and wherein, upon receiving an instruction signal from the instruction circuit, the power control internal circuit stops supplying power to the synapse circuit and the comparator. See Saito, col. 3, lines 45-47, “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.”
In regard to claim 5, Hayata and Saito also teach:
5. The apparatus of analog-neuron according to claim 3, wherein the synapse output holding circuit includes a logic memory circuit to store the output signal of the comparator, and See Hayata, ¶ 0044, “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
wherein the power control internal circuit supplies power to the logic memory circuit when receiving an instruction signal from the instruction circuit. See Saito col. 3 lines 41-50 as cited above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to save power as suggested by Saito (see at least col. 1, lines 34-40).
In regard to claim 7, Hayata discloses:
7. A control method for an apparatus of analog-neuron, See Hayata, at least ¶ 0055, “a computation operation of a neural network.”
…
wherein the controlling includes:
detecting presence or absence of a change in a level of signals input to the input terminal; counting a predetermined time required for performing arithmetic processing of multiplying by the synapse circuit from when detecting presence or absence of the change in the level of signals input to the input terminal; See Saito, Fig. 2, depicting input detector 14 and timer 15. Also see related text at col. 3 lines 23-30 “When the input data is detected, the input detector 14 sets a data input flag F1 which functions like a trigger signal for a timer 15. Upon being triggered by the data input flag F1, the timer 15 sets an action flag FA, which determines a time period required for the main circuit 12 to process the input data and counts a clock signal CK.”
instructing to stop power supply to the synapse circuit and the comparator when the predetermined time has been counted; and stopping the supply of power to the synapse circuit and the comparator when a stop power supply instruction is received. See Saito, col. 3, lines 45-47, “When the low-speed clock signal CK' is provided to the main circuit 12, the main circuit 12 is placed in a sleep mode.”
All further limitations of claim 7 have been addressed in the above rejection of claim 1.
In regard to claim 10, Hayata and Saito also teach:
10. The control method for the apparatus of analog-neuron according to claim 9, comprising:
digitizing the output signal of the synapse circuit by using the comparator; and See Hayata, Fig. 5 element 26 and ¶ 0062, “Each of eight computation circuits 26 compares currents of positive-side bit line 23A and negative-side bit line 23B, and outputs (0, 1).”
storing the output signal obtained by the digitizing step in a logic memory circuit logic, and See Hayata, ¶ 0044, “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
Hayata does not expressly disclose:
putting the supply of power to the logic memory is performed when a [] power supply instruction [signal] is received. This is taught by Saito. See col. 3 lines 41-50 as cited above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Saito’s power control with Hayata’s various circuit elements, including comparator units 26, in order to save power and flexibly adapt to circuit changes as suggested by Saito (see at least col. 1, lines 34-40).
In regard to claim 12:
Parent claim 4 is addressed above. All further limitations of claim 12 have been addressed in the above rejection of claim 5.
Claims 6, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hayata in view of Saito as applied above, and further in view of U.S. Patent 6515528 to Tohsche ("Tohsche").
In regard to claim 6, Hayata also discloses:
6. The apparatus of analog-neuron according to claim 5, wherein the logic memory circuit includes: a latch circuit to latch an output signal of the comparator, and See Hayata ¶ 0044 “Output holding circuit 27 includes a flip-flop, a latch circuit, etc.”
Hayata does not expressly disclose:
a switch circuit having a first switch and a second switch connected in series between a first voltage and a second voltage and having an output terminal at an output point of the first switch and the second switch, the switch circuit functions to open and close the first switch and the second switch in accordance with a logic value stored in the latch circuit. However, this is taught by Tohsche. See Fig. 1, depicting output driver 4 with switches 19 and 20 in connection with latch 3. See col. 3, lines 54-65, “The input of this inverter circuit is connected to the node between transistors 12 and 14 where the negated output signal value Q arises, so that the output signal Q is emitted by inverter circuit 4 from an output which is decoupled from the internal nodes of the slave latch 3.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tohsche’s switch circuit with Hayata’s latch in order to give a power consumption which is as low as possible and a switching speed which is as high as possible, as suggested by Tohsche (see col. 2, lines 24-38).
In regard to claim 11:
Hayata does not expressly disclose:
… wherein the method further comprises opening and closing the first switch and the second switch in accordance with the logical value held in the latch circuit. However, this is taught by Tohsche. See Fig. 1, depicting output driver 4 with switches 19 and 20 in connection with latch 3. See col. 3, lines 54-65, “The input of this inverter circuit is connected to the node between transistors 12 and 14 where the negated output signal value Q arises, so that the output signal Q is emitted by inverter circuit 4 from an output which is decoupled from the internal nodes of the slave latch 3.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tohsche’s switch circuit with Hayata’s latch in order to give a power consumption which is as low as possible and a switching speed which is as high as possible, as suggested by Tohsche (see col. 2, lines 24-38).
All further limitations of claim 11 have been addressed in the above rejection of claim 6.
In regard to claim 13:
Parent claim 5 is addressed above. All further limitations of claim 12 have been addressed in the above rejection of claim 6.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James D Rutten whose telephone number is (571)272-3703. The examiner can normally be reached M-F 9:00-5:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B Zhen can be reached at (571)272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/James D. Rutten/Primary Examiner, Art Unit 2121