DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/05/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13, 34-36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13, line 6 recites, “a respective current limit set input”, and it is indefinite which limitation is being referred as to being respective, a current limit set input is not recited for the first port power path. For examination purposes, the current limit set input recited in the interlock logic circuit of parent claim 2 is considered..
Claim 34 recites the limitation "the control input" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 28, 31-32, 37, 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Audy (US 2006/0001459).
Regarding Claim 1, Audy discloses a circuit (Figures 1-7) comprising:
a power circuit having a power input (IN, Figure 1), a power output (DRVH driving Q1 to output at 10, Figure 1), an overload output (Hlock, Figure 1), and a control input (Llock, Figure 1), the power circuit being capable of:
responsive to the control input having a first state (Llock having high state, Figure 1), allowing a current at the power output to exceed a current limit (DRVH>REF, Figure 1), and providing a signal at the overload output (Hlock, Figure 1) indicative of the current exceeding the current limit (when DRVH>REF, Hlock is provided, Figure 1, Paragraph 7); and
responsive to the control input having a second state (Llock having low state, Figure 1), limiting the current at the power output at or below the current limit (DRVH<REF/Q1 off, Figure 1, Paragraph 7).
Regarding Claim 28, Audy discloses the circuit of Claim 1, wherein the power circuit is configurable to, responsive to the control input having a first state, allowing the current at the power output to exceed the current limit for a pre-determined duration (duration Llock remains at low logic/until change to logic high), and after the duration elapses, limiting the current at the power output at or below the current limit (DRVH <REF).
Regarding Claim 31, Audy discloses he circuit of Claim 1, wherein the power circuit is a first power circuit (comprising 16, 12, 20, Figure 1, the power output is a first power output, the overload output is a first overload output, the control input is a first control input (IN, DRVH, Hlock, Llock respectively, Figure 1), and the circuit further comprises a second power circuit (comprising 18, 14, 22, Figure 1) having a second power input (inverted IN to 18, Figure 1), a second power output (DRVL, Figure 1), a second overload output (Llock, Figure 1), and a second control input (Hlock, Figure 1), the second power input coupled to the first power input (inverted IN coupled to IN, Figure 1), the second overload output coupled to the first control input (Llock coupled to the first control input to 16, Figure 1, and the second control input coupled to the first overload output (second control input to 18 coupled to Hlock, Figure 1).
Regarding Claim 32, Audy discloses he circuit of Claim 31, wherein the current is a first current (first current driving Q1), the signal is a first signal (Hlock at low), and the second power circuit is capable of: responsive to the second control input having the first state (Hlock having high state, Figure 1), allowing a second current at the second power output to exceed the current limit (corresponding to DRVL>REF, Figure 1), and providing a second signal at the overload second output (Llock at low state, Figure 1) indicative of the second current exceeding the current limit (corresponding to DRVL>REF, Figure 1, Paragraph 7); and responsive to the second control input having a second state(Hlock having low state), limiting the second current at the second power output at or below the current limit (DRVL<REF, Figure 1).
Regarding Claim 37, Audy discloses an electronic device (Figures 1-7) comprising:
a port (OUT, Figure 1); and
a power circuit having a power output (DRVH, Figure 1), an overload output (Hlock, Figure 1), and a control input (Llock, Figure 1), the power output coupled to the port (DRVH coupled to OUT via Q1, Figure 1), the power circuit being capable of:
responsive to the control input having a first state (Llock having high state, Figure 1), allowing a current at the power output to exceed a current limit (corresponding to DRVH>REF, Figure 1), and providing a signal at the overload output (Hlock at low state, Figure 1) indicative of the current exceeding the current limit (corresponding to DRVH>REF, Figure 1, Paragraph 7); and
responsive to the control input having a second state (Llock having low state), limiting the current at the power output at or below the current limit (DRVH<REF, Figure 1).
Regarding Claim 39, Audy discloses an electronic device of Claim 37, wherein the power circuit is a first power circuit, the power output is a first power output, the overload output is a first overload output, the control input is a first control input, and the electronic device further comprises: a second port (OUT coupled when Q2 is conducting, Figure 1); a second power circuit having a second power input (input receiving inverted IN, Figure 1) coupled to the second port (IN coupled to OUT with Q1 conducting, Figure 1), a second power output (DRVL, Figure 1), a second overload output (Llock, Figure 1), and a second control input (input receiving Hlock, Figure 1), the second power input coupled to the first power input (the second input coupled to IN via inverter, Figure 1), the second overload output coupled to the first control input (Llock coupled to the first control input, Figure 1), and the second control input coupled to the first overload output (second control input coupled to Hlock, Figure 1).
Regarding Claim 40, Audy discloses an electronic device of Claim 39, wherein the current is a first current (first current driving Q1), the signal is a first signal (Hlock at low), and the second power circuit is capable of: responsive to the second control input having the first state (Hlock having high state, Figure 1), allowing a second current at the second power output to exceed the current limit (corresponding to DRVL>REF, Figure 1), and providing a second signal at the overload second output (Llock at low state, Figure 1) indicative of the second current exceeding the current limit (corresponding to DRVL>REF, Figure 1, Paragraph 7); and responsive to the second control input having a second state(Hlock having low state), limiting the second current at the second power output at or below the current limit (DRVL<REF, Figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 29-30, 33-36, 38 are rejected under 35 U.S.C. 103 as being unpatentable over Audy (US 2006/0001459) in view of Scheel (US 11,205,894).
Regarding Claim 29, Audy does not specifically disclose the circuit of Claim 28, wherein the power output is coupled to a USB port.
Scheel discloses a circuit (multi-port system/circuit, Figures 1-6) comprising:
a power circuit Figures 1-3having a power input (VSYS, Figures 1-3), a power output (VBUS1, VBUS2/17) and a first overload output (FLTB, Figures 1-4, 6); and an interlock logic/control circuit (comprising 14, Q3, Figures 1-2, 54, Q3, Figure 3), wherein the power output is coupled to a USB port (PORT1/PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the port in the electronic device of Audy, as USB port as taught by Scheel such that USB compatible load devices can be charged using the port.
Regarding Claim 30, combination of Audy and Scheele discloses the circuit of Claim 31, wherein the second power output is coupled to a second USB port (PORT1/PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31).
Regarding Claim 33, Audy does not specifically disclose the circuit of Claim 31, wherein the second power output is coupled to a second USB port.
Scheel discloses a circuit (multi-port system/circuit, Figures 1-6) comprising:
a power circuit Figures 1-3having a power input (VSYS, Figures 1-3), a power output (VBUS1, VBUS2/17) and a first overload output (FLTB, Figures 1-4, 6); and an interlock logic/control circuit (comprising 14, Q3, Figures 1-2, 54, Q3, Figure 3), wherein the power output is coupled to a second USB port (PORT1/PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the port in the electronic device of Audy, as USB port as taught by Scheel such that USB compatible load devices can be charged using the port.
Regarding Claim 34, Audy discloses an electronic device (Figures 1-7) comprising:
a port (OUT, Figure 1);
a port power path circuit coupled to the port (comprising circuit coupled to OUT, Figure 1), the port power path circuit having a first overload output (DRVH feedback output to 20, Figure 1), and a current limit output (DRVH, Figure 1); and
an interlock logic circuit (comprising 16, 12, 20, Figure 1) having an interlock input coupled to a control input (input receiving control input Llock input, Figure 1), a current limit input (REF, Figure 1), and a current limit set output (Hlock, Figure 1), the interlock input adapted to be coupled to a second overload output of a second port power circuit (input receiving Llock coupled to a second port power circuit comprising 18, 14, 22, Figure 1), the interlock logic circuit includes AND-logic having first and second logic inputs and an output (comprising 16 having a first and second inputs and an output, Figure 1). Audy does not specifically disclose an OR-logic having the first logic input coupled to the current limit output and the second logic input coupled to the first overload output, the output of the OR logic coupled to the current limit input.
Scheel discloses an electronic device (multi-port system, Figures 1-6) comprising: a port (PORT1, PORT2, Figures 1-3);
a port power path circuit having a power input (VSYS, Figures 1-3) and a first overload output (FLTB, Figures 1-4, 6); and
an interlock logic circuit (comprising 14, Q3, Figures 1-2, 54, Q3, Figure 3) having an interlock input (DISB, Figures 1-4, 6), a current limit input (input at the gate of Q3, Figure 3), a current limit set output (ISRC input to 63, 65 to output of 63, 65, Figures 3-4, 6), the current limit input coupled to the first overload output (output of 62 coupled to FLTB via Q3, Figures 3-4, 6), the interlock input adapted to be coupled to a second overload output of a second port power circuit (DISB of port controller 1 coupled to FLTB of port controller 2), the interlock logic circuit being configured to delay providing an output signal to the current limit set output responsive to an overload signal at the current limit input (delay at comparators 63, 65 and logic gate 62, Figures , 1-4, 6), wherein the port power path circuit has a current limit output (output at 17 when FLTB is asserted, Figures 1-3), and
the interlock logic circuit comprises OR-logic (comprising 62, Figures 3-4, 6) having first and second logic inputs and an output (inputs to 62 from 63, 65 and output of 62 to Q3, Figures 3-4, 6), the output of the OR logic coupled to the current limit input (output of OR gate 62 to the gate of Q3, current limit input to Q3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the electronic device of Audy, an OR-logic as taught by Scheele and to configure the inputs to obtain the desired output logic.
Regarding Claim 35, combination of Audy and Scheel discloses the electronic device of Claim 34, wherein the port is a USB port (Scheele, PORT1, PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31).
Regarding Claim 36, combination of Audy and Scheel discloses the electronic device of Claim 34, wherein the port is a first port (OUT when Q1 is conducting, Figure 1), and the electronic device further comprises: a second port (OUT when Q2 is conducting, Figure 1); and the second port power circuit coupled to the second port (port when Q2 is conducting is coupled to a second port power circuit comprising 8, 14, 22, Figure 1).
Regarding Claim 38, Audy does not specifically disclose the electronic device of Claim 37, wherein the port is a USB port.
Scheel discloses an electronic device (multi-port system, Figures 1-6) comprising: a port (PORT1, PORT2, Figures 1-3);
a port power path circuit having a power input (VSYS, Figures 1-3) and a first overload output (FLTB, Figures 1-4, 6); and an interlock logic circuit (comprising 14, Q3, Figures 1-2, 54, Q3, Figure 3), wherein the port is a USB port (PORT1, PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the port in the electronic device of Audy, as USB port as taught by Scheel such that USB compatible load devices can be charged using the port.
Claims 2-7, 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Audy (US 2006/0001459) in view of Scheel (US 11,205,894) and Muroor (US 2003/0145244).
Regarding Claims 2 and 3-7, Audy discloses the circuit of Claim 1, wherein the overload output is a first overload output (DRVH being a first overload output, Figure 1), and the power circuit includes:
a port power path circuit coupled between the power input and the power output (comprising power circuit coupled to OUT via Q1, Figure 1), the port power path circuit having the first overload output (DRVH, Figure 1), and a current limit output (DRVH provided to a control gate of Q1, Figure 1); and
an interlock logic circuit (comprising 16, 12, 20, Figure 1) having an interlock input coupled to the control input (input at 16 receiving control input Llock, Figure 1), a current limit input (REF, Figure 1), and a current limit set output (Hlock, Figure 1), the interlock input adapted to be coupled to a second overload output of a second port power circuit (input receiving Llock coupled to a second port power circuit comprising 18, 14, 22, Figure 1),
the interlock logic circuit includes AND-logic having first and second logic inputs and an output (comprising 16 having a first and second inputs and an output, Figure 1), the interlock circuit is capable of delaying providing an output signal to the current limit set output responsive to an overload signal from the first overload output (Paragraph 7).
Audy does not specifically disclose an OR-logic having the first logic input coupled to the current limit output and the second logic input coupled to the first overload output, the output of the OR logic coupled to the current limit input (Claim 2) and a deglitch circuit (Claim 3) and the inputs and output coupling of the OR-logic and the deglitch circuit as recited (Claims 3-7).
Scheel discloses an electronic device (multi-port system, Figures 1-6) comprising: a port (PORT1, PORT2, Figures 1-3);
a port power path circuit having a power input (VSYS, Figures 1-3) and a first overload output (FLTB, Figures 1-4, 6); and
an interlock logic circuit (comprising 14, Q3, Figures 1-2, 54, Q3, Figure 3) having an interlock input (DISB, Figures 1-4, 6), a current limit input (input at the gate of Q3, Figure 3), a current limit set output (ISRC input to 63, 65 to output of 63, 65, Figures 3-4, 6), the current limit input coupled to the first overload output (output of 62 coupled to FLTB via Q3, Figures 3-4, 6), the interlock input adapted to be coupled to a second overload output of a second port power circuit (DISB of port controller 1 coupled to FLTB of port controller 2), the interlock logic circuit being configured to delay providing an output signal to the current limit set output responsive to an overload signal at the current limit input (delay at comparators 63, 65 and logic gate 62, Figures , 1-4, 6), wherein the port power path circuit has a current limit output (output at 17 when FLTB is asserted, Figures 1-3), and
the interlock logic circuit comprises OR-logic (comprising 62, Figures 3-4, 6) having first and second logic inputs and an output (inputs to 62 from 63, 65 and output of 62 to Q3, Figures 3-4, 6), the output of the OR logic coupled to the current limit input (output of OR gate 62 to the gate of Q3, current limit input to Q3).
Muroor discloses a circuit (circuit for selecting output, Figures 1-4) comprising an interlock logic circuit (comprising 240A, 240B, 250, Figure 2, details of 240 shown in 340, Figure 3) comprising a first input (A, Figures 2-3), a second input (B, Figure 2) and an output (DISABLE, Figures 2-3), the interlock logic circuit configured to delay providing an output signal to an output port of the circuit (output CLKOUT), wherein the interlock logic circuit comprises OR-logic (comprising 340, Figure 3 and 250, Figure 2) having first and second logic inputs and an output (inputs and output of 340, Figure 3, inputs and output of 250, Figure 2), and a deglitch circuit (comprising 310, 330, Figure 3), OR-logic having the first logic input coupled to an output of the deglitch circuit and the second logic input coupled to an output of control circuit, the output of the OR logic coupled to a limit input (input A, input B/Q output of 330 and output disable, Figures 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the electronic device of Audy, an OR-logic as taught by Scheel and Muroor and deglitch circuit as taught by Moroor and additional OR-logic and to configure the inputs to obtain the desired delay and output logic.
Regarding Claim 8, combination of Audy, Scheel and Muroor discloses the circuit of Claim 2,further comprising a current sensor having a current sensor output (Rsense in Figures 3-4, 6 of Scheel in the combination, Column 3, lines 57-63, “…a multi-port system implements fault detection using a resistor RSENSE connected to each port controller and also connected in parallel with at least one other resistor….. adds a RSENSE monitoring pin to the port controller…”).
Regarding Claim 9, combination of Audy, Scheel and Muroor discloses the circuit of Claim 8, wherein the port power path circuit comprises:
a power switch control circuit having a sensor input and a control output, in which the sensor input is coupled to the current sensor output (Scheel, part of control circuit 54 with RSENSE at 55 and control output to Q1, Q2, Figures 1-4, 6, Column 3, lines 57-63, “…a multi-port system implements fault detection using a resistor RSENSE connected to each port controller and also connected in parallel with at least one other resistor….. adds a RSENSE monitoring pin to the port controller…”);
a driver circuit (Scheel, part of control circuit 54 providing dive signal to Q1, Q2, Figures 1-4, 6); and
a power switch coupled between the power input and the power output (comprising Q1, Q2 coupled between VSYS and PORT1/PORT2, Figures 3-4, 6), the power switch having a control input coupled to the driver output (control input of Q1, Q2 coupled to output of 54, the power input coupled to a power supply (power input coupled to VSYS, 18 to internal system/power source, Figure 3), and the power output coupled to the a port output (power output to 17, PORT1/PORT2, Figure 3).
Combination of Audy, Scheel and Muroor does not specifically disclose the driver circuit having a driver input and a driver output, the driver input coupled to the control output (Scheel shows the control circuit including monitoring and driving circuit component one block, not outside the control circuit). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination, to provide the driver circuit as a separate unit, outside of the control circuit, to facilitate easy trouble shooting and maintenance in the event of a failure in the system.
Regarding Claim 10, combination of Audy, Scheel and Muroor discloses the circuit of Claim 9, wherein the current sensor is capable of providing a current sensor signal at the sensor output representative of current provided to the port output (Scheel, Rsense in Figures 3-4, 6 in the combination, Column 3, lines 57-63), and the power switch control circuit comprises current control circuit capable of detecting an overcurrent condition and provide the overload signal at the first overload output responsive to the current sensor signal (Scheel in the combination, Column 3, lines 3-11, 57-63).
Regarding Claim 11, combination of Audy, Scheel and Muroor discloses the circuit of Claim 10, wherein the current limit is a first current limit, wherein the current control circuit is capable of detecting the overcurrent condition responsive to detecting the current provided to the port output exceeds the first current limit and less than a second current limit setting, the second current limit being greater than the first current limit setting (current limits corresponding to VTH_UP and VTH_LOW in Figure 4 of Scheel in the combination).
Regarding Claim 12, combination of Audy, Scheel and Muroor discloses the circuit of Claim 9, wherein the port output is coupled to a power terminal of a universal serial bus (USB)connector (PORT1, PORT2, Figures 1-3, Column 1, lines 12-33, Column 4, lines 17-31).
Regarding Claim 13, combination of Audy, Scheel and Muroor discloses the circuit of Claim 2, wherein the port power path circuit is a first port power path circuit and the interlock logic circuit is a first interlock logic circuit, the first port power path circuit and the first interlock logic circuit are part of a first port power circuit, the circuit further comprising: the second port power circuit, comprising:
a second port power path circuit (Audy, comprising power circuit coupled to OUT via Q2, Figure 1) having a respective current limit set input (REF, Figure 1) and the second overload output (DRVL, Figure 1), the second overload output coupled to the interlock input of the first interlock logic circuit (DRVL coupled to input of 16, Figure 1); and
a second interlock logic circuit (Audy, comprising 18, 14, 22, Figure 1) having a second interlock input (input at 18 receiving control input Hlock, Figure 1), a second current limit input (REF, Figure 1) and a second current limit set output (Llock, Figure 1), the second current limit input coupled to the second overload output (DRVL, Figure 1), the second interlock input coupled to the first overload output (Hlock input to 18 coupled to DRVH, Figure 1), and the second current limit set output coupled to the respective current limit set input of the second port power path circuit (Llock coupled to REF via 22, Figure 1).
an interlock logic circuit (comprising 16, 12, 20, Figure 1) having an interlock input coupled to the control input (input at 16 receiving control input Llock, Figure 1), a current limit input (REF, Figure 1), and a current limit set output (Hlock, Figure 1), the interlock input adapted to be coupled to a second overload output of a second port power circuit (input receiving Llock coupled to a second port power circuit comprising 18, 14, 22, Figure 1),
Regarding Claim 39, Audy discloses an electronic device of Claim 37, wherein the power circuit is a first power circuit, the power output is a first power output, the overload output is a first overload output, the control input is a first control input, and the electronic device further comprises: a second port (OUT coupled when Q2 is conducting, Figure 1); a second power circuit having a second power input (input receiving inverted IN, Figure 1) coupled to the second port (IN coupled to OUT with Q1 conducting, Figure 1), a second power output (DRVL, Figure 1), a second overload output (Llock, Figure 1), and a second control input (input receiving Hlock, Figure 1), the second power input coupled to the first power input (the second input coupled to IN via inverter, Figure 1), the second overload output coupled to the first control input (Llock coupled to the first control input, Figure 1), and the second control input coupled to the first overload output (second control input coupled to Hlock, Figure 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US 2011/0316585) discloses an interlock circuit (Figures 1-13, Abstract) including input delay unit 100 (Figures 1-3) and output suppressing unit 200 (Figures 1, 3, 5-6); Chen et al. (US 2006/0125419) discloses a power supply control circuit with selectable current-limiting modes (Figures 1-3, Abstract); Perry et al. (US 2020/0303939) Discloses a multi-port charging system including charging logic circuit (Figures 1-4, Abstract); Todsen et al. (US 8,873,644) discloses an isolated modulator circuit including self-monitoring reset circuit (Figures 1-7, Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LUCY M THOMAS/Examiner, Art Unit 2838, 3/14/2026.
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838