DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of “a method of manufacturing microelectronic buildup redistribution layer system” in the reply filed on 06 March 2023 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant’s amendment to the claims on 06 March 2023 has been resulted in two different sets of claims, namely version 1, claims 1-17 and version 2, claims 1-18. Upon further clarification during the interview, the applicant has elected version 1, method claims 1-17 for prosecution.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 4, 9, 11, 14, 15 and 16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13, 16, 17, 14, 15, 18, 20 and 21 of copending Application Numbers 17/514,225, 17/515,402, 17/515,404 and 18/058,267. (reference application). Applicant also informed that claims of the copending applications 18/058,181 and 17/978,958 may be rejected on the grounds of nonstatutory double patenting rejection.
Claims 1-2, 4, 9, 11, 14, 15 and 16 of are not patentably distinct from each other of the copending 17/514,225, 17/515,402, 17/515,404 and 18/058,267 because following claims have identical limitations.
Instant Application 17/515,400
Copending Applications and corresponding conflicting claims:
17/514,225, 17/515,402, 17/515,404, and 18/058,267.
1. A method of manufacturing microelectronic buildup redistribution layer system comprising and providing a base substrate; A, forming a plurality of microelectronic redistribution layers on the base substrate, the redistributions layers including a dielectric layer and conductive (conductor) traces. B, forming a multi-layer structure by cross-linking or connecting layers by via conductor.
13. A method of manufacturing microelectronic buildup redistribution layer system comprising and providing a substrate; A, forming a plurality of microelectronic redistribution layers on the substrate, the redistributions layers including a dielectric layer and conductive (conductor) traces. B, forming a multi-layer structure by cross-linking or connecting layers by via conductor.
2. The method of claim 1, wherein providing the substrate includes providing the substrate including a through substrate vias and forming the redistribution layers include the conductive traces connected to the through substrate via.
16. The method of claim 13, wherein providing the substrate includes providing the substrate including a through substrate vias and forming the redistribution layers include the conductive traces connected to the through substrate via.
4. The method of claim 1, wherein the base carrier substrate is a ceramic material in construction of single or multi-layers.
17. The method of claim 13, wherein providing the substrate includes providing a ceramic substrate.
9. The method of claim 1, wherein forming the microelectronic redistribution layers includes the polymer layer as a polyimide-based polymer material.
14. The method of claim 13, wherein forming the microelectronic redistribution layers includes the polymer layer as a polyimide-based polymer material.
11. The method of claim 1, wherein the dielectric is an epoxy-based polymer material.
15. The method of claim 13, wherein forming the redistribution layers includes the polymer layer as an epoxy-based polymer material.
14. The method of claim 1, wherein the substrate is a polymer composite substrate.
18. The method of claim 13, wherein providing the substrate includes providing a polymer composite substrate.
15. The method of claim 1, wherein proving the substrate includes providing no lamination process for the multi-layered redistribution system.
20. The method of claim 13, wherein proving the substrate includes providing no lamination process for the multi-layered redistribution system.
16. The method of claim 1, wherein proving the substrate includes layer to layer buildup process for the multi-layered redistribution system.
21. The method of claim 13, wherein proving the substrate includes layer to layer buildup process for the multi-layered redistribution system.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Specification
The disclosure is objected to because of the following informalities:
Para. [31], line 7: “redistribution substate platform 300,” should read -- redistribution substrate platform 300, --
Para. [32], line 4: “test interface substate are” should read -- test interface substrates are --
Para. [41], line 3: “base substate 500” should read -- base substrate 500 --
Appropriate correction is required.
Claim Objections
Claim 1-17 are objected to because of several informalities. The Examiner recommends amending the claims 1-17 as follows to ensure proper format or form of claims, see MPEP 608.01(m) Form of Claims:
1. A method of manufacturing a microelectronic buildup redistribution layer system comprising:
providing a base carrier substrate;
forming a plurality of microelectronic redistribution layers on the base carrier substrate, wherein each redistribution layer comprises:
a dielectric layer, conductive traces, and
forming a multi-layer structure by cross-linking or connecting layers by via conductor.
2. The method of claim 1, wherein providing the base carrier substrate includes providing a substrate having a through substrate via and forming the redistribution layers having the conductive traces connected to the through substrate via.
3. The method of claim 1, wherein the via conductor provides an interlocking or connecting function with a top layer conductor or a bottom layer conductor.
4. The method of claim 1, wherein the base carrier substrate is a ceramic substrate having single or multi-layers.
5. The method of claim 1, wherein the base carrier substrate is an organic, printed circuit board material having single or multi-layers.
6. The method of claim 1, wherein the base carrier substrate is a wafer.
7. The method of claim 1, wherein the base carrier substrate is glass.
8. The method of claim 1, wherein the base carrier substrate is quartz.
9. The method of claim 1, wherein forming the microelectronic redistribution layer includes forming a polyimide-based polymer material.
10. The method of claim 1, wherein the dielectric layer is a polyimide-based polymer material.
11. The method of claim 1, wherein the dielectric layer is an epoxy-based polymer material.
12. The method of claim 1, wherein the dielectric layer is a resin-based polymer material.
13. The method of claim 1, wherein providing the base carrier substrate includes forming a through substrate via and connecting the via to a conductive trace.
14. The method of claim 1, wherein the base carrier substrate is a polymer composite substrate.
15. The method of claim 1, wherein the base carrier substrate has no lamination layers.
16. The method of claim 1, wherein proving the base carrier substrate includes layer to layer buildup process for the multi-layered redistribution layer system.
17. The method of claim 1, wherein proving the base carrier substrate includes layer level X and Y coordinate measurement, calculation, and adjustment on buildup process for the multi-layered redistribution layer system.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, line 2, the limitation “a base substrate” renders claim indefinite because it is unclear the recited “base substrate” is same as the “base carrier substrate” recited in claims 4-8. See specification para. [37], “Referring now to FIG. 4, therein is shown an embodiment of microelectronic test interface substrate system cross-sectional side view of the test interface base substrate system 500 of FIG. 1”, para. [31], “the wafer testing system 900 can include a mechanical stiffener 600, a printed circuit board 610, a redistribution test interface platform 700 consist of the base carrier substrate 500 and redistribution substrate platform 300”.
The limitation “forming a multi-layer structure by cross-linking or connecting layers by via conductor.” In claim 1, line 4 renders claim indefinite because claim or specification fails to define what a “cross-linking” or “interlocking” is. Further, claim 3 recites “The method of claim 1, wherein the via conductor provide an interlocking or connecting function” in which it is unclear how the recited “connecting layers by via conductor” provides “an interlocking” feature as recited in claim 3.
Claim 15 recites “method of claim 1, wherein proving the substrate includes providing no lamination process for the multi-layered redistribution system.” However, claim 16 recites “method of claim 1, wherein proving the substrate includes layer to layer buildup process for the multi-layered redistribution system.” It is unclear how “a layer to layer buildup process” has been enabled if there is “no lamination process” involved as recited in claim 15. Specification fails to point out a lamination process or a layer to layer buildup process as recited in claim 16.
The limitation “and adjustment on buildup process” in claim 17 renders claim indefinite because it is unclear how the recited adjustment has been enabled from a measured data. See para. [58], “interconnecting conductors 50 are almost perfectly aligned based on open buildup redistribution layer allows the X and Y coordinate measurement and ability to make the design adjustment for subsequent build up layers.” It is unclear how the internal coordinates are measured from the cross-sectional view as presented in Fig. 12, para. [57]. How does a cross-section view enable while manufacturing the redistribution layers? In other words, how the internal dimensions are measured before completing a buildup process?
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae (US 20190219613).
Bae reads on the claims as follows:
1. A method of manufacturing (Figs. 1 to 10) microelectronic buildup redistribution layer system (redistribution system 100, see Figs. 1, 2 below, and Fig. 10, para. [0083]) comprising and providing a base substrate (providing a substrate step 1002, Fig. 10, substrate 330, Fig. 3); A, forming a plurality of microelectronic redistribution layers (step 1004, Fig. 10, redistribution layers 320, Fig. 3) on the base substrate, the redistributions layers including a dielectric layer (dielectric layer 212, Fig. 3, step 1006, Fig. 10) and conductive (conductor) traces (routing traces 210, Fig. 3, step 1008, Fig. 10). B, forming a multi-layer structure by cross-linking or connecting layers by via conductor (via 332, Fig. 3).
[AltContent: textbox (via)][AltContent: arrow][AltContent: textbox (substrate)][AltContent: arrow]
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Figs. 2 and 3 Bae.
2. The method of claim 1, wherein providing the substrate includes providing the substrate including a through substrate vias (substrate vias 332, Fig. 3) and forming the redistribution layers include the conductive traces connected to the through substrate via (routing traces 210 can be electrically connect with the through substrate vias 332 on the first side of the substrate 330, para. [0040]).
3. The method of claim 1, wherein the via conductor provide an interlocking or connecting function with the top or bottom layer conductor (routing traces 210 can be electrically connect with the through substrate vias 332 on the first side of the substrate 330, para. [0040]; routing traces 210 embedded within the homogenous dielectric structure 212 can provide an interlocking function, para. [0077]).
4. The method of claim 1, wherein the base carrier substrate is a ceramic material (the substrate 330 can be formed from a ceramic based material, para. [0048]) in construction of single or multi-layers.
5. The method of claim 1, wherein the base carrier substrate is an organic, printed circuit board, material (Flame Retardant-4 (FR-4) grade printed circuit boards, para. [0048]) in construction of single or multi-layers.
6. The method of claim 1, wherein the base carrier substrate is a wafer (redistribution system 100 can be a component in a wafer testing system 120, para. [0025]).
9. The method of claim 1, wherein forming the microelectronic redistribution layers includes the polymer layer as a polyimide-based polymer material (see claim 14).
10. The method of claim 1, wherein the dielectric is a polyimide-based polymer material (see claim 4).
11. The method of claim 1, wherein the dielectric is an epoxy-based polymer material (see claim 5).
13. The method of claim 1, wherein the base carrier substrate includes a through substrate via (via 332, Fig. 3) in the substrate and connected to the conductor traces.
14. The method of claim 1, wherein the substrate is a polymer composite substrate (substrate 330 can be formed from a polymer composite based material, para. [0048]).
15. The method of claim 1, wherein proving the substrate includes providing no lamination process (redistribution layers 320 are individual layers that have been chemically bonded to one another, para. [0038]) for the multi-layered redistribution system.
16. The method of claim 1, wherein proving the substrate includes layer to layer buildup process (the application phase of the polymer buildup process, para. [0064]) for the multi-layered redistribution system.
17. The method of claim 1, wherein proving the substrate includes layer level X and Y coordinate measurement, calculation, and adjustment on buildup process for the multi-layered redistribution system (redistribution layer thickness 324 of the redistribution layers 320 can be measured in a direction that is perpendicular to the substrate first side 340 or the substrate second side 342, para. [0043]).
Claim(s) 1-7 and 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 20210272889).
Wu reads on the claims as follows:
1. A method of manufacturing (Figs. 1 to 26) microelectronic buildup redistribution layer system (redistribution structure 200, Fig. 1 below, para. [0018]) comprising and providing a base substrate (core substrate 300, Fig. 1); A, forming a plurality of microelectronic redistribution layers (first redistribution structure 200 includes protective layer 106 and redistribution layers 110, 120, 130, 140, 150, and 160, Fig. 6, para. [0037]) on the base substrate, the redistributions layers including a dielectric layer (redistribution layers 110, 120, 130, 140, 150, and 160 include both metallization patterns and dielectric layers, para. [0037]) and conductive (conductor) traces (metallization patterns 156 and 166 of redistribution layers 150, 160, para. [0038]). B, forming a multi-layer structure by cross-linking or connecting layers by via conductor (conductive vias 144, Fig. 9, para. [0038]).
[AltContent: textbox (substrate)][AltContent: textbox (redistribution layer)]
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Modified Fig. 1 Wu.
2. The method of claim 1, wherein providing the substrate includes providing the substrate including a through substrate vias (conductive vias 320, Figs. 1 and 10) and forming the redistribution layers include the conductive traces connected to the through substrate via (first redistribution structure 200 may be electrically and mechanically attached to the core substrate 300, para. [0018]).
3. The method of claim 1, wherein the via conductor provide an interlocking or connecting function with the top or bottom layer conductor (redistribution structures 340A and 340B are electrically coupled by the conductive vias 320, para. [0042]).
4. The method of claim 1, wherein the base carrier substrate is a ceramic material (core substrate 300 may be, e.g., an organic substrate, a ceramic substrate, para. [0041]) in construction of single or multi-layers.
5. The method of claim 1, wherein the base carrier substrate is an organic, printed circuit board, material (pre-preg, epoxy, para. [0042]) in construction of single or multi-layers.
6. The method of claim 1, wherein the base carrier substrate is a wafer (a silicon substrate, para. [0041]).
7. The method of claim 1, wherein the base carrier substrate is a glass (core substrate 300 includes a core 310. The core 310 may be formed of one or more layers of glass fiber, para. [0042]).
9. The method of claim 1, wherein forming the microelectronic redistribution layers includes the polymer layer as a polyimide-based polymer material (polyimide, para. [0034]).
10. The method of claim 1, wherein the dielectric is a polyimide-based polymer material (see para. [0034]).
11. The method of claim 1, wherein the dielectric is an epoxy-based polymer material (core substrate 300 includes a core 310. The core 310 may be formed of one or more layers of glass fiber, resin, filler, pre-preg, epoxy, silica filler, ABF, polyimide, molding compound, other materials, and/or combinations thereof, para. [0042]).
12. The method of claim 1, wherein the dielectric is a resin-based polymer material (resin, para. 0042]).
13. The method of claim 1, wherein the base carrier substrate includes a through substrate via (via 320, Fig. 1) in the substrate and connected to the conductor traces.
14. The method of claim 1, wherein the substrate is a polymer composite substrate (core substrate 300 includes a core 310. The core 310 may be formed of one or more layers of glass fiber, resin, filler, pre-preg, epoxy, silica filler, ABF, polyimide, molding compound, other materials, and/or combinations thereof, para. [0042]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 1 above, in view of Bae.
Regarding claims 15-17 Wu does not teach the recited limitations. However, Bae teaches,
15. The method of claim 1, wherein proving the substrate includes providing no lamination process (redistribution layers 320 are individual layers that have been chemically bonded to one another, para. [0038]) for the multi-layered redistribution system.
16. The method of claim 1, wherein proving the substrate includes layer to layer buildup process (the application phase of the polymer buildup process, para. [0064]) for the multi-layered redistribution system.
17. The method of claim 1, wherein proving the substrate includes layer level X and Y coordinate measurement, calculation, and adjustment on buildup process for the multi-layered redistribution system (redistribution layer thickness 324 of the redistribution layers 320 can be measured in a direction that is perpendicular to the substrate first side 340 or the substrate second side 342).
Therefore, in view of the teachings of Bae, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing a microelectronic redistribution structure taught by Wu to replace the fabrication process to a layer to layer buildup process and to include a measuring process as taught by Bae so that it enables to correct the layer dimensions during manufacturing a redistribution structure.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 1 above, in view of Takano (US 20190304888).
Regarding claim 8, Wu does not teach a quartz substrate. However, Takano teaches an electrode structure interposer in which,
wherein the base carrier substrate is a quartz (substrate 11 include a glass substrate, a glass ceramic substrate, a quartz substrate, a sapphire substrate, a resin substrate, a glass epoxy substrate, a silicon substrate, Fig. 2, para. [0075]).
Therefore, in view of the teachings of Takano, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of a microelectronic redistribution structure as taught by Wu to replace the substrate with a quartz substrate as taught by Takano so that it enables manufacturing of a redistribution structure on a quartz substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art of record Chen (US 20180005931) teaches a method for manufacturing a circuit redistribution structure including forming first dielectric on a carrier, conductive blind vias are formed in the first dielectric, and forming a plurality of circuit redistribution layers dielectric substrate.
Prior art of record Haba (US 20120267751) teaches a multilayer redistribution system comprising forming one or more redistribution layers by patterning conductive traces and vias on multilayer dielectric layers and interconnecting them.
Prior art of record Yang (US 20210305228) teaches a method of forming a redistribution structure including metallization patterns; encapsulating the semiconductor device with an encapsulant; forming openings in the encapsulant, and exposing a metallization pattern of the redistribution structure; and forming a conductive material in the openings.
Prior art of record Wu (US 20210098421) teaches a multilayer redistribution structure comprising layers of dielectric materials and conductive patterns and patterned conductive openings that interconnect between the layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
/PETER DUNGBA VO/Supervisory Patent Examiner of Art Unit 3729